Chapter9-Bootloader
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Addr 0000 0001 0002 0003 ...
EPRΒιβλιοθήκη BaiduM
DMA
CPU
PC=0003 PC=0002 PC=0001 PC=0000
L1D Cache C6211/C6711
When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero.
Chapter 9, Slide 7 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What happens at reset: System timeline
/RS pin
CPU Reset Device Reset CPU Reset Boot load in operation
Chapter 9, Slide 12
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Bootloader configuration
The boot mode is selected by pulling the HD[4:3] pins (HPI data bus pins) high or low at reset. Depending on the voltages on this pins one of the four modes is selected.
Chapter 9, Slide 11
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Bootloader operational modes
The TMS320C6211 and ‘C6711 support the following boot configurations:
On the rising edge of the /RS pin:
The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader. The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero.
(1) (2) (3) (4) Host Port Interface (HPI) boot. 8-bit ROM boot. 16-bit ROM boot. 1632-bit ROM boot. 32-
Note: with the ‘C6211 and ‘C6711 there is no “no“no-boot” mode as for the other ‘C6000 processors.
Boot modes and processes
Two questions need to be answered about the bootloader, these are:
What methods of boot are available and how are they selected? How does the DSP know what type of memory it is going to boot from?
Endianess configuration
The endian mode is determined at the same time as boot mode. Pulling pin HD[8] high or low selects the following endian modes.
HD[4:3] 00 01 10 11 Boot mode HPI boot 8-bit ROM boot 16-bit ROM boot 1632-bit ROM boot 32-
Chapter 9, Slide 13
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 9, Slide 3 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What is the bootloader?
VCC VCC Boot Config L1P Cache L2 Cache EMIF
What happens at reset: System timeline
/RS pin
CPU Reset Device Reset
When the device is held in reset:
The device is initialised to the default state. Most 3-state outputs are in the high 3impedance state.
Boot process: HPI boot mode
In this mode the following sequence is used:
The CPU is held in reset while the remaining of the device is released. The host processor initialises the CPU’s memory space through the HPI. When all the necessary memory is initialised the host processor takes the CPU out of reset by writing a ‘1’ to the DSPINT bit filed of the Host Port Interface Control (HPIC) register.
17 DSPINT
Chapter 9, Slide 16
HPIC
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Boot process: HPI boot mode
/RS Boot Config L1P Cache HPI L2 Cache HOST
Chapter 9, Slide 9
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
‘C6211 and ‘C6711 Memory map
Chapter 9, Slide 10
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 9, Slide 6
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What happens at reset: System timeline
/RS pin
CPU Reset Device Reset CPU Reset Boot load in operation
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
‘C6211 and ‘C6711 Memory map
The ‘C6211 and ‘C6711 has only one memory map, MAP0. Internal memory is always located at address zero. Internal memory can be used as either program or data.
Chapter 9, Slide 14 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Clock mode configuration
The input clock mode is also determined at the same time as boot mode. Pulling CLKMODE0 pin high or low selects the following modes.
EPROM
DMA
CPU
L1D Cache C6211/C6711
With the boot, a portion of code can be automatically copied from external to internal memory.
Chapter 9, Slide 5 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
CLKMODE0 PLL frequency multiplier 0 No multiplication 1 Input frequency is multiplied by 4
Chapter 9, Slide 15
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Once the boot loader has finished initialising the internal memory the CPU is taken out of reset. The CPU starts running from address zero.
Chapter 9, Slide 8
DRAM
EMIF
DMA
CPU
L1D Cache
C6211/C6711
Chapter 9, Slide 17
Chapter 9 Bootloader
Learning Objectives
Need for a bootloader. What happens during a reset. Boot modes and processes. Memory map.
Chapter 9, Slide 2
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
HD[8] 0 1 Device operation Big endian Little endian
Note: ensure that the software development tools are also configured with the same endian type as the hardware.
Chapter 9, Slide 4 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What is the bootloader?
VCC VCC Boot Config L1P Cache L2 Cache EMIF
What is the bootloader?
VCC VCC Boot Config L1P Cache L2 Cache EMIF
Addr 0000 0001 0002 0003 ...
EPROM
DMA
CPU
L1D Cache C6211/C6711
When the DSP is NOT powered or under reset the internal program memory is in a random state.
EPRΒιβλιοθήκη BaiduM
DMA
CPU
PC=0003 PC=0002 PC=0001 PC=0000
L1D Cache C6211/C6711
When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero.
Chapter 9, Slide 7 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What happens at reset: System timeline
/RS pin
CPU Reset Device Reset CPU Reset Boot load in operation
Chapter 9, Slide 12
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Bootloader configuration
The boot mode is selected by pulling the HD[4:3] pins (HPI data bus pins) high or low at reset. Depending on the voltages on this pins one of the four modes is selected.
Chapter 9, Slide 11
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Bootloader operational modes
The TMS320C6211 and ‘C6711 support the following boot configurations:
On the rising edge of the /RS pin:
The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader. The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero.
(1) (2) (3) (4) Host Port Interface (HPI) boot. 8-bit ROM boot. 16-bit ROM boot. 1632-bit ROM boot. 32-
Note: with the ‘C6211 and ‘C6711 there is no “no“no-boot” mode as for the other ‘C6000 processors.
Boot modes and processes
Two questions need to be answered about the bootloader, these are:
What methods of boot are available and how are they selected? How does the DSP know what type of memory it is going to boot from?
Endianess configuration
The endian mode is determined at the same time as boot mode. Pulling pin HD[8] high or low selects the following endian modes.
HD[4:3] 00 01 10 11 Boot mode HPI boot 8-bit ROM boot 16-bit ROM boot 1632-bit ROM boot 32-
Chapter 9, Slide 13
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 9, Slide 3 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What is the bootloader?
VCC VCC Boot Config L1P Cache L2 Cache EMIF
What happens at reset: System timeline
/RS pin
CPU Reset Device Reset
When the device is held in reset:
The device is initialised to the default state. Most 3-state outputs are in the high 3impedance state.
Boot process: HPI boot mode
In this mode the following sequence is used:
The CPU is held in reset while the remaining of the device is released. The host processor initialises the CPU’s memory space through the HPI. When all the necessary memory is initialised the host processor takes the CPU out of reset by writing a ‘1’ to the DSPINT bit filed of the Host Port Interface Control (HPIC) register.
17 DSPINT
Chapter 9, Slide 16
HPIC
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Boot process: HPI boot mode
/RS Boot Config L1P Cache HPI L2 Cache HOST
Chapter 9, Slide 9
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
‘C6211 and ‘C6711 Memory map
Chapter 9, Slide 10
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Chapter 9, Slide 6
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What happens at reset: System timeline
/RS pin
CPU Reset Device Reset CPU Reset Boot load in operation
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
‘C6211 and ‘C6711 Memory map
The ‘C6211 and ‘C6711 has only one memory map, MAP0. Internal memory is always located at address zero. Internal memory can be used as either program or data.
Chapter 9, Slide 14 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Clock mode configuration
The input clock mode is also determined at the same time as boot mode. Pulling CLKMODE0 pin high or low selects the following modes.
EPROM
DMA
CPU
L1D Cache C6211/C6711
With the boot, a portion of code can be automatically copied from external to internal memory.
Chapter 9, Slide 5 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
CLKMODE0 PLL frequency multiplier 0 No multiplication 1 Input frequency is multiplied by 4
Chapter 9, Slide 15
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Once the boot loader has finished initialising the internal memory the CPU is taken out of reset. The CPU starts running from address zero.
Chapter 9, Slide 8
DRAM
EMIF
DMA
CPU
L1D Cache
C6211/C6711
Chapter 9, Slide 17
Chapter 9 Bootloader
Learning Objectives
Need for a bootloader. What happens during a reset. Boot modes and processes. Memory map.
Chapter 9, Slide 2
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
HD[8] 0 1 Device operation Big endian Little endian
Note: ensure that the software development tools are also configured with the same endian type as the hardware.
Chapter 9, Slide 4 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
What is the bootloader?
VCC VCC Boot Config L1P Cache L2 Cache EMIF
What is the bootloader?
VCC VCC Boot Config L1P Cache L2 Cache EMIF
Addr 0000 0001 0002 0003 ...
EPROM
DMA
CPU
L1D Cache C6211/C6711
When the DSP is NOT powered or under reset the internal program memory is in a random state.