Microcontroller Instruction SetFor interrupt response time information, refer to the hardware description chapter.Note:1.Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW orbits in the PSW) also affect flag settings.Instructions that Affect Flag Settings (1)InstructionFlag InstructionFlag COV AC C OVACADD X X X CLR C O ADDC XX X CPL C X SUBB X X XANL C,bit X MUL O X ANL C,/bit X DIV O XORL C,bit X DA X ORL C,/bit X RRC X MOV C,bit X RLC X CJNE XSETB C 1The Instruction Set and Addressing ModesR n Register R7-R0 of the currently selected Register Bank.direct8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)].@R i 8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0.#data 8-bit constant included in instruction.#data 1616-bit constant included in instruction.addr 1616-bit destination address. Used by LCALL and LJMP . A branch can be anywhere within the 64K byte Program Memory address space.addr 1111-bit destination address. Used by ACALL and AJMP . The branch will be within the same 2K byte page of program memory as the first byte of the following instruction.relSigned (two’s complement) 8-bit offset byte. Used by SJMP and allconditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.bitDirect Addressed bit in Internal Data RAM or Special Function Register.Instruction Set SummaryNote:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle12345670NOPJBC bit,rel [3B, 2C]JB bit, rel [3B, 2C]JNB bit, rel [3B, 2C]JC rel [2B, 2C]JNC rel [2B, 2C]JZ rel [2B, 2C]JNZ rel [2B, 2C]1AJMP (P0)[2B, 2C]ACALL (P0)[2B, 2C]AJMP (P1)[2B, 2C]ACALL (P1)[2B, 2C]AJMP (P2)[2B, 2C]ACALL (P2)[2B, 2C]AJMP (P3)[2B, 2C]ACALL (P3)[2B, 2C]2LJMP addr16[3B, 2C]LCALL addr16[3B, 2C]RET [2C]RETI [2C]ORL dir, A [2B]ANL dir, A [2B]XRL dir, a [2B]ORL C, bit [2B, 2C]3RR A RRC A RL A RLC A ORL dir, #data [3B, 2C]ANL dir, #data [3B, 2C]XRL dir, #data [3B, 2C]JMP @A + DPTR[2C]4INC A DEC A ADD A, #data [2B]ADDC A, #data [2B]ORL A, #data [2B]ANL A, #data [2B]XRL A, #data [2B]MOV A, #data [2B]5INC dir [2B]DEC dir [2B]ADD A, dir [2B]ADDC A, dir [2B]ORL A, dir [2B]ANL A, dir [2B]XRL A, dir [2B]MOV dir, #data [3B, 2C]6INC @R0DEC @R0ADD A, @R0ADDC A, @R0ORL A, @R0ANL A, @R0XRL A, @R0MOV @R0, @data[2B]7INC @R1DEC @R1ADD A, @R1ADDC A, @R1ORL A, @R1ANL A, @R1XRL A, @R1MOV @R1, #data[2B]8INC R0DEC R0ADD A, R0ADDC A, R0ORL A, R0ANL A, R0XRL A, R0MOV R0, #data [2B]9INC R1DEC R1ADD A, R1ADDC A, R1ORL A, R1ANL A, R1XRL A, R1MOV R1, #data [2B]AINC R2DEC R2ADD A, R2ADDC A, R2ORL A, R2ANL A, R2XRL A, R2MOV R2, #data [2B]BINC R3DEC R3ADD A, R3ADDC A, R3ORL A, R3ANL A, R3XRL A, R3MOV R3, #data [2B]CINC R4DEC R4ADD A, R4ADDC A, R4ORL A, R4ANL A, R4XRL A, R4MOV R4, #data [2B]DINC R5DEC R5ADD A, R5ADDC A, R5ORL A, R5ANL A, R5XRL A, R5MOV R5, #data [2B]EINC R6DEC R6ADD A, R6ADDC A, R6ORL A, R6ANL A, R6XRL A, R6MOV R6, #data [2B]FINC R7DEC R7ADD A, R7ADDC A, R7ORL A, R7ANL A, R7XRL A, R7MOV R7, #data [2B]Instruction SetInstruction Set Summary (Continued)Note:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle89A B C D E F 0SJMP REL [2B, 2C]MOV DPTR,#data 16[3B, 2C]ORL C, /bit [2B, 2C]ANL C, /bit [2B, 2C]PUSH dir [2B, 2C]POP dir [2B, 2C]MOVX A,@DPTR [2C]MOVX @DPTR, A[2C]1AJMP (P4)[2B, 2C]ACALL (P4)[2B, 2C]AJMP (P5)[2B, 2C]ACALL (P5)[2B, 2C]AJMP (P6)[2B, 2C]ACALL (P6)[2B, 2C]AJMP (P7)[2B, 2C]ACALL (P7)[2B, 2C]2ANL C, bit [2B, 2C]MOV bit, C [2B, 2C]MOV C, bit [2B]CPL bit [2B]CLR bit [2B]SETB bit [2B]MOVX A, @R0[2C]MOVX wR0, A [2C]3MOVC A,@A + PC [2C]MOVC A,@A + DPTR[2C]INC DPTR [2C]CPL C CLR C SETB C MOVX A, @RI [2C]MOVX @RI, A [2C]4DIV AB [2B, 4C]SUBB A, #data [2B]MUL AB [4C]CJNE A,#data, rel [3B, 2C]SWAP A DA A CLR A CPL A 5MOV dir, dir [3B, 2C]SUBB A, dir [2B]CJNE A, dir, rel [3B, 2C]XCH A, dir [2B]DJNZ dir, rel [3B, 2C]MOV A, dir [2B]MOV dir, A [2B]6MOV dir, @R0[2B, 2C]SUBB A, @R0MOV @R0, dir [2B, 2C]CJNE@R0, #data, rel[3B, 2C]XCH A, @R0XCHD A, @R0MOV A, @R0MOV @R0, A 7MOV dir, @R1[2B, 2C]SUBB A, @R1MOV @R1, dir [2B, 2C]CJNE@R1, #data, rel[3B, 2C]XCH A, @R1XCHD A, @R1MOV A, @R1MOV @R1, A 8MOV dir, R0[2B, 2C]SUBB A, R0MOV R0, dir [2B, 2C]CJNE R0, #data, rel [3B, 2C]XCH A, R0DJNZ R0, rel [2B, 2C]MOV A, R0MOV R0, A 9MOV dir, R1[2B, 2C]SUBB A, R1MOV R1, dir [2B, 2C]CJNE R1, #data, rel [3B, 2C]XCH A, R1DJNZ R1, rel [2B, 2C]MOV A, R1MOV R1, A AMOV dir, R2[2B, 2C]SUBB A, R2MOV R2, dir [2B, 2C]CJNE R2, #data, rel [3B, 2C]XCH A, R2DJNZ R2, rel [2B, 2C]MOV A, R2MOV R2, A BMOV dir, R3[2B, 2C]SUBB A, R3MOV R3, dir [2B, 2C]CJNE R3, #data, rel [3B, 2C]XCH A, R3DJNZ R3, rel [2B, 2C]MOV A, R3MOV R3, A CMOV dir, R4[2B, 2C]SUBB A, R4MOV R4, dir [2B, 2C]CJNE R4, #data, rel [3B, 2C]XCH A, R4DJNZ R4, rel [2B, 2C]MOV A, R4MOV R4, A DMOV dir, R5[2B, 2C]SUBB A, R5MOV R5, dir [2B, 2C]CJNE R5, #data, rel [3B, 2C]XCH A, R5DJNZ R5, rel [2B, 2C]MOV A, R5MOV R5, A EMOV dir, R6[2B, 2C]SUBB A, R6MOV R6, dir [2B, 2C]CJNE R6, #data, rel [3B, 2C]XCH A, R6DJNZ R6, rel [2B, 2C]MOV A, R6MOV R6. A FMOV dir, R7[2B, 2C]SUBB A, R7MOV R7, dir [2B, 2C]CJNE R7, #data, rel [3B, 2C]XCH A, R7DJNZ R7, rel [2B, 2C]MOV A, R7MOV R7, ATable 1. AT89 Instruction Set Summary (1)Note: 1.All mnemonics copyrighted © Intel Corp., 1980.MnemonicDescriptionByteOscillator PeriodARITHMETIC OPERATIONS ADD A,R n Add register to Accumulator 112ADD A,direct Add direct byte to Accumulator 212ADD A,@R i Add indirect RAM to Accumulator112ADD A,#data Add immediate data to Accumulator212ADDC A,R n Add register toAccumulator with Carry 112ADDC A,direct Add direct byte toAccumulator with Carry 212ADDC A,@R i Add indirect RAM to Accumulator with Carry 112ADDC A,#data Add immediate data to Acc with Carry 212SUBB A,R n Subtract Register from Acc with borrow112SUBB A,direct Subtract direct byte from Acc with borrow 212SUBB A,@R i Subtract indirect RAM from ACC with borrow 112SUBB A,#data Subtract immediate data from Acc with borrow 212INC A Increment Accumulator 112INC R n Increment register 112INC direct Increment direct byte 212INC @R i Increment direct RAM 112DEC A Decrement Accumulator 112DEC R n Decrement Register 112DEC direct Decrement direct byte 212DEC @R i Decrement indirect RAM 112INC DPTR Increment Data Pointer 124MUL AB Multiply A & B 148DIV AB Divide A by B 148DAADecimal Adjust Accumulator112MnemonicDescriptionByteOscillator PeriodLOGICAL OPERATIONSANL A,R n AND Register to Accumulator 112ANL A,direct AND direct byte to Accumulator 212ANL A,@R i AND indirect RAM to Accumulator112ANL A,#data AND immediate data to Accumulator 212ANL direct,A AND Accumulator to direct byte212ANL direct,#data AND immediate data to direct byte 324ORL A,R n OR register to Accumulator 112ORL A,direct OR direct byte to Accumulator 212ORL A,@R i OR indirect RAM to Accumulator112ORL A,#data OR immediate data to Accumulator212ORL direct,A OR Accumulator to direct byte212ORL direct,#data OR immediate data to direct byte324XRLA,R nExclusive-OR register to Accumulator112XRL A,direct Exclusive-OR direct byte to Accumulator 212XRLA,@R iExclusive-OR indirect RAM to Accumulator 112XRL A,#data Exclusive-OR immediate data to Accumulator 212XRLdirect,AExclusive-ORAccumulator to direct byte212XRL direct,#data Exclusive-OR immediate data to direct byte 324CLR A Clear Accumulator 112CPL A Complement Accumulator112RL A Rotate Accumulator Left 112RLCARotate Accumulator Left through the Carry112LOGICAL OPERATIONS (continued)Instruction SetRR A Rotate Accumulator Right112RRC A Rotate Accumulator Right through the Carry 112SWAPASwap nibbles within the Accumulator112DATA TRANSFER MOV A,R n Move register to Accumulator 112MOV A,direct Move direct byte to Accumulator212MOV A,@R i Move indirect RAM to Accumulator112MOV A,#data Move immediate data to Accumulator212MOV R n ,A Move Accumulator to register112MOV R n ,direct Move direct byte to register224MOV R n ,#data Move immediate data to register212MOV direct,A Move Accumulator to direct byte212MOV direct,R n Move register to direct byte224MOV direct,direct Move direct byte to direct 324MOV direct,@R i Move indirect RAM to direct byte224MOV direct,#data Move immediate data to direct byte324MOV @R i ,A Move Accumulator to indirect RAM 112MOV @R i ,direct Move direct byte to indirect RAM224MOV @R i ,#dataMove immediate data to indirect RAM212MOVDPTR,#data16Load Data Pointer with a16-bit constant324MOVC A,@A+DPTR Move Code byte relative to DPTR to Acc124MOVC A,@A+PC Move Code byte relative to PC to Acc124MOVXA,@R iMove External RAM (8-bit addr) to Acc124DATA TRANSFER (continued)Mnemonic Description Byte Oscillator PeriodMOVX A,@DPTR Move Exernal RAM (16-bit addr) to Acc 124MOVX @R i ,A Move Acc to External RAM (8-bit addr) 124MOVX @DPTR,A Move Acc to External RAM (16-bit addr)124PUSHdirectPush direct byte onto stack224POPdirect Pop direct byte from stack224XCHA,R n Exchange register with Accumulator112XCHA,direct Exchange direct byte with Accumulator 212XCHA,@R i Exchange indirect RAM with Accumulator 112XCHDA,@R i Exchange low-order Digit indirect RAM with Acc112BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry 112CLR bit Clear direct bit 212SETB C Set Carry 112SETB bit Set direct bit 212CPL C Complement Carry 112CPL bit Complement direct bit 212ANL C,bit AND direct bit to CARRY 224ANL C,/bit AND complement of direct bit to Carry 224ORL C,bit OR direct bit to Carry 224ORL C,/bit OR complement of direct bit to Carry224MOV C,bit Move direct bit to Carry 212MOV bit,C Move Carry to direct bit 224JC rel Jump if Carry is set 224JNC rel Jump if Carry not set 224JB bit,rel Jump if direct Bit is set 324JNB bit,rel Jump if direct Bit is Not set324JBCbit,relJump if direct Bit is set & clear bit324PROGRAM BRANCHINGMnemonic DescriptionByte Oscillator PeriodACALL addr11Absolute Subroutine Call 224LCALL addr16Long Subroutine Call 324RET Return from Subroutine 124RETI Return from interrupt 124AJMP addr11Absolute Jump 224LJMP addr16Long Jump324SJMP rel Short Jump (relative addr)224JMP @A+DPTR Jump indirect relative to the DPTR124JZ rel Jump if Accumulator is Zero224JNZ rel Jump if Accumulator is Not Zero224CJNEA,direct,relCompare direct byte to Acc and Jump if Not Equal324CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal324CJNER n ,#data,relCompare immediate to register and Jump if Not Equal324CJNE@R i ,#data,relCompare immediate to indirect and Jump if Not Equal324DJNZ R n ,rel Decrement register and Jump if Not Zero 224DJNZ direct,rel Decrement direct byte and Jump if Not Zero 324NOPNo Operation112Mnemonic DescriptionByte Oscillator PeriodInstruction Set Table 2. Instruction Opcodes in Hexadecimal OrderHex Code Numberof BytesMnemonic Operands001NOP012AJMP code addr023LJMP code addr031RR A041INC A052INC data addr061INC@R0071INC@R1081INC R0091INC R10A1INC R20B1INC R30C1INC R40D1INC R50E1INC R60F1INC R7103JBC bit addr,code addr 112ACALL code addr123LCALL code addr131RRC A141DEC A152DEC data addr161DEC@R0171DEC@R1181DEC R0191DEC R11A1DEC R21B1DEC R31C1DEC R41D1DEC R51E1DEC R61F1DEC R7203JB bit addr,code addr 212AJMP code addr221RET231RL A242ADD A,#data252ADD A,data addr HexCodeNumberof BytesMnemonic Operands261ADD A,@R0271ADD A,@R1281ADD A,R0291ADD A,R12A1ADD A,R22B1ADD A,R32C1ADD A,R42D1ADD A,R52E1ADD A,R62F1ADD A,R7303JNB bit addr,code addr 312ACALL code addr321RETI331RLC A342ADDC A,#data352ADDC A,data addr361ADDC A,@R0371ADDC A,@R1381ADDC A,R0391ADDC A,R13A1ADDC A,R23B1ADDC A,R33C1ADDC A,R43D1ADDC A,R53E1ADDC A,R63F1ADDC A,R7402JC code addr412AJMP code addr422ORL data addr,A433ORL data addr,#data 442ORL A,#data452ORL A,data addr461ORL A,@R0471ORL A,@R1481ORL A,R0491ORL A,R14A1ORL A,R24B 1ORL A,R34C 1ORL A,R44D 1ORL A,R54E 1ORL A,R64F 1ORL A,R7502JNC code addr 512ACALL code addr 522ANL data addr,A 533ANL data addr,#data 542ANL A,#data 552ANL A,data addr 561ANL A,@R0571ANL A,@R1581ANL A,R0591ANL A,R15A 1ANL A,R25B 1ANL A,R35C 1ANL A,R45D 1ANL A,R55E 1ANL A,R65F 1ANL A,R7602JZ code addr 612AJMP code addr 622XRL data addr,A 633XRL data addr,#data 642XRL A,#data 652XRL A,data addr 661XRL A,@R0671XRL A,@R1681XRL A,R0691XRL A,R16A 1XRL A,R26B 1XRL A,R36C 1XRL A,R46D 1XRL A,R56E 1XRL A,R66F 1XRL A,R7702JNZcode addrHex Code Number of BytesMnemonic Operands 712ACALL code addr 722ORL C,bit addr 731JMP @A+DPTR 742MOV A,#data 753MOV data addr,#data 762MOV @R0,#data 772MOV @R1,#data 782MOV R0,#data 792MOV R1,#data 7A 2MOV R2,#data 7B 2MOV R3,#data 7C 2MOV R4,#data 7D 2MOV R5,#data 7E 2MOV R6,#data 7F 2MOV R7,#data 802SJMP code addr 812AJMP code addr 822ANL C,bit addr 831MOVC A,@A+PC 841DIV AB853MOV data addr,data addr 862MOV data addr,@R0872MOV data addr,@R1882MOV data addr,R0892MOV data addr,R18A 2MOV data addr,R28B 2MOV data addr,R38C 2MOV data addr,R48D 2MOV data addr,R58E 2MOV data addr,R68F 2MOV data addr,R7903MOV DPTR,#data 912ACALL code addr 922MOV bit addr,C 931MOVC A,@A+DPTR 942SUBB A,#data 952SUBB A,data addr 961SUBBA,@R0Hex Code Number of BytesMnemonic OperandsInstruction Set971SUBB A,@R1981SUBB A,R0991SUBB A,R19A 1SUBB A,R29B 1SUBB A,R39C 1SUBB A,R49D 1SUBB A,R59E 1SUBB A,R69F 1SUBB A,R7A02ORL C,/bit addr A12AJMP code addr A22MOV C,bit addr A31INC DPTR A41MUL ABA5reserved A62MOV @R0,data addr A72MOV @R1,data addr A82MOV R0,data addr A92MOV R1,data addr AA 2MOV R2,data addr AB 2MOV R3,data addr AC 2MOV R4,data addr AD 2MOV R5,data addr AE 2MOV R6,data addr AF 2MOV R7,data addr B02ANL C,/bit addr B12ACALL code addr B22CPL bit addr B31CPL CB43CJNE A,#data,code addr B53CJNE A,data addr,code addr B63CJNE @R0,#data,code addr B73CJNE @R1,#data,code addr B83CJNE R0,#data,code addr B93CJNE R1,#data,code addr BA 3CJNE R2,#data,code addr BB 3CJNE R3,#data,code addr BC3CJNER4,#data,code addr Hex Code Number of BytesMnemonic Operands BD 3CJNE R5,#data,code addr BE 3CJNE R6,#data,code addr BF 3CJNE R7,#data,code addr C02PUSH data addr C12AJMP code addr C22CLR bit addr C31CLR C C41SWAP AC52XCH A,data addr C61XCH A,@R0C71XCH A,@R1C81XCH A,R0C91XCH A,R1CA 1XCH A,R2CB 1XCH A,R3CC 1XCH A,R4CD 1XCH A,R5CE 1XCH A,R6CF 1XCH A,R7D02POP data addr D12ACALL code addr D22SETB bit addr D31SETB C D41DA AD53DJNZ data addr,code addr D61XCHD A,@R0D71XCHD A,@R1D82DJNZ R0,code addr D92DJNZ R1,code addr DA 2DJNZ R2,code addr DB 2DJNZ R3,code addr DC 2DJNZ R4,code addr DD 2DJNZ R5,code addr DE 2DJNZ R6,code addr DF 2DJNZ R7,code addr E01MOVX A,@DPTR E12AJMP code addr E21MOVXA,@R0Hex Code Number of BytesMnemonic OperandsE31MOVX A,@R1E41CLR AE52MOV A,data addr E61MOV A,@R0E71MOV A,@R1E81MOV A,R0E91MOV A,R1EA 1MOV A,R2EB 1MOV A,R3EC 1MOV A,R4ED 1MOV A,R5EE 1MOV A,R6EF 1MOV A,R7F01MOVX @DPTR,A F12ACALL code addr F21MOVX @R0,A F31MOVX @R1,A F41CPL AF52MOV data addr,A F61MOV @R0,A F71MOV @R1,A F81MOV R0,A F91MOV R1,A FA 1MOV R2,A FB 1MOV R3,A FC 1MOV R4,A FD 1MOV R5,A FE 1MOV R6,A FF1MOVR7,AHex Code Number of BytesMnemonic OperandsInstruction SetInstruction DefinitionsACALL addr11Function:Absolute CallDescription:ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-orderbyte first) and increments the Stack Pointer twice. The destination address is obtained by successivelyconcatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of theinstruction. The subroutine called must therefore start within the same 2 K block of the program memory as thefirst byte of the instruction following ACALL. No flags are affected.Example:Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the following instruction,ACALL SUBRTNat location 0123H, SP contains 09H, internal RAM locations 08H and 09H will contain 25H and 01H, respectively,and the PC contains 0345H.Bytes:2Cycles:2Encoding:a10a9a810001a7a6a5a4a3a2a1a0Operation:ACALL(PC) ← (PC) + 2(SP) ← (SP) + 1((SP)) ← (PC7-0)(SP) ← (SP) + 1((SP)) ← (PC15-8)(PC10-0) ← page addressADD A,<src-byte>Function:AddDescription:ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. Whenadding unsigned integers, the carry flag indicates an overflow occurred.OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV iscleared. When adding signed integers, OV indicates a negative number produced as the sum of two positiveoperands, or a positive sum from two negative operands.Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.Example:The Accumulator holds 0C3H (1100001lB), and register 0 holds 0AAH (10101010B). The following instruction, ADD A,R0leaves 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1. ADD A,R nBytes:1Cycles:1Encoding:00101r r rOperation:ADD(A) ← (A) + (R n)ADD A,directBytes:2Cycles:1Encoding:00100101direct addressOperation:ADD(A)← (A) + (direct)ADD A,@R iBytes:1Cycles:1Encoding:0010011iOperation:ADD(A) ← (A) + ((R i))ADD A,#dataBytes:2Cycles:1Encoding:00100100immediate dataOperation:ADD(A)← (A) + #dataInstruction SetADDC A, <src-byte>Function:Add with CarryDescription:ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OVis cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positiveoperands or a positive sum from two negative operands.Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.Example:The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) with the carry flag set. The following instruction,ADDC A,R0leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV set to 1.ADDC A,R nBytes:1Cycles:1Encoding:00111r r rOperation:ADDC(A) ← (A) + (C) + (R n)ADDC A,directBytes:2Cycles:1Encoding:00110101direct addressOperation:ADDC(A)← (A) + (C) + (direct)ADDC A,@R iBytes:1Cycles:1Encoding:0011011iOperation:ADDC(A) ← (A) + (C) + ((R i))ADDC A,#dataBytes:2Cycles:1Encoding:00110100immediate dataOperation:ADDC(A)← (A) + (C) + #dataAJMP addr11Function:Absolute JumpDescription:AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte ofthe instruction. The destination must therfore be within the same 2 K block of program memory as the first byte ofthe instruction following AJMP.Example:The label JMP ADR is at program memory location 0123H. The following instruction,AJMP JMP ADRis at location 0345H and loads the PC with 0123H.Bytes:2Cycles:2Encoding:a10a9a800001a7a6a5a4a3a2a1a0Operation:AJMP(PC) ← (PC) + 2(PC10-0) ← page addressANL<dest-byte>,<src-byte>Function:Logical-AND for byte variablesDescription:ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected.The two operands allow six addressing mode combinations. When the destination is the Accumulator, the sourcecan use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, thesource can be the Accumulator or immediate data.Note: When this instruction is used to modify an output port, the value used as the original port data will be readfrom the output data latch, not the input pins.Example:If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B), then the following instruction,ANL A,R0leaves 41H (01000001B) in the Accumulator.When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAMlocation or hardware register. The mask byte determining the pattern of bits to be cleared would either be aconstant contained in the instruction or a value computed in the Accumulator at run-time. The followinginstruction,ANL P1,#01110011Bclears bits 7, 3, and 2 of output port 1.ANL A,R nBytes:1Cycles:1Encoding:01011r r rOperation:ANL(A) ← (A) ∧ (R n)Instruction SetANL A,directBytes:2Cycles:1Encoding:01010101direct addressOperation:ANL(A)← (A) ∧ (direct)ANL A,@R iBytes:1Cycles:1Encoding:0101011iOperation:ANL(A) ← (A) ∧ ((R i))ANL A,#dataBytes:2Cycles:1Encoding:01010100immediate dataOperation:ANL(A)← (A) ∧ #dataANL direct,ABytes:2Cycles:1Encoding:01010010direct addressOperation:ANL(direct)← (direct) ∧ (A)ANL direct,#dataBytes:3Cycles:2Encoding:01010011direct address immediate data Operation:ANL(direct) ← (direct) ∧ #dataANL C,<src-bit>Function:Logical-AND for bit variablesDescription:If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicatesthat the logical complement of the addressed bit is used as the source value, but the source bit itself is notaffected. No other flags are affected.Only direct addressing is allowed for the source operand.Example:Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:MOV C,P1.0;LOAD CARRY WITH INPUT PIN ST A TEANL C,ACC.7;AND CARRY WITH ACCUM. BIT 7ANL C,/OV;AND WITH INVERSE OF OVERFLOW FLAGANL C,bitBytes:2Cycles:2Encoding:10000010bit addressOperation:ANL(C)← (C) ∧ (bit)ANL C,/bitBytes:2Cycles:2Encoding:10110000bit addressOperation:ANL(C)← (C) ∧ (bit)Instruction SetCJNE <dest-byte>,<src-byte>, relFunction:Compare and Jump if Not Equal.Description:CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, afterincrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of<dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neitheroperand is affected.The first two operands allow four addressing mode combinations: the Accumulator may be compared with anydirectly addressed byte or immediate data, and any indirect RAM location or working register can be comparedwith an immediate constant.Example:The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,CJNE R7, # 60H, NOT_EQ;. . . . . . . . ;R7 = 60H.NOT_EQ: JC REQ_LOW;IF R7 < 60H.;. . . . . . . . ;R7 > 60H.sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instructiondetermines whether R7 is greater or less than 60H.If the data being presented to Port 1 is also 34H, then the following instruction,WAIT:CJNE A, P1,WAITclears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal thedata read from P1. (If some other value was being input on P1, the program loops at this point until the P1 datachanges to 34H.)CJNE A,direct,relBytes:3Cycles:2Encoding:10110101direct address rel.addressOperation:(PC)← (PC) + 3IF (A) < > (direct)THEN(PC) ← (PC) + relative offsetIF (A) < (direct)THEN(C) ← 1ELSE(C) ← 0CJNE A,#data,relBytes:3Cycles:2Encoding:10110100immediate data rel.address Operation:(PC)← (PC) + 3IF (A) < > dataTHEN(PC) ← (PC) + relative offsetIF (A) < dataTHEN(C) ← 1ELSE(C) ← 0CJNE R n,#data,relBytes:3Cycles:2Encoding:10111r r r immediate data rel. address Operation:(PC) ← (PC) + 3IF (R n) < > dataTHEN(PC) ← (PC) + relative offsetIF (R n) < dataTHEN(C) ← 1ELSE(C) ← 0CJNE @R i,data,relBytes:3Cycles:2Encoding:1011011i immediate data rel.address Operation:(PC)← (PC) + 3IF ((R i)) < > dataTHEN(PC) ← (PC) + relative offsetIF ((R i)) < dataTHEN(C) ← 1ELSE(C) ← 0Instruction SetCLR AFunction:Clear AccumulatorDescription:CLR A clears the Accumulator (all bits set to 0). No flags are affectedExample:The Accumulator contains 5CH (01011100B). The following instruction,CLR Aleaves the Accumulator set to 00H (00000000B).Bytes:1Cycles:1Encoding:11100100Operation:CLR(A) ← 0CLR bitFunction:Clear bitDescription:CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit.Example:Port 1 has previously been written with 5DH (01011101B). The following instruction,CLR P1.2 leaves the port set to 59H (01011001B).CLR CBytes:1Cycles:1Encoding:11000011Operation:CLR(C) ← 0CLR bitBytes:2Cycles:1Encoding:11000010bit addressOperation:CLR(bit)← 0CPL AFunction:Complement AccumulatorDescription:CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a1 are changed to a 0 and vice-versa. No flags are affected.Example:The Accumulator contains 5CH (01011100B). The following instruction,CPL Aleaves the Accumulator set to 0A3H (10100011B).Bytes:1Cycles:1Encoding:11110100Operation:CPL(A) ← (A)CPL bitFunction:Complement bitDescription:CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.Note: When this instruction is used to modify an output pin, the value used as the original data is read from theoutput data latch, not the input pin.Example:Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,CPL P1.1CPL P1.2 leaves the port set to 5BH (01011011B).CPL CBytes:1Cycles:1Encoding:10110011Operation:CPL(C) ← (C)CPL bitBytes:2Cycles:1Encoding:10110010bit addressOperation:CPL(bit)← (bit)。
