CAT28F010TR-70T中文资料

Dimensions of CNY70 in mm95 11345www.vishay.Document Number 83751Ozone Depleting Substances Policy StatementIt is the policy of Vishay Semiconductor GmbH to1.Meet all present and future national and international statutory requirements.2.Regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.1.Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively2.Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the EnvironmentalProtection Agency (EPA) in the USA3.Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Telefunken products for any unintended or unauthorized application, the buyer shall indemnify Vishay Telefunken against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, GermanyTelephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423Document Number 83751。

The RMC70 Base module includes CPU, communications, and one or two motion axes. Up to four Expansion modules can be added (e.g. analog inputs and DI/O).FeaturesCommand-based—minimal program development and The din-rail mountable RMC75Base module is just 3.22” x 5.00”Motion Control…and More.p.2Printed in USA 6/11EXP70-AP2RMC70 Series Ordering InformationRMC70 Base ModuleCPU ModuleR MC75E = RMC75 with Ethernet communications and USB monitor port ................................ p. 6 RMC75P = RMC75 with PROFIBUS-DP communications and RS-232 monitor port .................... p. 6 RMC75S = RMC75 with serial RS-232/485 communications and RS-232 monitor port ............. p .7Axis ModuleAA1 = Analog input (±10 V or 4-20 mA), ±10 V analog control output, 1 axis ............................ p .9 AA2 = Analog input (±10 V or 4-20 mA), ±10 V analog control output, 2 axes ........................... p .9 MA1 = Magnetostrictive (Start/Stop, PWM) or SSI input, ±10 V analog control output, 1 axis .. p .10 MA2 = Magnetostrictive (Start/Stop, PWM) or SSI input, ±10 V analog control output, 2 axes . p .10 QA1 = Quadrature encoder input (5 V differential), ±10 V analog control output, 1 axis .......... p .11 QA2 = Quadrature encoder input (5 V differential), ±10 V analog control output, 2 axes ......... p .11RMC70 Expansion ModulesExpansion ModuleA2 = 2 analog reference inputs (±10 V or 4-20 mA) ............................................................. p .13 AP2 = 2 analog inputs (±10 V or 4-20 mA) for position-pressure and position-force control.... p .13 D8 = 8 discrete I/O, 12-24 VDC, software configurable ....................................................... p .14 Q1 = ½–axis quadrature reference input (5 V differential) .................................................. p .15Mounting Dimensions ........................................... p . 18Voltage-to-Current Converters................................. p . 19 Cable Assemblies .................................................. p . 19 Terminal Blocks ..................................................... p . 19RMC75E-MA2Ethernet communications with 2 axes ofmagnetostrictive (Start/Stop or PWM) or SSI feedback. RMC75P-QA1PROFIBUS communications with 1 axis of quadrature encoder feedback. EXP70-D8 8 discrete I/OCompany ProfileDelta Computer Systems, Inc. manufactures motion controllers, color sensors, and other industrial controls providing high-performance automation solutions to a wide range of industries.RMC75E-MA1RMCTools Features Motion Control…and More. p.3Printed in USA 6/11RMC70 Control FeaturesThe RMC70 provides an extensive set of motion commands and programming capability for quick and easy yet flexible motion control for virtually every motion application.SClosed Loop ControlFull PID loop control with velocity, acceleration and jerk feed forwards for precise synchronized motion. Directional gain factors support fluid power control. SPosition ControlSPoint-to-Point moves S S-curvesS Speed at Position S GearingS Cyclic Sinusoidal Motion S Splines S CamsS Move VelocityS Rotary motion with support for incremental andabsolute SVelocity ControlSVelocity control with position feedback S Velocity control with velocity feedback SPressure and Force ControlSLinear or S-curve Ramps S GearingS Cyclic Sinusoidal Profile S Splines S Cams SForce ControlLoad cell or differential force.SPosition-Pressure and Position-Force Control STransition seamlessly between position control and pressure or force control.S Pressure or Force Limit – limit the pressure orforce during a position or velocity move. SActive DampingFor high-performance control of pneumatics and difficult systems.SOpen Loop ControlSeamless transition from open loop to closed loop and vice versa. Ramp the Control Output smoothly between two values, or ramp the Control Output down as the position approaches the final position, for hard-to-control systems.SQuick MoveMove in open loop and stop in closed loop for fast, smooth motion with accurate stops.SUser ProgramsPrograms are easy-to-understand sequences of commands. Run multiple programs simultaneously to handle axis commands and machine control functions.SPreScan TableCyclic task for immediate response to internal conditions or external events, such as discrete inputs, error conditions, etc.SVariablesRecipes and other user parameters can be stored for use by user programs.SMathematical ExpressionsExpressions provide flexible programming capability for advanced calculations and machine control sequences.SPlotsPlot any register in the RMC70, up to 16 registers per plot, sampled down to the control loop resolution. Event LogSpeeds troubleshooting by recording events such as parameter changes, commands, errors, and communications.SClosed Loop stopsRamp speed to zero at specified rate and hold position.SOpen Loop stopsRamp output voltage to zero at specified rate. SMulti-axis (group) stopsA fault on one axis halts multiple axes when configured as a group.SAutoStopsThe response of axes to each fault type is easily configurable.RMC75E CPU ModuleRMC75P CPU ModuleRMC75S CPU Module Motion Control…and More. p.5| Delta Computer Systems, Inc. | Battle Ground, WA USA 98604 | Tel: 360.254.8688 | Fax: 360.254.5435 | |p.6Motion Control…and More.p.7| Delta Computer Systems, Inc. | Battle Ground, WA USA 98604 | Tel: 360.254.8688 | Fax: 360.254.5435 | |p.8MA1 Axis ModuleAA2 Axis ModuleQA1 Axis ModuleMotion Control…and More.p.9| Delta Computer Systems, Inc. | Battle Ground, WA USA 98604 | Tel: 360.254.8688 | Fax: 360.254.5435 | |p.10Motion Control…and More.p.11| Delta Computer Systems, Inc. | Battle Ground, WA USA 98604 | Tel: 360.254.8688 | Fax: 360.254.5435 | |p.12Up to four Expansion modules (Exp70) can be added to an RMC70 motion controller to bring additional capabilities to the controller. Thetransducers.The A2 generates a 10 VDC exciter output, which eliminates a precision power source in some potentiometer applications. This low noise reference also provides the accuracyfollowing characteristics:S Voltage: r10 VS Current: 4-20 mAEach 16-bit input of the AP2 can be Motion Control…and More. p.13| Delta Computer Systems, Inc. | Battle Ground, WA USA 98604 | Tel: 360.254.8688 | Fax: 360.254.5435 | |p.14output common, all inputs must be the same polarity, and all outputs must be the same polarity, but inputs need not be the samepolarity as outputs. That is, outputs can switch high side or low side, and the inputs can be operated with either polarity signals.allows up to 64 slave axes to be electronically geared to one master quadrature signal. Motion Control…and More. p.15Printed in USA 6/11RMC70 Series WiringN ote: For detailed wiring diagrams, see the RMC70 Startup Guide or the RMCTools help.Ethernet (RJ-45)Twisted pair cable CAT5, CAT5e or CAT6, UTP or STP conforming to IEEE 802.3 for 100BASE-T must be used.Power Terminal BlockPin Label Function1 +24Vdc PS +24 VDC power2 PS Return Isolated power common3 Case Chassis groundMonitor Port (USB “B” Connector)Accepts a standard USB cable to communicate with a PC running RMCTools.PROFIBUS-DPStandard PROFIBUS-DP cabling must be used.Power Terminal BlockPin LabelFunction1 +24Vdc PS +24 VDC power2 PS Return Isolated power common3 CaseChassis groundMonitor PortAccepts a null-modem DB-9 female-to-female cable tocommunicate with a PC running RMCTools.RS-232 (DB-9)Pin Function2 Received data3 Transmitted data 5 Serial common 7 Request to Send (RTS) 8 Clear to Send (CTS)RS-485 Terminal BlockPin Label Function1 + T/R Tx/ Rx B (+)2 Trm Jpr Jumper to +T/R for termination3 - T/R Tx/ Rx A (-)4 SCmn Isolated serial common5 Bias Jumper Jumper to SCmn for bias6 CaseChassis groundPower (shared connector with RS-485)Pin Label Function 6 Case Chassis ground 7 +24Vdc PS +24 VDC power 8 PS Return Isolated power commonMonitor PortAccepts a null-modem DB-9 female-to-female cable tocommunicate with a PC running RMCTools.One connector per axis:Pin Label Function 1 + Fault InFault Input (12-24 VDC)2 - Fault In3 + Enable OutEnable Output (12-24 VDC)4 - Enable Out5 Control OutControl Output (±10 V)6 Common MDT SSI7 + Int/Clock + Interrogate + Clock8 - Int/Clock - Interrogate - Clock9 Common Common Common 10 + Ret/Data + Return + Data 11 - Ret/Data - Return - Data 12 Case Chassis groundNote: Pins 6 and 9 are electrically the same.One connector per axis:PinLabelFunction1 + Fault InFault Input (12-24 VDC)2 - Fault In3 + Enable OutEnable Output (12-24 VDC)4 - Enable Out5 Control OutControl Output (±10 V)6 Common7 + Anlg InAnalog input(For 4-20 mA, jumper pins 7 and 8)8 Jmpr for 4- 20mA9 - Anlg In 10 Common Analog common11+ 10Vdc Exciter Exciter output for use withpotentiometers12 Case Chassis ground Note: Pins 6 and 10 are electrically the same.Wiring continuedN ote: For detailed wiring diagrams, see the RMC70 Startup Guide or the RMCTools help.One connector per axis:PinLabelFunction1 A- A- from encoder (5 V signal)2 A+ A+ from encoder (5 V signal)3 B- B- from encoder (5 V signal)4 B+ B+ from encoder (5 V signal) 5 n/c No connection6 RegY/NegLim- Registration Y orNegative Limit (12-24 VDC) 7 RegY/NegLim+8 RegX/PosLim- Registration X orPositive Limit (12-24 VDC) 9 RegX/PosLim+10 n/c No connection 11 n/c No connection 12 Control OutControl Output (±10 V)13 Common 14 Z- Index pulse from encoder(5 V signals) 15 Z+16 Cmn Common17 n/c No connection 18 Home-Home Input (12-24 VDC)19 Home+ 20 - Fault InFault Input (12-24 VDC)21 + Fault In 22 n/c No connection 23 n/c No connection 24 - Enable OutEnable Output25 + Enable OutNote: Pins 13 and 16 are electrically the same.Pin LabelFunction110V Exciter+Exciter output for use with potentiometers2 Anlg Cmn Isolated analog common3 Input 0+ Analog input 0 (For 4-20mA, jumper pins 3and 4) 4 Jumper for 4-20mA5 Input 0-6 Anlg Cmn Isolated analog common7 Input 1+ Analog input 1 (For 4-20mA, jumper pins 7and 8) 8 Jumper for 4-20mA 9 Input 1-10 Case Chassis GroundNote: Pins 2 and 6 are electrically the same.Pin LabelFunction1 Input 0+Analog input 0(For 4-20 mA, jumper pins 1 and 2)2Jumper for4-20mA3 Input 0-4 Anlg Cmn Isolated analog common5 Input 1+Analog input 1(For 4-20 mA, jumper pins 5 and 6)6Jumper for4-20mA7 Input 1- 8 Case Chassis groundPinLabelFunction1 Output Cmn Common to one side of all outputs2 I/O 0 Input or output 03 I/O 1 Input or output 14 I/O 2 Input or output 25 I/O 3 Input or output 36 I/O 4 Input or output 47 I/O 5 Input or output 58 I/O 6 Input or output 69 I/O 7Input or output 710Input CmnCommon to one side of all inputsPin Label Function 1 Reg In+ High-speed registration orhome input 2 Reg In-3 A+Encoder A Input(to enable termination,jumper pins 3 and 4*)4 Jumper forTermination*5 A-6 Cmn Common7 B+Encoder B Input(to enable termination,jumper pins 7 and 8*)8 Jumper forTermination*9 B- 10 Case Chassis ground * Use either both jumpers or no jumpers.Printed in USA 6/11Drawings are not at 1:1 scale.RMC70 Series DimensionsAccessoriesDelta's voltage-to-current converters are designed for converting a voltage drive output to a current drive output in order to control a servo valve. Delta offers several voltage-to-current converters to fit your needs. The maximum output current is adjustable in increments of 10 mA up to the maximum output current range.PartNumber Description Output Current Range*PowerSupplyVC21242-channel voltage-to-current converter ±100 mA per channel 24 VDCVC2100 2-channel voltage-to-current converter ±100 mA per channel ±15 VDCVC2100-HS 2-channel voltage-to-current converter –high speed**±100 mA per channel ±15 VDCVC2124 VC2100 VC2100-HS* Channels can be connected in parallel to provide higher current. For example, two ±100 mA channels connected in parallel will provide ±200 mA.** M ost hydraulic control applications do not require the high-speed converter.Delta 's provides cable assemblies for certain products. The table below lists the available cables:Cable Part No Cable DescriptionRMC-CB-QUAD-01-06 6 ft long, for QA module. 1 DB25 to 3 individual pig-tailed cablesfor drive, encoder, and limits.RMC-CB-QUAD-01-10 10 ft long, for QA module. 1 DB25 to 3 individual pig-tailed cablesfor drive, encoder, and limits.RMC-CB-QUAD-01-15 15 ft long, for QA module. 1 DB25 to 3 individual pig-tailed cablesfor drive, encoder, and limits.RMC-CB-QUAD-01-20 20 ft long, for QA module. 1 DB25 to 3 individual pig-tailed cablesfor drive, encoder, and limits.Custom lengths are available per request. A drawing of RMC-CB-QUAD-01-xx is available on the Downloads page of Delta’s website at /dloads.All RMCs ship with connectors. Connectors are also available for order individually from Delta. The table below lists the available connectors. These parts are also available from connector manufacturers Amphenol Pcd or WECO using thesepart numbers.Connector Part NoConnector Description For ModulesELFT03260E RMC70 3-pin Terminal Block RMC75E, RMC75PELFT08260 RMC70 8-pin Terminal Block RMC75S, AP2ELFT10260 RMC70 10-pin Terminal Block A2, D8ELFT12260 RMC70 12-pin Terminal Block AA, MA p.19| Delta Computer Systems, Inc. | Battle Ground, WA USA 98604 | Tel: 360.254.8688 | Fax: 360.254.5435 | |Printed in USA 6/11。

H820系列3G/4G路由器规格说明书产品概述H820系列路由器是伊林思科技有限公司基于无线网络需求，采用最新硬件系统平台，使用Linux软件系统引用最新技术研发出来的一款全新的，性能更为优异的物联网无线通信路由器产品。

采用工业级设计标准，它主要应用于行业用户的数据传输业务。

该产品采用高性能的32位嵌入式处理器,内嵌完备的TCP/IP协议栈,同时提供RS串口和10/100M以太网接口。

集成IO端子座，提供串口或者GPIO接口。

串口分别提供RS-232、RS-485、TTL电平接口的透明传输模式，支持的VPN 通信功能，采用IPSec/PPTP/L2TP/GRE/OpenVPN等VPN技术，企业级VPN隧道技术和防火墙技术，保证高安全性行业的数据安全，支持自动在线检测，实时动态刷新网络状态，保持链路畅通，产品以性能稳定、体积小、易于安装嵌入、抵抗环境能力强等优点，深受用户欢迎。

支持WEB/Telnet/Console/TR069/NMS管理系统等多种配置方式，其中用户面对的是WEB图形化管理配制界面，管理方便简单。

该产品已广泛应用于物联网产业链中的M2M/IoT行业，如物流快递柜、充电桩、金融、邮政、智能电网、智能交通、智能家居、智能建筑、环保监测、消防监控、安防监控、水利监测、公共安全、广告发布、供应链自动化、工业自动化、工业控制、地震监测、气象监测、数字化医疗、遥感勘测、仪表监测、农业、林业、水务、煤矿、石化等领域。

行业应用公共服务：物流快递柜、充电桩金融：银行储蓄点机房监控，移动性证券交易和信息查询，ATM机通信：电信机房动力环境监控，通信维护人员线路资料查询交通：GPRS/SMS/GPS 机动车辆监控调度系统；银行运钞车，邮政运输车监控调度公安：公安、110、交警车辆监控调度，公安移动性数据（身份证、犯罪档案等）查询，交警移动通信数据（车辆、司机档案等）查询热力：热力系统实时监控和维护电力：电力系统城市中电网实时监控和自动补偿，远程自动抄表；铁塔监控等；公司：移动办公及管理，其他外勤人员移动性数据查询工业：工业遥感，遥测，遥控信息回报气象：气象数据采集与传输水利：水文监测生活：煤气调压站实时数据采集自动控制，自来水；快递柜；污水管道，闸门、泵站与水厂实时监控维护电子商务：支持B2B、B2C的电子商务和电子支付、股票交易等监控: 视频监控, CCTV>>| 主要功能特性项目内容支持多种网络灵活选择全网通支持中国联通、中国电信、中国移动、中国广电等2G/3G/4G网络工业级应用设计采用高性能工业级无线模块；采用高性能工业级32位通讯处理器；支持低功耗模式，包括休眠模式、定时上下线、模式和定时开关机模式；采用金属外壳，保护等级IP30。

LED驱动控制专用电路---HT1628一、概述HT1628是一种带键盘扫描接口的LED（发光二极管显示器）驱动控制专用电路，内部集成有MCU数字接口、数据锁存器、LED高压驱动、键盘扫描等电路。

本产品性能优良，质量可靠。

二、特性说明�采用功率CMOS工艺�多种显示模式（10段×7位～13段×4位）�键扫描（10×2bit）�辉度调节电路（占空比8级可调）�串行接口（CLK，STB，DI/O）�振荡方式：RC振荡�内置上电复位电路�封装形式：SOP28三、内部功能框图：四、管脚定义：管脚功能定义：五、显示寄存器地址和显示模式：该寄存器存储通过串行接口从外部器件传送到HT1628的数据，地址分配如下：六、键扫描和键扫数据寄存器：为10×3bit，如下所示：键扫数据储存地址如下所示，用读指令读取，读从低位开始：七、指令说明：指令用来设置显示模式和LED驱动器的状态。

在STB下降沿后由DIN输入的第一个字节作为一条指令。

如果在指令或数据传输时STB被置为高电平，串行通讯被初始化，并且正在传送的指令或数据无效（之前传送的指令或数据保持有效）。

（1）显示模式设置：该指令用来设置选择段和位的个数（4～7位，10～13段）。

当指令执行时，显示被强制终止，同时键扫描也停止。

要重新显示，显示开/关指令“ON”必需被执行，但当相同模式被设置时，则上述情况并不发生。

上电时，设置模式为4位，14段。

（2）数据设置：该指令用来设置数据写和读（3）地址设定：该指令用来设置显示寄存器的地址。

如果地址设为0EH或更高，数据被忽略，直到有效地址被设定。

上电时，地址设为00H。

（4）显示控制：上电时，设置为脉冲宽度为1/16，显示关。

上电时，键扫停止。

八、串行数据传输格式：数据接收（写数据）数据读取：因为DOUT管脚为N管开漏输出，所以该脚要连接一个外部上拉电阻（1KΩ到10KΩ）**：读取数据时，从串行时钟CLK的第8个上升沿开始设置指令到CLK下降沿读数据之间需要一个等待时间tWAIT(最小1μS)。

MX28F160C3T/B16M-BIT [1M x16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORY- Word write suspend to read- Sector erase suspend to word write- Sector erase suspend to read register report•Automatic sector erase, word write and sector lock/unlock configuration •Status Reply- Detection of program and erase operation comple-tion.- Command User Interface (CUI)- Status Register (SR)•Data Protection Performance- Include boot sectors and parameter and main sectors to be locked/unlocked•100,000 minimum erase/program cycles •Common Flash Interface (CFI)•128-bit Protection Register- 64-bit Unique Device Identifier - 64-bit User-Programmable•Latch-up protected to 100mA from -1V to VCC+1V •Package type:- 48-pin TSOP (12mm x 20mm)- 48-ball CSP (8mm x 6mm)FEATURES•Bit Organization: 1,048,576 x 16•Single power supply operation- VCC=VCCQ=2.7~3.6V for read, erase and program operation- VPP=12V for fast production programming - Operating temperature:-40°C~85°C •Fast access time : 70/90/110ns •Low power consumption- 9mA typical active read current, f=5MHz- 18mA typical program current (VPP=1.65~3.6V)- 21mA typical erase current (VPP=1.65~3.6V)- 7uA typical standby current under power saving mode•Sector architecture- Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x 31 (main sectors)- Top/Bottom Boot•Auto Erase and Auto Program- Automatically program and verify data at specified address- Auto sector erase at specified sector •Automatic Suspend EnhanceGENERAL DESCRIPTIONThe MX28F160C3T/B is a 16-mega bit Flash memory organized as 1M words of 16 bits. The 1M word of data is arranged in eight 4Kword boot and parameter sectors,and thirty-one 32K word main sectors which are indi-vidually erasable. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX28F160C3T/B is packaged in 48-pin TSOP and 48-ball CSP . It is designed to be re-programmed and erased in system or in standard EPROM programmers.fast as 70ns, allowing operation of high-speed micropro-cessors without wait states.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX28F160C3T/B uses a command register to manage this functionality. The command register allows for 100%TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi-mum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXICMX28F160C3T/Bmechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX28F160C3T/B uses a 2.7V~3.6V VCC sup-ply to perform the High Reliability Erase and auto Pro-gram/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.The dedicated VPP pin gives complete data protection when VPP< VPPLK.A Command User Interface (CUI) serves as the inter-face between the system processor and internal opera-tion of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algo-rithms and timings necessary for erase, word write and sector lock/unlock configuration operations.A sector erase operation erases one of the device's 32K-word sectors typically within 1.0s, 4K-word sectors typi-cally within 0.5s independent of other sectors. Each sec-tor can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector.Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program sus-pend mode enables the system to read data or execute code from any other memory array location.MX28F160C3T/B features with individual sectors lock-ing by using a combination of bits thirty-nine sector lock-bits and WP, to lock and unlock sectors.The status register indicates when the WSM's sector erase, word program or lock configuration operation is done.The access time is 70/90/110ns (tELQV) over the oper-ating temperature range (-40°C to +85°C) and VCC sup-ply voltage range of 2.7V~3.6V.MX28F160C3T/B's power saving mode feature substan-tially reduces active current when the device is in static mode (addresses not switching). In this mode, the typi-cal ICCS current is 7uA (CMOS) at 3.0V VCC.As CE and RP are at VCC, ICC CMOS standby mode is enabled. When RP is at GND, the reset mode is enabled which minimize power consumption and provide data write protection.A reset time (tPHQV) is required from RP switching high until outputs are valid. Similarly, the device has a wake time (tPHEL) from RP-high until writes to the CUI are recognized. With RP at GND, the WSM is reset and the status register is cleared.MX28F160C3T/BMX28F160C3T/BMX28F160C3T/BTable 1. Pin DescriptionSymbol Type Description and FunctionA0-A19input Address inputs for memory address. Data pin float to high-impedance when the chip isdeselected or outputs are disable. Addresses are internally latched during a write orerase cycle.DQ0-DQ15input/output Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-gram command. Data is internally latched. Outputs array and configuration data. Thedata pin float to tri-state when the chip is de-selected.CE input Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.CE high de-selects the memory device and reduce power consumption to standbylevel. CE is active low.RP input Reset/Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,which drives the outputs to High Z, resets the WSM and minimizes current level.When RP=VIH, the device is normal operation. When RP transitions from VIL to VIH,the device defaults to the read array mode.WE input Write Enable: to control write to CUI and array sector. WE=VIL becomes active. Thedata and addresses are latched on the rising edge of the second WE pulse.VPP input/supply Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)Lower VPP<VPPLK, to protect any contents against Program and Erase Command.Set VPP=VCC for in-system Read, Program and Erase Operation.Raise VPP to 12V±5% for faster program and erase in a production environment.OE input Output enable: gates the device's outputs during a real cycle.WP input Write Protect: When WP is VIL, the sectors marked Lock Down can't be unlockedthrough software. When WP is VIH, the lock down mechanism is disable and sectorspreviously locked down are now locked and can be unlocked and locked through soft-ware. After WP goes low, any sectors previously marked lock down revert to that state. VCC supply Device power supply: (2.7V~3.6V).VCCQ input I/O Power Supply: supplies for input/output buffers. (VCCQ must be tied to VCC) GND supply Ground voltage: all the GND pin shall not be connected.MX28F160C3T/BSECTOR STRUCTURE (TOP)Sector Sector Size Address Range (h)Boot Sector 04K Word FF000 ~ FFFFFBoot Sector 14K Word FE000 ~ FEFFFParameter Sector 04K Word FD000 ~ FDFFFParameter Sector 14K Word FC000 ~ FCFFFParameter Sector 24K Word FB000 ~ FBFFFParameter Sector 34K Word FA000 ~ FAFFFParameter Sector 44K Word F9000 ~ F9FFFParameter Sector 54K Word F8000 ~ F8FFFMain Sector 032K Word F0000 ~ F7FFFMain Sector 132K Word E8000 ~ EFFFFMain Sector 232K Word E0000 ~ E7FFFMain Sector 332K Word D8000 ~ DFFFFMain Sector 432K Word D0000 ~ D7FFFMain Sector 532K Word C8000 ~ CFFFFMain Sector 632K Word C0000 ~ C7FFFMain Sector 732K Word B8000 ~ BFFFFMain Sector 832K Word B0000 ~ B7FFFMain Sector 932K Word A8000 ~ AFFFFMain Sector 1032K Word A0000 ~ A7FFFMain Sector 1132K Word98000 ~ 9FFFFMain Sector 1232K Word90000 ~ 97FFFMain Sector 1332K Word88000 ~ 8FFFFMain Sector 1432K Word80000 ~ 87FFFMain Sector 1532K Word78000 ~ 7FFFFMain Sector 1632K Word70000 ~ 77FFFMain Sector 1732K Word68000 ~ 6FFFFMain Sector 1832K Word60000 ~ 67FFFMain Sector 1932K Word58000 ~ 5FFFFMain Sector 2032K Word50000 ~ 57FFFMain Sector 2132K Word48000 ~ 4FFFFMain Sector 2232K Word40000 ~ 47FFFMain Sector 2332K Word38000 ~ 3FFFFMain Sector 2432K Word30000 ~ 37FFFMain Sector 2532K Word28000 ~ 2FFFFMain Sector 2632K Word20000 ~ 27FFFMain Sector 2732K Word18000 ~ 1FFFFMain Sector 2832K Word10000 ~ 17FFFMain Sector 2932K Word08000 ~ 0FFFFMX28F160C3T/BSECTOR STRUCTURE (BOTTOM)Sector Sector Size Address Range (h)Boot Sector 04K Word00000 ~ 00FFFBoot Sector 14K Word01000 ~ 01FFFParameter Sector 04K Word02000 ~ 02FFFParameter Sector 14K Word03000 ~ 03FFFParameter Sector 24K Word04000 ~ 04FFFParameter Sector 34K Word05000 ~ 05FFFParameter Sector 44K Word06000 ~ 06FFFParameter Sector 54K Word07000 ~ 07FFFMain Sector 032K Word08000 ~ 0FFFFMain Sector 132K Word10000 ~ 17FFFMain Sector 232K Word18000 ~ 1FFFFMain Sector 332K Word20000 ~ 27FFFMain Sector 432K Word28000 ~ 2FFFFMain Sector 532K Word30000 ~ 37FFFMain Sector 632K Word38000 ~ 3FFFFMain Sector 732K Word40000 ~ 47FFFMain Sector 832K Word48000 ~ 4FFFFMain Sector 932K Word50000 ~ 57FFFMain Sector 1032K Word58000 ~ 5FFFFMain Sector 1132K Word60000 ~ 67FFFMain Sector 1232K Word68000 ~ 6FFFFMain Sector 1332K Word70000 ~ 77FFFMain Sector 1432K Word78000 ~ 7FFFFMain Sector 1532K Word80000 ~ 87FFFMain Sector 1632K Word88000 ~ 8FFFFMain Sector 1732K Word90000 ~ 97FFFMain Sector 1832K Word98000 ~ 9FFFFMain Sector 1932K Word A0000 ~ A7FFFMain Sector 2032K Word A8000 ~ AFFFFMain Sector 2132K Word B0000 ~ B7FFFMain Sector 2232K Word B8000 ~ BFFFFMain Sector 2332K Word C0000 ~ C7FFFMain Sector 2432K Word C8000 ~ CFFFFMain Sector 2532K Word D0000 ~ D7FFFMain Sector 2632K Word D8000 ~ DFFFFMain Sector 2732K Word E0000 ~ E7FFFMain Sector 2832K Word E8000 ~ EFFFFMain Sector 2932K Word F0000 ~ F7FFFMX28F160C3T/B2 PRINCIPLES OF OPERATIONThe product includes an on-chip WSM to manage sec-tor erase, word write and lock-bit configuration functions.After initial device power-up or return from reset mode (see section on Bus Operations), the device defaults to read array mode. Manipulation of external memory con-trol pins allow array read, standby and output disable operations.Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. All functions associated with altering memory contents -sector erase, word write, sector lock/unlock, status and identifier codes - are accessed via the CUI and verified through the status register.Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the sector erase, word write and sector lock/unlock. The internal algorithms are regulated by the WSM, including pulse repetition, internal verifica-tion and margining of data. Addresses and data are in-ternally latched during write cycles. Address is latched at falling edge of CE and data latched at rising edge of WE. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data.Interface software that initiates and polls progress of sector erase, word write and sector lock/unlock can be stored in any sector. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Sector erase suspend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location.With the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. When RP=VIH and VCC<VLKO (lockout voltage), any data write alteration can be failure. During read opera-tion, if write VPP voltage is below VPPLK, then hard-ware level data protection is achieved. With CUI's two-step command sequence sector erase, word write or sector lock/unlock, software level data protection is 3 BUS OPERATIONThe local CPU reads and writes flash memory in-sys-tem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.3.1 ReadInformation can be read from any sector, configuration codes or status register independent of the VPP volt-age. RP can be at VIH.The first task is to write the appropriate read mode com-mand (Read Array, Read Configuration, Read Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset, the device automati-cally resets to read array mode. In order to read data, control pins set for CE, OE, WE, RP and WP must be driven to active. CE and OE must be active to obtain data at the outputs. CE is the device selection control. OE is the data output (DQ0-DQ15) control and active drives the selected memory data onto the I/O bus, WE must be VIH, RP must be VIH, WP must be at VIL or VIH.3.2 Output DisableWith OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ15) are placed in a high-impedance state.3.3 StandbyCE at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0~DQ15 outputs are placed in a high-impedance state independent of OE. If deselected dur-ing sector erase, word write or sector lock/unlock, the device continues functioning, and consuming active power until the operation completes.3.4 ResetAs RP=VIL, it initiates the reset mode. The device en-ters reset/deep power down mode. However, the data stored in the memory has to be sustained at least 100nsMX28F160C3T/Band output high impedance state.In read modes, RP-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP must be held low for a minimum of 100ns. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. Af-ter this wake-up interval tPHEL or tPHWL, normal op-eration is restored. The CUI is reset to read array mode and status register is set to 80H. Sector lock bit is set at lock status.During sector erase, word write or sector lock/unlock modes, RP-low will abort the operation. Memory con-tents being altered are no longer valid; the data may be partially erased or written.In addition, CUI will go into either array read mode or erase/write interrupted mode. When power is up and the device reset subsequently, it is necessary to read sta-tus register in order to assure the status of the device. Recognizing status register (SR.7~0) will assure if the device goes back to normal reset and enters array read mode.3.5 Read Configuration CodesThe read configuration codes operation outputs the manu-facturer code, device code, sector lock configuration codes, and the protection register. Using the manufac-turer and device codes, the system CPU can automati-cally match the device with its proper algorithms. The sector lock codes identify locked and unlocked sectors.3.6 WriteWriting commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCC=2.7V-3.6V and VPP within VPP1 or VPP2 range, the CUI addition-ally controls sector erase, word write and sector lock/ unlock.The Sector Erase command requires appropriate com-mand data and an address within the sector to be erased. The Full Chip Erase command requires appropriate com-mand data and an address within the device. The Word Write command requires the command and address of mands require the command and address within the de-vice or sector within the device (Sector Lock) to be locked. The Clear Sector Lock-Bits command requires the command and address within the device.The CUI does not occupy an addressable memory loca-tion. It is written when WE and CE are active (whichever goes high first). The address and data needed to ex-ecute a command are latched on the rising edge of WE or CE. Standard microprocessor write timings are used.MX28F160C3T/B4 COMMAND DEFINITIONSThe flash memory has four read modes: read array, readconfiguration, read status, read query, and two writemodes: program, erase. These read modes are acces-sible independent of the VPP voltage. But write modesare disable during VPP<VPPLK. Placing VPP on VPP1/2 enables successful sector erase, word write and sec-tor lock/unlock.Device operations are selected by writing specific com-mands into the CUI. T able 3 defines these commands.Table 2. Bus OperationMode Notes RP CE OE WE DQ0~DQ15Read1,2VIH VIL VIL VIH DOUTOutput Disable2VIH VIL VIH VIH High ZStandby2VIH VIH X X High ZReset2VIL X X X High ZWrite2,3,4,5VIH VIL VIH VIL DINNotes:1.Refer to DC Characteristics for VPPLK, VPP1, VPP2 voltage.2.X can be VIL or VIH for pin and addresses.3.RP at GND±0.2 to ensure the lowest power consumption.4.Refer to Table 3 for valid DIN during a write operation.5.To program or erase the lockable sectors holds WP at VIH.MX28F160C3T/BTable 3. Command Definition (1)Command Bus Notes First Bus Cycle Second Bus CycleCycles Operation Address Data Operation Address DataRequired(1)(2)(3)(1)(2)(3) Read Array1Write X FFHRead Configuration> 22,4Write X90H Read IA ID Read Query22,7Write X98H Read QA QD Read Status Register23Write X70H Read X SRD Clear Status Register13Write X50HSector Erase/Confirm2Write X20H Write SA D0H Word Write22,5Write X40H/10H Write WA WD Program/Erase Suspend1Write X B0HProgram/Erase Resume1Write X D0HSector Lock2Write X60H Write SA01H Sector Unlock26Write X60H Write SA D0H Lock-Down Sector2Write X60H Write SA2FH Protection Program2Write X C0H Write P A PDNotes:1.Bus operation are defined in Table 2 and referred to AC Timing Waveform.2.X=Any address within device.IA=ID-Code Address (refer to Table 4).ID=Data read from identifier code.SA=Sector Address within the sector being erased.WA=Address of memory location to be written.WD=Data to be written at location WA.PA=Program Address, PD=Program DataQA=Query Address, QD=Query Data.3.Data is latched from the rising edge of WE or CE (whichever goes high first)SRD=Data read from status register, see T able 6 for description of the status register bits.4.Following the Read Configuration codes command, read operation access manufacturer, device codes, sectorlock/unlock codes, see chapter 4.2.5.Either 40H or 10H command is recognized by the WSM as word write setup.6.The sector unlock operation simultaneously clear all sector lock.7.Read Query Command is read for CFI query information.MX28F160C3T/B4.1 Read Array CommandUpon initial device power-up and after exit from reset mode, the device defaults to read array mode. This op-eration is also initiated by writing the Read Array com-mand. The device remains enabled for reads until an-other command is written. Once the internal WSM has started a sector erase, word write or sector lock con-figuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via a Sector Erase Suspend or Word Write Suspend command. If RP=VIL device is in read Read Array command mode, this read operation no longer requires VPP . The Read Array command func-tions independently of the VPP voltage and RP can be VIH.4.2 Read Configuration Codes CommandThe configuration code operation is initiated by writing the Read Configuration Codes command (90H). To re-turn to read array mode, write the Read Array Command (FFH). Following the command write, read cycles from addresses shown in T able 4 retrieve the manufacturer,device, sector lock configuration codes and the protec-tion register(see Table 4 for configuration code values).T o terminate the operation, write another valid command.Like the Read Array command, the Read Configuration Codes command functions independently of the VPP voltage and RP can be VIH. Following the Read Configu-ration Codes command, the information is shown:CodeAddress Data (A19-A0)(DQ15-DQ0)Manufacturer Code00000H00C2H Device Code(Top/Bottom)00001H 88C2/88C3H Sector Lock Configuration XX002H LocK - Sector is unlocked DQ0=0- Sector is locked DQ0=1- Sector is locked-down DQ1=1Protection Register Lock 80PR-LK Protection Register81-88PRTable 4: ID Code4.3 Read Status Register CommandCUI writes read status command (70H). The status reg-ister may be read to determine when a sector erase,word write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 6) It may be read at any time by writing the Read Status Register command. After writing this command,all subsequent read operations output data from the sta-tus register until another valid command is written. The status register contents are latched on the falling edge of CE or OE, whichever occurs last. CE or OE must toggle to VIH before further reads to update the status register latch. The Read Status Register command func-tions independently of the VPP voltage. RP can be VIH.4.4 Clear Status Register CommandStatus register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command (50H). These bits indicate various failure conditions (see Table 6). By allowing sys-tem software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing sev-eral words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence.T o clear the status register, the Clear Status Register command (50H) is written on CUI. It functions indepen-dently of the applied VPP Voltage. RP can be VIH. This command is not functional during sector erase or word write suspend modes.MX28F160C3T/B4.5 Sector Erase CommandErase is executed one sector at a time and initiated by a two-cycle command. A sector erase setup is first writ-ten (20H), followed by a sector erase confirm (D0H). This command sequence requires appropriate sequencing and an address within the sector to be erased. Sector pre-conditioning, erase, and verify are handled internally by the WSM. After the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect sec-tor erase completion by analyzing the output data of the status register bit SR.7.When the sector erase is complete, status register bit SR.5 should be checked. If a sector erase error is de-tected, the status register should be cleared before sys-tem software attempts corrective actions. The CUI re-mains in read status register mode until a new com-mand is issued.This two-step command sequence of set-up followed by execution ensures that sector contents are not acciden-tally erased. An invalid sector Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable sector erasure can only occur when 2.7V~3.6V and VPP=VPP1/2. In the absence of this high voltage, sector contents are protected against erasure. If sector erase is attempted while VPP<VPPLK SR.3 and SR.5 will be set to "1". T o successfully erase the boot sector, the corresponding sector lock-bit must be clear first. In parameter and sectors case, it must be cleared the corresponding sector lock-bit. If sector erase is attempted when the excepting above sector being locked conditions, SR.1 and SR.5 will be set to "1". Sec-tor erase is not functional.4.6 Word Write CommandWord write is executed by a two-cycle command se-quence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the word write and write verify algorithms internally. Af-ter the word write sequence is written, the device auto-matically outputs status register data when read (see Figure 6). The CPU can detect the completion of the word write event by analyzing the status register bit SR.7. When word write is complete, status register bit SR.4should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command.Reliable word writes can only occur when VCC=2.7V~3.6V and VPP=VPP1/2. If VPP is not within acceptable limits, the WSM doesn't execut the program command. If word write is attempted while VPP<VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write requires for boot sector that WP is VIH the corresponding sector lock-bit be cleared. In parameter and main sectors case, it must be cleared the corresponding sector lock-bit. If word write is at-tempted when the excepting above sector being clocked conditions, SR.1 and SR.4 will be set to "1". Word write is not functional.4.7 Sector Erase Suspend CommandThe Sector Erase Suspend command (50H) allows sec-tor-erase interruption to read or word write data in an-other sector of memory. Once the sector erase process starts, writing the Sector Erase Suspend command re-quests that the WSM suspend the sector erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Sector Erase Suspend command is written. Polling status reg-ister bits SR.7 and SR.6 can determine when the sector erase operation has been suspended (both will be set to "1"). Specification tWHRH2/tEHRH2 defines the sector erase suspend latency.When Sector Erase Suspend command is written to the CUI, if sector erase was finished, the device would be placed read array mode. Therefore, after Sector Erase Suspend command is written to the CUI, Read Status Register command (70H) has to be written to CUI, then status register bit SR.6 should be checked if/when the device is in suspend mode.At this point, a Read Array command can be written to read data from sectors other than that which is sus-pended. A Word Write commands sequence can also be issued during erase suspend to program data in other sectors. Using the Word Write Suspend command (see Section 4.9), a word write operation can also be sus-pended. During a word write operation with sector erase suspended, status register bit SR.7 will return to "0".MX28F160C3T/BHowever, SR.6 will remain "1" to indicate sector erase suspend status.The only other valid commands while sector erase is suspended are Read Status Register, Read Configura-tion, Read Query, Program Setup, Program Resume, Sector Lock, Sector Unlock, Sector Lock-Down and sec-tor erase Resume. After a Sector Erase Resume com-mand is written to the flash memory, the WSM will con-tinue the sector erase process. Status register bits SR.6 and SR.7 will automatically be cleared. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9). VPP must remain at VPP1/2 while sector erase is sus-pended. RP must also remain at VIH (the same RP level used for sector erase). Sector cannot resume until word write operations initiated during sector erase suspend has completed.If the time between writing the Sector Erase Resume command and writing the Sector Erase Suspend com-mand is shorter than 15ms and both commands are writ-ten repeatedly, a longer time is required than standard sector erase until the completion of the operation.4.8 Word Write Suspend CommandThe Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM sus-pend the Word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). Specification tWHRH1/tEHRH1 defines the word write suspend latency. When Word Write Suspend command write to the CUI, if word write was finished, the device places read array mode. Therefore, after Word Write Suspend command write to the CUI, Read Status Register command (70H) has to be written to CUI, then status register bit SR.2 should be checked for if/when the device is in suspend mode.At this point, a Read Array command can be written to read data from locations other than that which is sus-pended. The only other valid commands while word write is suspended are Read Status Register Read Configura-tion, Read Query and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the Word write process. Status register bits SR.2 and SR.7 will automatically be cleared. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Figure 7). VPP must remain at VPP1/2 while in word write suspend mode. RP must also remain at VIH (the same RP level used for word write).If the time between writing the Word Write Resume com-mand and writing the Word Write Suspend command is short and both commands are written repeatedly, a longer time is required than standard word write until the comple-tion of the operation.。

FEATURES•524,288 x 8 only•Single power supply operation- 5.0V only operation for read, erase and program op-eration•Fast access time: 55/70/90/120ns •Low power consumption- 30mA maximum active current(5MHz)- 1uA typical standby current •Command register architecture - Byte Programming (7us typical)- Sector Erase8 equal sectors of 64K-Byte each•Auto Erase (chip & sector) and Auto Program- Automatically erase any combination of sectors with Erase Suspend capability.- Automatically program and verify data at specified address•Erase suspend/Erase Resume- Suspends an erase operation to read data from, orduring erase and programming, while maintaining maxi-mum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.The MX29F040 uses a 5.0V ±10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi tch-up protection is proved for stresses up to 100milliamps on address and data pin from -1V to VCC + 1V.GENERAL DESCRIPTIONThe MX29F040 is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-vola-tile random access memory. The MX29F040 is pack-aged in 32-pin PLCC, TSOP , PDIP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers.The standard MX29F040 offers access time as fast as 55ns, allowing operation of high-speed microprocessorswithout wait states. To eliminate bus contention, the MX29F040 has separate chip enable (CE) and output enable (OE) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F040 uses a command register to manage this functionality. The command register allows for 100%TTL level control inputs and fixed power supply levelsprogram data to, another sector that is not being erased, then resumes the erase.•Status Reply- Data polling & Toggle bit for detection of program and erase cycle completion.•Sector protect/unprotect for 5V only system or 5V/12V system.•Sector protection- Hardware method to disable any combination of sectors from program or erase operations •100,000 minimum erase/program cycles•Latch-up protected to 100mA from -1V to VCC+1V •Low VCC write inhibit is equal to or less than 3.2V •Package type:- 32-pin PLCC, TSOP or PDIP•Compatibility with JEDEC standard- Pinout and software compatible with single-power supply Flash•20 years data retentionMX29F0404M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORYMX29F040MX29F040MX29F040AUTOMATIC PROGRAMMINGThe MX29F040 is byte programmable using the Auto-matic Programming algorithm. The Automatic Program-ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro-grammed. The typical chip programming time at room temperature of the MX29F040 is less than 4 seconds. AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm au-tomatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASEThe MX29F040 is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 un-lock write cycle and A0H) and a program command (pro-gram data and address). The device automatically times the programming pulse width, provides the program veri-fication, and counts the number of sequences. A status bit similar to DAT A polling and a status bit toggling be-tween consecutive read cycles, provide feedback to the user as to the status of the programming operation.AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand-ard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu-tive read cycles provides feedback to the user as to the status of the programming operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge of WE or CE, whichever happens later, and data are latched on the rising edge of WE or CE, whichever happens first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, relia-bility, and cost effectiveness. The MX29F040 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injec-tion.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set.MX29F040TABLE 1. SOFTWARE COMMAND DEFINITIONSFirst Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Command Bus Cycle Cycle Cycle Cycle Cycle CycleCycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1XXXH F0HRead1RA RDRead Silicon ID4555H AAH2AAH55H555H90H ADI DDISector Protect Verify4555H AAH2AAH55H555H90H(SA)X00H0201HProgram4555H AAH2AAH55H555H A0H PA PDChip Erase6555H AAH2AAH55H555H80H555H AAH2AAH55H555H10H Sector Erase6555H AAH2AAH55H555H80H555H AAH2AAH55H SA30H Sector Erase Suspend1XXXH B0HSector Erase Resume1XXXH30HUnlock for sector6555H AAH2AAH55H555H80H555H AAH2AAH55H555H20H protect/unprotectNote:1.ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code A2-A18=Donot care.(Refer to table 3)DDI = Data of Device identifier : C2H for manufacture code, A4H for device code.X = X can be VIL or VIHRA=Address of memory location to be read.RD=Data to be read at location RA.2.P A = Address of memory location to be programmed.PD = Data to be programmed at location P A.SA = Address to the sector to be erased.3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .Address bit A11~A18=X=Don't care for all address commands except for Program Address (P A) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state.4.For Sector Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read outdata is 00H, it means the sector is still not being protected.COMMAND DEFINITIONSDevice operations are selected by writing specific ad-dress and data sequences into the command register.Writing incorrect address and data values or writing themin the improper sequence will reset the device to theread mode. Table 1 defines the valid register commandsequences. Note that the Erase Suspend (B0H) andErase Resume (30H) commands are valid only while theSector Erase operation is in progress. Either of the tworeset command sequences will reset the device (whenapplicable).MX29F040Mode PinsCE OE WE A0A1A6A9Q0 ~ Q7 Read Silicon ID L L H L L X VID(2)C2H Manufacturer Code(1)Read Silicon ID L L H H L X VID(2)A4H Device Code(1)Read L L H A0A1A6A9DOUT Standby H X X X X X X HIGH Z Output Disable L H H X X X X HIGH ZWrite L H L A0A1A6A9DIN(3)Sector Protect with 12V L VID (2)L X X L VID(2)Xsystem(6)Chip Unprotect with 12V L VID (2)L X X H VID(2)Xsystem(6)Verify Sector Protect L L H X H X VID(2)Code(5)with 12V systemSector Protect without 12V L H L X X L H Xsystem (6)Chip Unprotect without 12V L H L X X H H Xsystem (6)Verify Sector Protect/Unprotect L L H X H X H Code(5) without 12V system (7)Reset X X X X X X X HIGH Z TABLE 2. MX29F040 BUS OPERATIONNOTES:1.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.2.VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.3.Refer to Table 1 for valid Data-In during a write operation.4.X can be VIL or VIH.5. Code=00H means unprotected.Code=01H means protected.A18~A16=Sector address for sector protect.6. Refer to sector protect/unprotect algorithm and waveform.Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system"command.MX29F040READ/RESET COMMANDThe read or reset operation is initiated by writing the read/reset command sequence into the command reg-ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com-mand must then be written to place the device in the desired state.SILICON-ID-READ COMMANDFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice.The MX29F040 contains a Silicon-ID-Read operation to supplement traditional PROM programming methodol-ogy. The operation is initiated by writing the read silicon ID command sequence into the command register. Fol-lowing the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H.A read cycle with A1=VIL, A0=VIH returns the device code of A4H for MX29F040.SET-UP AUTOMATIC CHIP/SECTOR ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy-cles are then followed by the chip erase command 10H.The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Au-tomatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the erase operation exceed internal timing limit.The automatic erase begins on the rising edge of the last WE or CE, whichever happens first pulse in the com-mand sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecu-tive read cycles, at which time the device returns to the Read mode.Pins A0A1Q7Q6Q5Q4Q3Q2Q1Q0Code (Hex) Manufacture code VIL VIL11000010C2HDevice code for MX29F040VIH VIL10100100A4HSector Protection Verification X VIH0000000101H (Protected)X VIH0000000000H(Unprotected) TABLE 3. EXPANDED SILICON ID CODEMX29F040 SECTOR ERASE COMMANDSThe Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Au-tomatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations.When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, which-ever happens later, while the command (data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal reg-ister on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever hap-pens later must begin within 30us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sec-tor Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode.Status Q7Q6Q5Q3Q2Note1Note2Byte Program in Auto Program Algorithm Q7Toggle0N/A No ToggleAuto Erase Algorithm0Toggle01ToggleErase Suspend Read1No0N/A Toggle In Progress(Erase Suspended Sector)ToggleErase Suspended Mode Erase Suspend Read Data Data Data Data Data(Non-Erase Suspended Sector)Erase Suspend Program Q7Toggle0N/A N/A Byte Program in Auto Program Algorithm Q7Toggle1N/A No Toggle Exceeded Auto Erase Algorithm0Toggle11Toggle Time Limits Erase Suspend Program Q7Toggle1N/A N/A TABLE 4. Write Operation StatusNote:1.Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for furtherdetails.2.Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.See "Q5:Exceeded Timing Limits " for more information.MX29F040ERASE SUSPENDThis command only has meaning while the state ma-chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com-mand is written during a sector erase operation, the de-vice requires a maximum of 100us to suspend the erase operations. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been ex-ecuted, the command register will initiate erase suspend mode. The state machine will return to read mode auto-matically after suspend is ready. At this time, state ma-chine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands.The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro-gram operation is complete, the system can once again read array data within non-suspended sectors. ERASE RESUMEThis command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.SET-UP AUTOMATIC PROGRAM COMMANDSTo initiate Automatic Program mode, A three-cycle com-mand sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Pro-gram command A0H.Once the Automatic Program command is initiated, the next WE or CE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first pulse. The rising edge of WE or CE, whichever happens first also begins the programming operation. The sys-tem is not required to provide further controls or timings. The device will automatically provide an adequate inter-nally generated program pulse and verify margin.If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required).DATA POLLING-Q7The MX29F040 also features Data Polling as a method to indicate to the host system that the Automatic Pro-gram or Erase algorithms are either in progress or com-pleted.While the Automatic Programming algorithm is in opera-tion, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an at-tempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE or CE, whichever happens first pulse of the four write pulse sequences for auto-matic program.While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE or CE, whichever happens first pulse of six write pulse sequences for automatic chip/ sector erase.The Data Polling feature is active during Automatic Pro-gram/Erase algorithm or sector erase time-out. (see sec-tion Q3 Sector Erase Timer)MX29F040that sector is erase-suspended. Toggle Bit I is valid af-ter the rising edge of the final WE or CE, whichever hap-pens first pulse in the command sequence.Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com-parison, indicates whether the device is actively eras-ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to T able 4 to compare outputs for Q2 and Q6.Reading Toggle Bits Q6/ Q2Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. T ypically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle.However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys-tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase op-eration. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high.The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta-tus as described in the previous paragraph. Alterna-tively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.Q6:Toggle BIT IT oggle Bit I on Q6 indicates whether an Automatic Pro-gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode.T oggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out.During an Automatic Program or Erase algorithm opera-tion, successive read cycles to any address cause Q6to toggle. The system may use either OE or CE to con-trol the read cycles. When the operation is complete, Q6stops toggling.After an erase command sequence is written, if all sec-tors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus-pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling.When the device enters the Erase Suspend mode, Q6stops toggling. However, the system must also use Q2to determine which sectors are erasing or erase-sus-pended. Alternatively, the system can use Q7.If a program address falls within a protected sector, Q6toggles for approximately 2us after the program com-mand sequence is written, then returns to reading array data.Q6 also toggles during the erase-suspend-program mode,and stops toggling once the Automatic Program algo-rithm is complete.Table 4 shows the outputs for Toggle Bit I on Q6.Q2:Toggle Bit IIThe "T oggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is,the Automatic Erase algorithm is in process), or whetherMX29F040Q5Exceeded Timing LimitsQ5 will indicate if the program or erase time has ex-ceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition.If this time-out condition occurs during sector erase op-eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func-tional and may be used for the program or erase opera-tion. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device.If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com-bination of sectors are bad.If this time-out condition occurs during the byte program-ming operation, it specifies that the entire sector con-taining that byte is bad and this sector may not be re-used, (other sectors are still functional and can be re-used).The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Au-tomatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops tog-gling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.DATA PROTECTIONThe MX29F040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi-tion. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incor-porates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down tran-sition or system noise.Q3Sector Erase TimerAfter the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com-mand sequence.If Data Polling or the T oggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or T oggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the com-mand has been accepted, the system software should check the status of Q3 prior to and following each sub-sequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CE or WE will not initiate a write cycle.LOGICAL INHIBITWriting is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. POWER SUPPL Y DECOUPLINGIn order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be-tween its VCC and GND.。

目录1设备主要技术指标 (1)1.1中兴ONU:9806H (1)1.1.1接口功能 (1)1.1.2技术指标和参数 (1)1.1.3物理性能 (2)1.2中兴ONU:F820 (3)1.2.1接口 (3)1.2.2技术指标和参数 (3)1.2.3物理规格 (6)1.3华为ONU: MA5616 (6)1.3.1设备参数 (6)1.3.2性能与容量 (7)1.3.3业务特性与规格 (8)1.4华为ONU: MA5610 (10)1.4.1设备参数 (10)1.4.2性能与容量 (11)1.4.3业务特性与规格 (11)1.5新邮通ONU: T233 (14)1.5.1产品简介： (14)1.5.2产品特点： (14)1.5.3产品特性： (15)1设备主要技术指标1.1 中兴ONU:9806HZXDSL9806H是一款提供xDSL用户线路的调制解调、多种宽带业务综合接入等功能的小容量的一体化设备，支持EPON上行。

可以满配4块用户板，最多支持96路ADSL2/2+ Over POTS 用户或64路VDSL2用户接入。

适合ONU节点、园区、企业等小容量接入的应用。

1.1.1接口功能线路侧：1个标准PON口（SC/PC）用户侧：96个ADSL/ADSL2+接口，或64个VDSL2用户接口1.1.2技术指标和参数数据传输速率线路端（EPON）：1.25Gbps（上下行对称）线路端（GPON）：上行1.244Gbps，下行2.488Gbps用户端接口：10/100Mbps 自适应传输距离链路距离0～20Km（MAX.）传输波长接收中心波长：1490nm发送中心波长：1310nm业务功能支持EPON、GPON上行接口支持《EPON设备互通性要求》，满足所有扩展OAM功能支持上电自动注册支持上行业务的加密和解密，支持churning 和AES128两种加密方式。

支持Dying Gasp支持事件自动上告功能DSLAM功能支持协议：802.1Q VLAN，SVLAN，LINK AGGREGATION, VBAS, DHCP OP82，PPPOE+，SNTP；组播控制：IGMP SNOOPING, IGMP PROXY, IGMP ROUTER, 组播VLAN，CAC, PRW, CDR, SMS管理，组播频道套餐，组播快速离开，组播预加入，端口组播带宽检测，组播带宽限制，组播业务暂停和恢复等；二层业务：标准L2交换，L2隔离/互通，MAC地址白/黑名单，IP绑定，MAC地址数目限制，MAC地址防欺骗，广播及洪泛包抑制，MAC地址统计/反查，静态MAC，用户端口环回检测，以太网端口输出速率限制等；QoS功能：用户端口支持4队列，支持SP/WRR队列调度，支持基于端口/pvc端口的优先级设置和remarking，支持流分类，支持pvc限速，支持端口优先级信任等；系统安全保护：网管通道ACL，网管通道风暴控制，登陆用户/密码权限管理，DHCP SNOOPING, DHCP SOURCE GUARD, DHCP/IGMP rate limit，SHH管理，管理用户的远程认证等；系统调试及诊断：内存使用检测/告警，CPU占有率检测/告警，LOG日志，系统HISTORY日志，系统死机文件，系统自检，端口环回测试，modem管理，SELT/DELT等；性能统计：ADSL2/2+性能统计，VDSL2性能统计，以太网端口性能统计等；网管支持远程管理支持本地管理支持SNMP1.1.3物理性能功耗：<150W（满配置）尺寸：19英寸2U高，88.1mm×482.6mm×240mm（高×宽×深）工作温度：-5℃～45℃工作湿度：5%～95%重量：8.5KG供电：220V AC/-48V DC安装方式：机架1.2 中兴ONU:F820ZXA10 F820 主要用于FTTB/FTTO 应用，提供大客户、专线用户以及多用户的接入，提供以太网和TDM（E1）业务以及VOIP 业务接入，支持EPON/GPON 上联，提供PON 口上联保护。

3 Volt Intel ® StrataFlash ™ Memory28F128J3A, 28F640J3A, 28F320J3A (x8/x16)Preliminary DatasheetProduct FeaturesCapitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel ®StrataFlash ™ memory products provide 2X the bits in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring reliable, two-bit-per-cell storage technology to the flash market segment.Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices.Using the same NOR-based ETOX ™ technology as Intel ’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of over one billion units of manufacturing experience since 1987. As a result, Intel StrataFlash components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging.By applying FlashFile ™ memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash memory (28F640J5 and 28F320J5) devices.Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel ® 0.25 micron ETOX ™ VI process technology, Intel StrataFlash memory provides the highest levels of quality and reliability.sHigh-Density Symmetrically-Blocked Architecture—128 128-Kbyte Erase Blocks (128 M)—64 128-Kbyte Erase Blocks (64 M)—32 128-Kbyte Erase Blocks (32 M)sHigh Performance Interface Asynchronous Page Mode Reads—110/25 ns Read Access Time (32 M)—120/25 ns Read Access Time (64 M)—150/25 ns Read Access Time (128 M)s 2.7 V –3.6 V V CC Operation s128-bit Protection Register—64-bit Unique Device Identifier—64-bit User Programmable OTP Cells sEnhanced Data Protection Features Absolute Protection with V PEN = GND —Flexible Block Locking—Block Erase/Program Lockout during Power TransitionssPackaging—56-Lead TSOP Package—64-Ball Intel ® Easy BGA PackagesCross-Compatible Command Support Intel Basic Command Set—Common Flash Interface —Scalable Command Set s32-Byte Write Buffer—6 µs per Byte Effective Programming Times12.8M Total Min. Erase Cycles (128 Mbit)6.4M Total Min. Erase Cycles (64 Mbit)3.2M Total Min. Erase Cycles (32 Mbit)—100K Minimum Erase Cycles per Block sAutomation Suspend Options —Block Erase Suspend to Read —Block Erase Suspend to Program —Program Suspend to Reads0.25 µ Intel ® StrataFlash ™ Memory TechnologyOrder Number: 290667-008April 2001Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.28F128J3A, 28F640J3A, 28F320J3A Contents1.0Product Overview (1)2.0Principles of Operation (6)2.1Data Protection (6)3.0Bus Operations (7)3.1Read (8)3.2Output Disable (8)3.3Standby (8)3.4Reset/Power-Down (8)3.5Read Query (9)3.6Read Identifier Codes (9)3.7Write (9)4.0Command Definitions (9)4.1Read Array Command (13)4.2Read Query Mode Command (13)4.2.1Query Structure Output (13)4.2.2Query Structure Overview (14)4.2.3Block Status Register (15)4.2.4CFI Query Identification String (15)4.2.5System Interface Information (16)4.2.6Device Geometry Definition (17)4.2.7Primary-Vendor Specific Extended Query Table (18)4.3Read Identifier Codes Command (19)4.4Read Status Register Command (20)4.5Clear Status Register Command (22)4.6Block Erase Command (22)4.7Block Erase Suspend Command (22)4.8Write to Buffer Command (23)4.9Byte/Word Program Commands (24)4.10Program Suspend Command (24)4.11Set Read Configuration Command (24)4.11.1Read Configuration (25)4.12Configuration Command (25)4.13Set Block Lock-Bit Commands (26)4.14Clear Block Lock-Bits Command (27)4.15Protection Register Program Command (27)4.15.1Reading the Protection Register (27)4.15.2Programming the Protection Register (27)4.15.3Locking the Protection Register (28)5.0Design Considerations (38)5.1Three-Line Output Control (38)5.2STS and Block Erase, Program, and Lock-Bit Configuration Polling (38)5.3Power Supply Decoupling (38)5.4Input Signal Transitions - Reducing Overshoots and Undershoots When Using28F128J3A, 28F640J3A, 28F320J3A28F128J3A, 28F640J3A, 28F320J3A Revision HistoryDate of Revision Version Description07/07/99-001Original Version08/03/99-002A0–A2 indicated on block diagram09/07/99-003Changed Minimum Block Erase time,I OL, I OH, Page Mode and ByteMode currents. Modified RP# on AC Waveform for Write Operations 12/16/99-004Changed Block Erase time and t AVWHRemoved all references to 5 V I/O operationCorrected Ordering Information, Valid Combinations entriesChanged Min program time to 211 µsAdded DU to Lead Descriptions tableChanged Chip Scale Package to Ball Grid Array PackageChanged default read mode to page modeRemoved erase queuing from Figure 10, Block Erase Flowchart03/16/00-005Added Program Max timeAdded Erase Max timeAdded Max page mode read currentMoved tables to correspond with sectionsFixed typographical errors in ordering information and DC parametertableRemoved V CCQ1 setting and changed V CCQ2/3 to V CCQ1/2Added recommended resister value for STS pinChange operation temperature rangeRemoved note that rp# could go to 14 VRemoved V OL of 0.45 VRemoved V OH of 2.4 VUpdated I CCR Typ valuesAdded Max lock-bit program and lock timesAdded note on max measurements06/26/00-006Updated cover sheet statement of 700 million units to one billion.Corrected Table 10 to show correct maximum program times.Corrected error in Max block program time in section 6.7Corrected typical erase time in section 6.72/15/01-007Updated cover page to reflect 100K minimum erase cycles.Updated cover page to reflect 110 ns 32M read speed.Removed Set Read Configuration command from Table 4.Updated Table 8 to reflect reserved bits are 1-7; not 2-7.Updated Table 16 bit 2 definition from R to PSS.Changed V PENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DCCharacteristicsUpdated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Sec-tion 6.5, AC Characteristics–Read-Only Operations (1,2)Updated write parameter W13 (t WHRL) from 90 ns to 500 ns, Section6.6, AC Characteristics–Write OperationsUpdated Max. Program Suspend Latency W16 (t WHRH1) from 30 to 75µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per-formance (1,2,3)04/13/01-008Revised Section 7.0, Ordering Information28F128J3A, 28F640J3A, 28F320J3A 1.0Product OverviewThe 0.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organizedas one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device isorganized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system. A 128-bit protection register has multiple uses, including unique flash deviceidentification.The device’s optimized architecture and interface dramatically increases read performance bysupporting page-mode reads. This read mode is ideal for non-clock memory systems.A Common Flash Interface (CFI) permits software algorithms to be used for entire families ofdevices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardizetheir existing interfaces for long-term compatibility.Scalable Command Set (SCS) allows a single, simple software driver in all host systems to workwith all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highestsystem/device data transfer rates and minimizes device and system-level implementation costs.A Command User Interface (CUI) serves as the interface between the system processor andinternal operation of the device. A valid command sequence written to the CUI initiates deviceautomation. An internal Write State Machine (WSM) automatically executes the algorithms andtimings necessary for block erase, program, and lock-bit configuration operations.A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—independent of other blocks. Each block can be independently erased 100,000 times. Block erasesuspend mode allows system software to suspend block erase to read or program data from anyother block. Similarly, program suspend allows system software to suspend programming (byte/word program and write-to-buffer operations) to read data or execute code from any other blockthat is not being suspended.Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programmingperformance. By using the Write Buffer, data is programmed in buffer increments. This feature canimprove system program performance more than 20 times over non-Write Buffer writes.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate blockerase and program operations. Lock-bit configuration operations set and clear lock-bits (Set BlockLock-Bit and Clear Block Lock-Bits commands).The status register indicates when the WSM’s block erase, program, or lock-bit configurationoperation is finished.The STS (STATUS) output gives an additional indicator of WSM activity by providing both ahardware signal of status (versus software polling) and status masking (interrupt masking forbackground block erase, for example). Status indication using STS minimizes both CPU overheadand system power consumption. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bitconfiguration. STS-high indicates that the WSM is ready for a new command, block erase is28F128J3A, 28F640J3A, 28F320J3A28F128J3A, 28F640J3A, 28F320J3A28F128J3A, 28F640J3A, 28F320J3A2.0Principles of OperationThe Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program,and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed powersupplies during block erasure, program, lock-bit configuration, and minimal processor overheadwith RAM-like interface timings.After initial device power-up or return from reset/power-down mode (see Section 3.0, “BusOperations” on page7), the device defaults to read array mode. Manipulation of external memorycontrol pins allows array read, standby, and output disable operations.Read array, status register, query, and identifier codes can be accessed through the CUI (CommandUser Interface) independent of the V PEN voltage. V PENH on V PEN enables successful blockerasure, programming, and lock-bit configuration. All functions associated with altering memorycontents—block erase, program, lock-bit configuration—are accessed via the CUI and verifiedthrough the status register.Commands are written using standard micro-processor write timings. The CUI contents serve asinput to the WSM, which controls the block erase, program, and lock-bit configuration. Theinternal algorithms are regulated by the WSM, including pulse repetition, internal verification, andmargining of data. Addresses and data are internally latched during program cycles.Interface software that initiates and polls progress of block erase, program, and lock-bitconfiguration can be stored in any block. This code is copied to and executed from system RAMduring flash memory updates. After successful completion, reads are again possible via the ReadArray command. Block erase suspend allows system software to suspend a block erase to read orprogram data from/to any other block. Program suspend allows system software to suspend aprogram to read data from any other flash memory array location.2.1Data ProtectionDepending on the application, the system designer may choose to make the V PEN switchable(available only when memory block erases, programs, or lock-bit configurations are required) orhardwired to V PENH. The device accommodates either design practice and encouragesoptimization of the processor-memory interface.When V PEN≤ V PENLK, memory contents cannot be altered. The CUI’s two-step block erase, byte/word program, and lock-bit configuration command sequences provide protection from unwantedoperations even when V PENH is applied to V PEN. All program functions are disabled when V CC isbelow the write lockout voltage V LKO or when RP# is V IL. The device’s block locking capabilityprovides additional protection from inadvertent code or data alteration by gating erase and programoperations.3.0Bus OperationsThe local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.NOTE:For single-chip applications, CE 2 and CE 1 can be strapped to GND.Figure 4. Memory MapTable 2. Chip Enable Truth TableCE 2CE 1CE 0DEVICE V IL V IL V IL Enabled V IL V IL V IH Disabled V IL V IH V IL Disabled V IL V IH V IH Disabled V IH V IL V IL Enabled V IH V IL V IH Enabled V IH V IH V IL Enabled V IHV IHV IHDisabled4.0Command DefinitionsWhen the V PEN voltage ≤ V PENLK, only read operations from the status register, query, identifiercodes, or blocks are enabled. Placing V PENH on V PEN additionally enables block erase, program,and lock-bit configuration operations.Device operations are selected by writing specific commands into the CUI. Table 4 defines thesecommands.Table 6. Example of Query Structure Output of a x16- and x8-Capable DeviceWord Addressing Byte AddressingOffset Hex Code Value Offset Hex Code ValueA15–A0 D15–D0A7–A0 D7–D00010h0051“Q”20h51“Q”0011h0052“R”21h51“Q”0012h0059“Y”22h52“R”0013h P_ID LO PrVendor23h52“R”0014h P_ID HI ID #24h59“Y”0015h P LO PrVendor25h59“Y”0016h P HI TblAdr26h P_ID LO PrVendor0017h A_ID LO AltVendor27h P_ID LO ID #0018h A_ID HI ID #28h P_ID HI ID #... ... ...... ... ...Table 8. Block Status RegisterOffset Length Description Address Value(BA+2)h(1)1Block Lock Status Register BA+2:--00 or --01BSR.0 Block Lock Status0 = Unlocked1 = LockedBA+2:(bit 0): 0 or 1BSR 1–7: Reserved for Future Use BA+2:(bit 1–7): 0 Table 9. CFI IdentificationOffset Length Description Add.HexCodeValue10h3Query-unique ASCII string “QRY”10--51“Q”11:--52“R”12:--59“Y”13h2Primary vendor command set and control interface ID code.13:--01 16-bit ID code for vendor-specified algorithms14:--00 15h2Extended Query Table primary algorithm address 15:--3116:--00Table 10. System Interface InformationOffset Length Description Add.HexCodeValue1Bh1V CC logic supply minimum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 BCD volts1B:--27 2.7 V1Ch1V CC logic supply maximum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 BCD volts1C:--36 3.6 V1Dh1V PP [programming] supply minimum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 HEX volts1D:--000.0 V1Eh1V PP [programming] supply maximum program/erase voltagebits 0–3 BCD 100 mVbits 4–7 HEX volts1E:--000.0 V1Fh1“n” such that typical single word program time-out = 2n µs1F:--07128 µs 20h1“n” such that typical max. buffer write time-out = 2n µs 20:--07128 µs 21h1“n” such that typical block erase time-out = 2n ms21:--0A 1 s 22h1“n” such that typical full chip erase time-out = 2n ms22:--00NA23h1“n” such that maximum word program time-out = 2n timestypical23:--04 2 ms24h1“n” such that maximum buffer write time-out = 2n times typical24:--04 2 ms 25h1“n” such that maximum block erase time-out = 2n times typical25:--0416 s 26h1“n” such that maximum chip erase time-out = 2n times typical26:--00NA28h2Flash device interface: x8 async x16 async x8/x16 async28:--02x8/ x1628:00,29:00 28:01,29:00 28:02,29:0029:--002Ah2“n” such that maximum number of bytes in write buffer = 2n2A:--05322B:--002Ch1Number of erase block regions within device:1. x = 0 means no erase blocking; the device erases in “bulk”2. x specifies the number of device or partition regions with one ormore contiguous same-size erase blocks3. Symmetrically blocked partitions have one blocking region4. Partition size = (total blocks) x (individual block size)2C:--0112Dh4Erase Block Region 1 Information 2D: bits 0–15 = y, y+1 = number of identical-size erase blocks2E: bits 16–31 = z, region erase block(s) size are z x 256 bytes2F:30:Address32 Mbit64 Mbit128 Mbit 27:--16--17--18 28:--02--02--02 29:--00--00--00 2A:--05--05--05 2B:--00--00--00 2C:--01--01--01 2D:--1F--3F--7F 2E:--00--00--00 2F:--00--00--00 30:--02--02--02Table 14. Burst Read InformationOffset(1) P = 31h LengthDescription(Optional Flash Features and Commands)Add.HexCodeValue(P+13)h1Page Mode Read capabilitybits 0–7 = “n” such that 2n HEX value represents the numberof read-page bytes. See offset 28h for device word width todetermine page-mode data output width. 00h indicates noread page buffer.44:--038 byte(P+14)h1Number of synchronous mode read configuration fields thatfollow. 00h indicates no burst capability.45:--000(P+15)h Reserved for future use46:• Block Is Unlocked DQ0 = 0• Block Is Locked DQ0 = 1• Reserved for Future Use DQ1–7Table 21. Byte-Wide Protection Register AddressingByte Use A8A7A6A5A4A3A2A1LOCK Both10000000LOCK Both10000000 0Factory100000011Factory100000012Factory100000103Factory100000104Factory100000115Factory100000116Factory100001007Factory100001008User100001019User10000101A User10000110B User10000110C User10000111D User10000111E User10001000F User100010005.0Design Considerations5.1Three-Line Output ControlThe device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:a.Lowest possible memory power dissipation.plete assurance that data bus contention will not occur.To use these control inputs efficiently, an address decoder should enable the device (see Table 2)while OE# should be connected to all memory devices and the system’s READ# control line. Thisassures that only selected memory devices have active outputs while de-selected memory devicesare in standby mode. RP# should be connected to the system POWERGOOD signal to preventunintended writes during system power transitions. POWERGOOD should also toggle duringsystem reset.5.2STS and Block Erase, Program, and Lock-Bit ConfigurationPollingSTS is an open drain output that should be connected to V CCQ by a pull-up resistor to provide ahardware method of detecting block erase, program, and lock-bit configuration completion. It isrecommended that a 2.5k resister be used between STS# and V CCQ. In default mode, it transitionslow after block erase, program, or lock-bit configuration commands and returns to High Z whenthe WSM has finished executing the internal algorithm. For alternate configurations of the STSpin, see the Configuration command.STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.STS, in default mode, is also High Z when the device is in block erase suspend (with programminginactive), program suspend, or in reset/power-down mode.5.3Power Supply DecouplingFlash memory power switching characteristics require careful device decoupling. System designersare interested in three supply current issues; standby current levels, active current levels andtransient peaks produced by falling and rising edges of CE0, CE1, CE2, and OE#. Transient currentmagnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control andproper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlashmemory devices draw their power from three V CC pins (these devices do not include a V PP pin), itis recommended that systems without separate power and ground planes attach a 0.1 µF ceramiccapacitor between each of the device’s three V CC pins (this includes V CCQ) and ground. Thesehigh-frequency, low-inductance capacitors should be placed as close as possible to package leadson each Intel StrataFlash memory device. Each device should have a 0.1 µF ceramic capacitorconnected between its V CC and GND. These high-frequency, low inductance capacitors should beplaced as close as possible to package leads. Additionally, for every eight devices, a 4.7 µFelectrolytic capacitor should be placed between V CC and GND at the array’s power supplyconnection. The bulk capacitor will overcome voltage slumps caused by PC board traceinductance.6.0Electrical Specifications6.1Absolute Maximum RatingsParameter Maximum Rating Temperature under Bias Expanded–25 °C to +85 °CStorage Temperature–65 °C to +125 °CVoltage On Any Pin –2.0 V to +5.0 V(1)Output Short Circuit Current100 mA(2)NOTES:1.All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and–0.2V on V CC and V PEN pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns.Maximum DC voltage on input/output pins, V CC, and V PEN is V CC +0.5 V which, during transitions, mayovershoot to V CC +2.0 V for periods <20 ns.2.Output shorted for no more than one second. No more than one output shorted at a time.NOTICE: This datasheet contains preliminary information on new products in production. The specifications aresubject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet beforefinalizing a design.Warning:Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.These are stress ratings only. Operation beyond the “Operating Conditions” is not recommendedand extended exposure beyond the “Operating Conditions” may affect device reliability.Symbol Parameter(1)Typ Max Unit Condition C IN Input Capacitance68pF V IN = 0.0 VC OUT Output Capacitance812pF V OUT = 0.0 VFigure 15. Transient Input/Output Reference Waveform for V CCQ = 3.0 V–3.6 V or V CCQ = 2.7 V–3.6 VTest Configuration C L (pF) V CCQ = V CC = 3.0 V−3.6 V30V CCQ = V CC = 2.7 V−3.6 V30。

ELC-PV28NNDR ELC-PV28NNDTELC that is micro, multi-functional, and with various instructionsInstruction SheetWARNINGx This instruc ion sheet only provides introductory information on electrical specification, functions, trouble-shoo ing and peripherals. For more information, please refer to “ELC System Manual ”.x This is an OPEN TYPE Controller. The ELC should be kept in an enclosure away from airborne dust, humidity, electric shock risk and vibration. Also, it is equipped with protective methods such as some special tools or keys to open the enclosure, so as to avoid the hazard to users and the damage to the ELC.x Never connect the AC main circuit power supply to any of the input/output terminals, as it will damage the ELC. Check all the wiring prior to power up. To avoid any electromagnetic noise, make sure the ELC is properly grounded. DO NOT touch terminals when power on.x Power, input and output (I/O) wiring must be in accordance wi h Class І, Division 2 wiring methods – Article 501-10(B)(1) of he National Electrical Code.x Suitable for use in Class І, Division 2, Groups A, B, C, D or non-hazardous loca ions only. x Explosion hazard - Substitution of components may impair suitability for Class І, Division 2.x Explosion hazard - DO NOT disconnect equipment unless power has been switched off or he area is known to be non hazardous. x Ambient temperature 55°C.xOperating Temperature Code T4A.1INTRODUCTION1.1 Model Name Explanation & PeripheralsThank you for choosing Eaton Logic Controller (ELC) series products. The ELC-PV series are 28-point (16 inputs + 12 outputs) controllers offering various instructions and 16K Steps program memory to connect with ELC series extension models which includes digital input/ output (max. 512 input/ output extension points), analog modules (A/D, D/A transforma ion and temperature units) and all kinds of new high-speed extension modules. Its 4-grouphigh-speed (200KHz) pulse outputs and the two new 2-axis interpola ion instructions satisfy all kinds of applications. ELC-PV is small in size and easy to install.1.2 Product Profile & Outline12345671410981312117039031718161560201921Unit: mm1 Status indicators of POWER, RUN, BAT LOW and ERROR2 COM1(RS-232) (Rx) indicator3 COM2(RS-485) (Tx) indicator 4/O point indicators 5 RUN/STOP switch6 VR0: Start-up by M1178/D1178 corresponding value7 VR1: Start-up by M1179/D1179 corresponding value 8/O terminal 9 COM1(RS-232) port10 D N rail clip11 Extension module positioning hole12 Extension port for wire to connect extension module/unit 13 D N rail track (35mm) 14 Extension unit clip15 RS-485 communication port (Master/Slave) 16 DC Power input17 3 pin removable terminal (standard component) 18 Power input cable (standard accessory)19 New high-speed extension module connection port 20 Nameplate21 Direct fastening hole2SPECIFICATIONStemSpecificationNoteOperation control method Stored program; cyclic scanning systemI/O control methodBatch processing and refresh /O status when ENDinstruction is executed With instruction that can immediately refresh I/O status Operation processing speed Basic instruction (min. 024 us) Application instruction Program language Instruction + ladder diagram + SFC With step instructionProgram capacity 15,872 STEPSSRAM + rechargeable battery + Flash Instruction type32 basic sequential instructions (including step ladder instructions)193 application instructionstemSpecificationNoteR e l a y (b i t )X External input relay X0 ~ X377, octal encoding; 256 points Total512 points Corresponds to external input pointsYExternal output relayY0 ~ Y377, octal encoding; 256 points Corresponds to external output pointsMAuxiliary relayGeneral purposeM0 ~ M499, 500 points (*2) Total4,096pointsThe contact can be On/Off in theprogram.Latched M500 ~ M999, 500 points (*3) M2000 ~ M4095, 2,096 points (*3) Special purposeM1000 ~ M1999, 1,000 points (part for latched)T Timer100 msT0 ~ T199, 200 points (*2) Total 256 points Timer indicated by TMR instruction. If timing reaches its target the T contact of the same No. will be On.T192 ~ T199 for subroutineT250 ~ T255, 6 accumulative points (*4) 10 ms T200 ~ T239, 40 points (*2)T240 ~ T245, 6 accumulative points (*4) 1 ms T246 ~ T249, 4 accumulative points (*4) C Counter16-bit counting up C0 ~ C99, 100 points (*2) Total253pointsCounter indicated by CNT (DCNT)instruction. If counting reaches itstarget, the C contact of the sameNo. will be On.C100 ~ C199, 100 points (*3) 32-bit counting up/downC200 ~ C219, 20 points (*2) C220 ~ C234, 15 points (*3)32-bit high-speedcounting up/downC235 ~ C244, 1 phase 1 input, 10 points (*3)C246 ~ C249, 1 phase 2 inputs, 4 points (*3)C251 ~ C254, 2 phase 2 inputs, 4 points (*3)S Step points InitialS0 ~ S9, 10 points (*2)Total 1,024 pointsUsed for SFCLatched area setup Start: D1214ΰK500α End: D1215ΰK899αFor zero returnS10 ~ S19, 10 points, used with IST instruction (*2)General purposeS20 ~ S499, 480 points (*2) Latched S500 ~ S899, 400 points (*3) For alarmS900 ~ S1023, 124 points (*3) R e g i s t e r (w o r d d a t a )T Present value in timer T0 ~ T255, 256 pointsWhen timing reaches the target, the contact continuity of timer appears. CPresent value in counterC0 ~ C199, 16-bit counter, 200 pointsWhen counting reaches the target, the contact continuity of counter appears.C200 ~ C254, 32-bit counter, 53 points DData registerGeneral purposeD0 ~ D199, 200 points (*2) Total 10,000 points Memory area for data storage can be used for special indirect indication.Latched D200 ~ D999, 800 points (*3) D2000 ~ D9999, 8,000 points (*3) Special purpose D1000 ~ D1999, 1,000 points For Indirect indicationE0 ~ E7, F0 ~ F7, 16 points (*1) N/A File register0 ~ 9,999 (10,000 points) (*4) Extension register for data storage I n d e xN For main control loop N0 ~ N7, 8 points Control point for main control loop PFor CJ, CALL instructions P0 ~ P255, 256 pointsPosition index of CJ and CALLII n t e r r u p t i o n s u b r o u t i n eExternal interruptionI0000/I0001(X0), I1000/I1001(X1), I2000/I2001(X2), I3000/I3001(X3), I4000/I4001(X4), I5000/I5001(X5),6 points (01: rising-edge trigger; 00: falling-edge trigger) Position index for interruption subroutineTime interruption I601~I699 (1ms), I701~I799 (1ms), I801~I899 (0.1ms) Interruption when high-speed counting reaches its target I010, I020, I030, I040, I050, 060, 6 points Interruption during pulse outputI110, I120, I130, I140, 4 points Interruption during communicationI150, I160, I170, 3 pointsC o n s t a n tK Decimal K-32,768 ~ K32,767 (16-bit operation)K-2,147,483,648 ~ K2,147,483,647ΰ32-bit operation αH HexH0000 ~ HFFFF (16-bit operation), H00000000 ~ HFFFFFFFF (32-bit operation) FFloating pointDisplaying floating points by the length of 32 bits with IEEE754 standard ±1.1755 × 10-38 ~ ±3.4028 × 10+38Serial communication ports (program write in/read out) COM1: RS-232; COM2: RS-485 (can be master or slave); COM1 and COM2 can be used at the same time Potentiometer / RTC Built-in 2 points VR / Built-in RTCSpecial extension moduleRight-side extension module and PB series share all modules (max. 8 modules extendable) Left-side can be connected with new high-speed extension modules (max. 8 module extendable)*1: Non-latched area cannot be modified.*2: The preset non-latched area can be modified into latched area by set ing up parameters. *3: The preset latched area can be modified into non-latched area by setting up parameters. *4: The fixed latched area cannot be modified.After the 24V DC power is switched off, the data in the latched area is stored in SRAM memory which is powered by he rechargeable battery. When the battery is damaged or cannot be changed, the data in the program and latched area will be lost. If the user needs to permanently save the data in he latched area in the program and device D, please refer to “Flash ROM permanently saved and recover mechanism ” as stated below. Permanently saved mechanism:The user can use ELCSoft (Options -> ELC<=>Flash) to indicate whether to permanently store the data in the latched area in the program (including password) and device D in Flash ROM memory (new indicated data will replace all data previously saved in the memory). Recover mechanism:If the rechargeable battery is in low voltage, resulting in the loss of data in the program, ELC will automatically restore he data in the latched area in the program and device D of Flash ROM into SRAM memory (M1176 = On) next time when 24V DC is re-powered. The ERROR LED flashing will remind the user that if the recorded program is able to resume its execution, the user only needs to shut down and re-power the ELC once to restart its operation (RUN).3ELECTRICAL SPECIFICATIONSInput pointTypeCurrent Motion levelResponding timeDC (Sink or Source)24VDC 5mAX0~X7,X12~X13,X16~X17Off On Ї165VDCX10~X11,X14~X15Off On Ї18.5VDCX0~X17 On Off І8VDCApprox. 10 ms (can be adjusted within the range of 10 ~ 60 ms by D1020 and D1021)Output pointType Current Voltage Max. loadingRespondingtimeMechani-cal life Electrical life relay-R1.5A/1 point (5A/COM)250VAC,Ї30VDC75VA (inductive) 90 W (resistive)Approx. 10 ms2×107times (without load)1.5×105times (5A 30VDC) 5×105 times (3A 120VAC)3×104 times (5A 250VAC)transistor-TGeneral: 0.3A/1 point @40ºCHigh-speed: І1kHz, 0.3A/1 point @ 40ºC; ≥ 1kHz,30mA/1point@40 ºC30VDCMax. 10kHz for Y5, Y7, Y10 ~ Y13Off On 20us On Off 30usMax. 200kHz for Y0, Y1, Y2, Y3, Y4, Y6Off On 0.2us On Off 0.2us4MODEL NAME & I/O CONFIGURATION5INSTALLATION & WIRING5.1 Mounting & WiringThe ELC can be secured to a cabinet by using the DIN rail of 35mm in height and 75mm in depth. When mounting ELC to DIN rail, be sure to use he end bracket to stop any side-to-side movement of ELC and reduce the chance of wires being loose. A small retaining clip is at the bottom of ELC. To secure ELC to DIN rail, place the clip onto he rail and gently push it up. To remove it, pull the retaining clip down and gently remove ELC from DIN rail, as shown in figure 1.Please use M4 screw (see figure 2) according to the dimension of the product. Please install ELC in an enclosurewith sufficient space around it to allow heat dissipation (see figure 3).9053.270101109.4D > 50 mmFigure 1Figure 2 (Unit: mm)Figure 35.2 Wiring1. Use 22-16AWG (1.5mm) single or multiple core wire on I/O wiring terminals. Thespecification of the terminal is shown in the figure on the left. The ELC terminalscrews shall be tightened to 1.95 kg-cm (1.7 in-lbs).2. DO NOT place the I/O signal wires and power supply wire in the same wiring duct.3. Use 60/75 ºC copper wires only.DO NOT install ELC in an environment with:1. Dust, smoke, metallic debris, corrosive or flammable gas2. High temperature, humidity3. Direct shock and vibration5.3 Power Input WiringThe power input of ELC-PV series is DC. When operating ELC-PV series, please make sure that:1. The power is connected to the two terminals, 24VDC and 0V, and the range of power is 20.4VDC ~28.8VDC. If the power voltage is less than 20.4VDC, ELC will stop running, all outputs will go “Off” andERROR indicator will flash continuously.2. A power shutdown of less than 10 ms will not affect the operation of ELC. However, power shutdown timethat is too long or a drop of power voltage will stop the operation of ELC and all outputs will go “Off”. When the power supplied again, ELC will automatically return to its operation. (Please be aware of the latched auxiliary relays and registers inside ELC when programming.)DC power input5.4 Input point wiringThere are two types of DC inputs, SINK and SOURCE.5.5 Output point wiring5.6 Relay (R) contact circuit wiring5.7 Transistor (T) contact circuit wiring6 TRIAL RUN■Preparation1. Prior to applying power, please verify that the power lines and the input/output wiring are correct. And beadvised not to supply 110V AC or 220V AC into he I/O terminals, or it might short-circuit the wiring and would cause direct damage to the ELC.2. After using the peripheral devices to write the program into he ELC and that the ERROR LED of the ELCis not on, it means that the program in use is legitimate, and it is now waiting for the user to give the RUN command.3. Use ELC-HHP to execute the forced On/Off test of the output contact.■Operation & test1. If the ERROR indicator does not flash, you can use the RUN/STOP switch or a peripheral device(ELC-HHP or ELCSoft) to give a RUN instruction. The RUN indicator should be continuously on at thistime. That the RUN indicator does not flash indicates ELC has no program in it.2. When ELC is in operation, use ELC-HHP or ELCSoft to monitor the set value or temporarily saved valuein timer (T), counter (C), and register (D) and force On/Off of output contacts. That the ERROR indicator is on (not flashes) indicates that part of the program exceeds the preset time-out. In this case, you have to set the RUN/STOP switch as STOP first, check special register D1008 and obtain the location in theprogram where time-out takes place. Please refer to he WDT instruction to solve this problem.■Operation of ELC basic sequential instruc ions & application instruc ions1. The basic sequential instructions and application instructions of ELC-PV series are compatible with allELC series ELCs. See Eaton “ELC System Manual” for relevant information.2. All ELC series ELCs are compatible with ELC-HHP handheld programming panel, ELCSoft ladderdiagram for program editing and exclusive transmission cables to connect with ELC-PV for programtransmission, ELC control, program monitoring and so on.7 TROUBLESHOOTINGBased on the indicators on the front panel, please check the following for errors:☼POWER indicatorWhen ELC is powered, the POWER LED indicator on the front panel will be on (in green). If this indicator is not on or the ERROR indicator keeps flashing when ELC is powered indicates that the power supply +24V are insufficient or DC power supply 24V is overloaded. In this case, change another 24V DC power supply. If the indicator is still off at this time, your ELC is malfunctioned. Send your ELC back to your distributor for repair.☼RUN indicatorCheck your ELC status. When ELC is running, this indicator will be on. You can use ELC-HHP, the ladder diagram editing program or the switch on the panel to RUN or STOP ELC.☼ERROR indicatorIf you enter illegal program into ELC or use instructions or devices that exceed their range, this indicator will flash (approx. every 1 second). When this happens, you have to obtain the error code from D1004 and save the address where the error occurs in register D1137 (if the error is a general circuit error, the address of D1137 will be invalid). Find out the cause of the error, amend the program and resend the program to ELC. If you cannot connect to ELC and this indicator keeps flashing quickly (approx. every 0.2 second), it means that the 24VDC power voltage is insufficient. Please check if the 24V DC is overloaded.If the ERROR indicator is on, you have to check the special relay M1008. If M1008 is on indicates that the execution time of program loop exceeds the preset time-out (in D1000). In this case, turn the RUN/STOP switch to STOP, check the special register D1008 and obtain the location in the program where the time-out takes place. Please refer to the WDT instruction to solve this problem. After amending the program, you only need to resend the program to stop the indicator from flashing. If the indicator still keeps flashing at this time, switch off he power and check if there is any interference existing or conductive matter inside ELC.For details of error codes (in D1004, hex coding), see “ELC System Ma nual: Programming”.☼BAT.LOW indicatorThe rechargeable lithium-ion battery in ELC-PV is mainly used on the latched procedure and data storage.The lithium-ion battery has been fully charged in the factory and is able to retain the latched procedure and data storage for 12 months. If ELC-PV has not been powered and used for more than 12 months, the battery will be out of power upon normal consumption and the procedure and data will be lost.The lithium-ion battery has longer life span than ordinary battery; therefore there is no need to change battery very frequently. You can charge the battery at any time without having to worry about a decrease in chargeability.You can also recharge the battery even when there is still power in the battery.Please be aware of the date of manufacturing; the charged battery can sustain for 12 months from this date. If you find that the BAT.LOW indicator stays on after ELC is powered, the battery voltage is low and the battery is being charged. ELC-PV has to remain on for more than 24 hours to fully charge the battery. If the indicator turns from on to “flash” (every 1 second), it indicates that the battery cannot be charged anymore. Please correctly process your data in time and send the ELC back to Eaton for changing a new battery.Precision of calendar timer:At 0̓C/32̓F, less than –117 seconds error per month.At 25̓C/77̓F, less than 52 seconds error per month.At 55̓C/131̓F, less than –132 seconds error per month.☼Input indicatorOn/Off of input point is indicated by input indicator or monitored by ELC-HHP. When the action condition of the input point is true, this indicator will be on. If abnormality is identified, check if the indicator and input circuit are normal. Use of electronic switch with too much electricity leakage often results in unexpected actions of the input point.☼Output indicatorOn/Off of output point is indicated by the output indicator. When the output indicator (On/Off) does notcorrespond to the action of its load, please be aware of the following:1. The output contact may be melted or blocked due to an over loaded or short-circuited load, which will resultin poor contact.2. If you are suspicious that he output point may execute an undesired action, check the output wiring circuitand whether the screw is properly tightened.。