LC89975MTER中文资料

1、引言UCC3895是美国德州仪器公司生产的移相谐振全桥软开关控制器，该系列控制器采用了先进的BCDM OS技术。

UCC3895在基本功能上与UC3875系列和UC3879系列控制器完全相同，同时增加了一些新的功能。

下面对其特点、引脚功能、电气参数、工作原理分别进行介绍。

2、特点和引脚说明2.1 特点（1）输出导通延迟时间编程可控；（2）自适应延迟时间设置功能；（3）双向振荡器同步功能；（4）电压模式控制或电流模式控制；（5）软启动/软关机和控制器片选功能编程可控，单引脚控制；（6）占空比控制范围0％～100％；（7）内置7MHz误差放大器；（8）最高工作频率达到1MHz；（9）工作电流低，500KHz下的工作电流仅为5mA；（10）欠压锁定状态下的电流仅为150μA。

2.2 引脚说明UCC3895和UCC2895移相谐振全桥软开关控制器采用SOIC-20、PDIP-20、TSSOP-20和PLCC-20四种封装形式，UCC1895采用CDIP-20和CLCC-20两种封装形式。

下面以PDIP-20为例进行介绍，其引脚排列如图1所示。

UCC3895系列移相谐振控制器采的引脚功能简介如下：·EAN（引脚1）：误差放大器反相输入端。

·EAOUT（引脚2）：误差放大器输出端。

在控制器内部，该端分别与PWM比较器和空载比较器的非反相输入端相连，并箝位于软启动电压。

当该端上的电压低于500mV时，控制器的输出级将被空载比较器关断。

当该端上的电压升至600mV时，输出级重新开通。

·RAMP（引脚3）：PWM比较器的非反相输入端。

在电压模式或平均电流模式下，该端接CT（引脚7）上的锯齿波信号；而在峰值电流模式下，该端接电流信号。

RAMP内接放电晶体管，该晶体管在振荡器死区时间内触发。

·REF（引脚4）：精密5V基准电压输出端。

控制器内部的基准电源一方面为控制器内部的电路供电，另一方面还能够向外接负载提供5mA的偏置电流。

LM2578A/LM3578A Switching RegulatorGeneral DescriptionThe LM2578A is a switching regulator which can easily be set up for such DC-to-DC voltage conversion circuits as the buck,boost,and inverting configurations.The LM2578A fea-tures a unique comparator input stage which not only has separate pins for both the inverting and non-inverting inputs, but also provides an internal1.0V reference to each input, thereby simplifying circuit design and p.c.board layout.The output can switch up to750mA and has output pins for its collector and emitter to promote design flexibility.An external current limit terminal may be referenced to either the ground or the V in terminal,depending upon the application.In addi-tion,the LM2578A has an on board oscillator,which sets the switching frequency with a single external capacitor from<1 Hz to100kHz(typical).The LM2578A is an improved version of the LM2578,offer-ing higher maximum ratings for the total supply voltage and output transistor emitter and collector voltages.Featuresn Inverting and non-inverting feedback inputsn 1.0V reference at inputsn Operates from supply voltages of2V to40Vn Output current up to750mA,saturation less than0.9V n Current limit and thermal shut downn Duty cycle up to90%Applicationsn Switching regulators in buck,boost,inverting,and single-ended transformer configurationsn Motor speed controln Lamp flasherConnection Diagram and Ordering InformationDual-In-Line Package00871129Order Number LM3578AM,LM2578AN or LM3578ANSee NS Package Number M08A or N08E February2005LM2578A/LM3578A Switching Regulator©2005National Semiconductor Corporation Functional Diagram00871101L M 2578A /L M 3578A 2Absolute Maximum Ratings(Note1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Total Supply Voltage50V Collector Output to Ground−0.3V to+50V Emitter Output to Ground(Note2)−1V to+50V Power Dissipation(Note3)Internally limited Output Current750mA Storage Temperature−65˚C to+150˚C Lead Temperature(soldering,10seconds)260˚C Maximum Junction Temperature150˚CESD Tolerance(Note4)2kVOperating RatingsAmbient Temperature RangeLM2578A−40˚C≤T A≤+85˚C LM3578A0˚C≤T A≤+70˚C Junction Temperature RangeLM2578A−40˚C≤T J≤+125˚C LM3578A0˚C≤T J≤+125˚CElectrical CharacteristicsThese specifications apply for2V≤V IN≤40V(2.2V≤V IN≤40V for T J≤−25˚C),timing capacitor C T=3900pF,and25%≤duty cycle≤75%,unless otherwise specified.Values in standard typeface are for T J=25˚C;values in boldface type apply for operation over the specified operating junction temperature range.LM2578A/Symbol Parameter Conditions Typical LM3578A Units(Note5)Limit(Note6) OSCILLATORf OSC Frequency20kHz24kHz(max)16kHz(min)∆f OSC/∆T Frequency Drift with Temperature−0.13%/˚C Amplitude550mV p-p REFERENCE/COMPARATOR(Note7)V R Input Reference I1=I2=0mA and 1.0V Voltage I1=I2=1mA±1%(Note8) 1.050/1.070V(max)0.950/0.930V(min)∆V R/∆V IN Input Reference Voltage LineRegulationI1=I2=0mA and0.003%/VI1=I2=1mA±1%(Note8)0.01/0.02%/V(max) I INV Inverting Input Current I1=I2=0mA,duty cycle=25%0.5µALevel Shift Accuracy Level Shift Current=1mA 1.0%10/13%(max)∆V R/∆t Input Reference Voltage Long TermStability100ppm/1000h OUTPUTV C(sat)Collector Saturation Voltage I C=750mA pulsed,Emittergrounded 0.7V0.90/1.2V(max)V E(sat)Emitter Saturation Voltage I O=80mA pulsed, 1.4VV IN=V C=40V 1.7/2.0V(max)I CES Collector Leakage Current V IN=V CE=40V,Emitter grounded,Output OFF 0.1µA200/250µA(max)BV CEO(SUS)Collector-Emitter Sustaining Voltage I SUST=0.2A(pulsed),V IN=060V50V(min) CURRENT LIMITV CL Sense Voltage Shutdown Level Referred to V IN or Ground110mV(Note9)80mV(min)160mV(max)LM2578A/LM3578A3Electrical Characteristics(Continued)These specifications apply for 2V ≤V IN ≤40V (2.2V ≤V IN ≤40V for T J ≤−25˚C),timing capacitor C T =3900pF,and 25%≤duty cycle ≤75%,unless otherwise specified.Values in standard typeface are for T J =25˚C;values in boldface type apply for operation over the specified operating junction temperature range.LM2578A/Symbol ParameterConditionsTypical LM3578A Units(Note 5)Limit (Note 6)CURRENT LIMIT ∆V CL /∆T Sense Voltage Temperature Drift 0.3%/˚C I CLSense Bias CurrentReferred to V IN 4.0µA Referred to ground0.4µA DEVICE POWER CONSUMPTION I SSupply CurrentOutput OFF,V E =0V2.0mA3.5/4.0mA (max)Output ON,I C =750mA pulsed,14mAV E =0VNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.Note 2:For T J ≥100˚C,the Emitter pin voltage should not be driven more than 0.6V below ground (see Application Information).Note 3:At elevated temperatures,devices must be derated based on package thermal resistance.The device in the 8-pin DIP must be derated at 95˚C/W,junction to ambient.The device in the surface-mount package must be derated at 150˚C/W,junction-to-ambient.Note 4:Human body model,1.5k Ωin series with 100pF.Note 5:Typical values are for T J =25˚C and represent the most likely parametric norm.Note 6:All limits guaranteed at room temperature (standard type face)and at temperature extremes (bold type face).Room temperature limits are 100%production tested.Limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC)methods.All limits are used to calculate AOQL.Note 7:Input terminals are protected from accidental shorts to ground but if external voltages higher than the reference voltage are applied,excessive current will flow and should be limited to less than 5mA.Note 8:I 1and I 2are the external sink currents at the inputs (refer to Test Circuit).Note 9:Connection of a 10k Ωresistor from pin 1to pin 4will drive the duty cycle to its maximum,typically 90%.Applying the minimum Current Limit Sense Voltage to pin 7will not reduce the duty cycle to less than 50%.Applying the maximum Current Limit Sense Voltage to pin 7is certain to reduce the duty cycle below 50%.Increasing this voltage by 15mV may be required to reduce the duty cycle to 0%,when the Collector output swing is 40V or greater (see Ground-Referred Current Limit Sense Voltage typical curve).Typical Performance CharacteristicsOscillator Frequency Changewith TemperatureOscillator Voltage Swing0087113200871133L M 2578A /L M 3578A 4Typical Performance Characteristics(Continued)Input Reference Voltage Drift with TemperatureCollector Saturation Voltage(Sinking Current,Emitter Grounded)0087113400871135Emitter Saturation Voltage(Sourcing Current,Collector at V in )Ground ReferredCurrent Limit Sense Voltage0087113600871137Current Limit Sense Voltage Drift with Temperature Current Limit Response Time for Various Over Drives0087113800871139LM2578A/LM3578A5Typical Performance Characteristics(Continued)Current Limit Sense Voltagevs Supply VoltageSupply Current0087114000871141Supply CurrentCollector Current with Emitter Output Below Ground0087114200871143Test Circuit*Parameter tests can be made using the test circuit shown.Select the desired V in ,collector voltage and duty cycle with adjustable power supplies.A digital volt meter with an input resistance greater than 100M Ωshould be used to measure the following:Input Reference Voltage to Ground;S1in either position.Level Shift Accuracy (%)=(T P3(V)/1V)x 100%;S1at I 1=I 2=1mAInput Current (mA)=(1V −T p3(V))/1M Ω:S1at I 1=I 2=0mA.Oscillator parameters can be measured at T p4using a fre-quency counter or an oscilloscope.The Current Limit Sense Voltage is measured by connecting an adjustable 0-to-1V floating power supply in series with the current limit terminal and referring it to either the ground or the V in terminal.Set the duty cycle to 90%and monitor test point T P5while adjusting the floating power supply voltage until the LM2578A’s duty cycle just reaches 0%.This voltage is the Current Limit Sense Voltage.The Supply Current should be measured with the duty cycle at 0%and S1in the I 1=I 2=0mA position.*LM2578A specifications are measured using automated test equipment.This circuit is provided for the customer’s convenience when checking parameters.Due to possible variations in testing conditions,the measured values from these testing procedures may not match those of the factory.L M 2578A /L M 3578A 6Test Circuit*(Continued)00871103 Op amp supplies are±15VDVM input resistance>100MΩ*LM2578max duty cycle is90%Definition of TermsInput Reference Voltage:The voltage(referred to ground) that must be applied to either the inverting or non-inverting input to cause the regulator switch to change state(ON or OFF).Input Reference Current:The current that must be drawn from either the inverting or non-inverting input to cause the regulator switch to change state(ON or OFF).Input Level Shift Accuracy:This specification determines the output voltage tolerance of a regulator whose output control depends on drawing equal currents from the inverting and non-inverting inputs(see the Inverting Regulator of Fig-ure21,and the RS-232Line Driver Power Supply of Figure 23).Level Shift Accuracy is tested by using two equal-value resistors to draw current from the inverting and non-inverting input terminals,then measuring the percentage difference in the voltages across the resistors that produces a controlled duty cycle at the switch output.Collector Saturation Voltage:With the inverting input ter-minal grounded thru a10kΩresistor and the output transis-tor’s emitter connected to ground,the Collector Saturation-Voltage is the collector-to-emitter voltage for a given collector current.Emitter Saturation Voltage:With the inverting input termi-nal grounded thru a10kΩresistor and the output transistor’s collector connected to V in,the Emitter Saturation Voltage is the collector-to-emitter voltage for a given emitter current. Collector Emitter Sustaining Voltage:The collector-emitter breakdown voltage of the output transistor,mea-sured at a specified current.Current Limit Sense Voltage:The voltage at the CurrentLimit pin,referred to either the supply or the ground terminal,which(via logic circuitry)will cause the output transistor toturn OFF and resets cycle-by-cycle at the oscillator fre-quency.Current Limit Sense Current:The bias current for theCurrent Limit terminal with the applied voltage equal to theCurrent Limit Sense Voltage.Supply Current:The IC power supply current,excluding thecurrent drawn through the output transistor,with the oscilla-tor operating.Functional DescriptionThe LM2578A is a pulse-width modulator designed for useas a switching regulator controller.It may also be used inother applications which require controlled pulse-width volt-age drive.A control signal,usually representing output voltage,fed intothe LM2578A’s comparator is compared with an internally-generated reference.The resulting error signal and the os-cillator’s output are fed to a logic network which determineswhen the output transistor will be turned ON or OFF.Thefollowing is a brief description of the subsections of theLM2578A.COMPARATOR INPUT STAGEThe LM2578A’s comparator input stage is unique in that boththe inverting and non-inverting inputs are available to theuser,and both contain a1.0V reference.This is accom-plished as follows:A1.0V reference is fed into a modifiedvoltage follower circuit(see FUNCTIONAL DIAGRAM).When both input pins are open,no current flows through R1LM2578A/LM3578A7Functional Description(Continued)and R2.Thus,both inputs to the comparator will have the potential of the 1.0V reference,V A .When one input,for example the non-inverting input,is pulled ∆V away from V A ,a current of ∆V/R1will flow through R1.This same current flows through R2,and the comparator sees a total voltage of 2∆V between its inputs.The high gain of the system,through feedback,will correct for this imbalance and return both inputs to the 1.0V level.This unusual comparator input stage increases circuit flex-ibility,while minimizing the total number of external compo-nents required for a voltage regulator system.The inverting switching regulator configuration,for example,can be set up without having to use an external op amp for feedback polarity reversal (see TYPICAL APPLICATIONS).OSCILLATORThe LM2578A provides an on-board oscillator which can be adjusted up to 100kHz.Its frequency is set by a single external capacitor,C 1,as shown in Figure 1,and follows the equationf OSC =8x10−5/C 1The oscillator provides a blanking pulse to limit maximum duty cycle to 90%,and a reset pulse to the internal circuitry.OUTPUT TRANSISTORThe output transistor is capable of delivering up to 750mA with a saturation voltage of less than 0.9V.(see Collector Saturation Voltage and Emitter Saturation Voltage curves).The emitter must not be pulled more than 1V below ground (this limit is 0.6V for T J ≥100˚C).Because of this limit,an external transistor must be used to develop negative output voltages (see the Inverting Regulator Typical Application).Other configurations may need protection against violation of this limit (see the Emitter Output section of the Applica-tions Information).CURRENT LIMITThe LM2578A’s current limit may be referenced to either the ground or the V in pins,and operates on a cycle-by-cycle basis.The current limit section consists of two comparators:one with its non-inverting input referenced to a voltage 110mV below V in ,the other with its inverting input referenced110mV above ground (see FUNCTIONAL DIAGRAM).The current limit is activated whenever the current limit terminal is pulled 110mV away from either V in or ground.Applications InformationCURRENT LIMITAs mentioned in the functional description,the current limit terminal may be referenced to either the V in or the ground terminal.Resistor R3converts the current to be sensed into a voltage for current limit detection.CURRENT LIMIT TRANSIENT SUPPRESSIONWhen noise spikes and switching transients interfere with proper current limit operation,R1and C1act together as a low pass filter to control the current limit circuitry’s response time.Because the sense current of the current limit terminal varies according to where it is referenced,R1should be less than 2k Ωwhen referenced to ground,and less than 100Ωwhen referenced to V in .00871104FIGURE 1.Value of Timing Capacitor vsOscillator Frequency00871115FIGURE 2.Current Limit,Ground Referred00871116FIGURE 3.Current Limit,V in ReferredL M 2578A /L M 3578A 8Applications Information(Continued)C.L.SENSE VOLTAGE MULTIPLICATIONWhen a larger sense resistor value is desired,the voltage divider network,consisting of R1and R2,may be used.This effectively multiplies the sense voltage by(1+R1/R2).Also, R1can be replaced by a diode to increase current limit sense voltage to about800mV(diode V f+110mV).UNDER-VOLTAGE LOCKOUTUnder-voltage lockout is accomplished with few external components.When V in becomes lower than the zener breakdown voltage,the output transistor is turned off.This occurs because diode D1will then become forward biased, allowing resistor R3to sink a greater current from the non-inverting input than is sunk by the parallel combination of R1 and R2at the inverting terminal.R3should be one-fifth of the value of R1and R2in parallel.MAXIMUM DUTY CYCLE LIMITINGThe maximum duty cycle can be externally limited by adjust-ing the charge to discharge ratio of the oscillator capacitor with a single external resistor.Typical values are50µA for the charge current,450µA for the discharge current,and a voltage swing from200mV to750mV.Therefore,R1is selected for the desired charging and discharging slopes and C1is readjusted to set the oscillator frequency.00871117 FIGURE4.Current Limit Transient Suppressor,Ground Referred00871118 FIGURE5.Current Limit Transient Suppressor,V in Referred00871119 FIGURE6.Current Limit Sense Voltage Multiplication,Ground Referred00871120FIGURE7.Current Limit Sense Voltage Multiplication,V in Referred00871122FIGURE8.Under-Voltage LockoutLM2578A/LM3578A9Applications Information(Continued)DUTY CYCLE ADJUSTMENTWhen manual or mechanical selection of the output transis-tor’s duty cycle is needed,the cirucit shown below may be used.The output will turn on with the beginning of each oscillator cycle and turn off when the current sunk by R2and R3from the non-inverting terminal becomes greater than the current sunk from the inverting terminal.With the resistor values as shown,R3can be used to adjust the duty cycle from 0%to 90%.When the sum of R2and R3is twice the value of R1,the duty cycle will be about 50%.C1may be a large electrolytic capacitor to lower the oscillator frequency below 1Hz.REMOTE SHUTDOWNThe LM2578A may be remotely shutdown by sinking a greater current from the non-inverting input than from the inverting input.This may be accomplished by selecting re-sistor R3to be approximately one-half the value of R1and R2in parallel.EMITTER OUTPUTWhen the LM2578A output transistor is in the OFF state,if the Emitter output swings below the ground pin voltage,the output transistor will turn ON because its base is clamped near ground.The Collector Current with Emitter Output Be-low Ground curve shows the amount of Collector current drawn in this mode,vs temperature and Emitter voltage.When the Collector-Emitter voltage is high,this current will cause high power dissipation in the output transistor and should be avoided.This situation can occur in the high-current high-voltage buck application if the Emitter output is used and the catch diode’s forward voltage drop is greater than 0.6V.A fast-recovery diode can be added in series with the Emitter output to counter the forward voltage drop of the catch diode (see Figure 2).For better efficiency of a high output current buck regulator,an external PNP transistor should be used as shown in Figure 16.SYNCHRONIZING DEVICESWhen several devices are to be operated at once,their oscillators may be synchronized by the application of an external signal.This drive signal should be a pulse waveform with a minimum pulse width of 2µs.and an amplitude from00871121FIGURE 9.Maximum Duty Cycle Limiting00871123FIGURE 10.Duty Cycle Adjustment00871124FIGURE 11.Shutdown Occurs when V L is High00871130FIGURE 12.D1Prevents Output Transistor from Improperly Turning ON due to D2’s Forward Voltage L M 2578A /L M 3578A 10Applications Information(Continued)1.5V to2.0V.The signal source must be capable of 1.)driving capacitive loads and 2.)delivering up to 500µA for each LM2578A.Capacitors C1thru CN are to be selected for a 20%slower frequency than the synchronization frequency.Typical ApplicationsThe LM2578A may be operated in either the continuous or the discontinuous conduction mode.The following applica-tions (except for the Buck-Boost Regulator)are designed for continuous conduction operation.That is,the inductor cur-rent is not allowed to fall to zero.This mode of operation has higher efficiency and lower EMI characteristics than the dis-continuous mode.BUCK REGULATORThe buck configuration is used to step an input voltage down to a lower level.Transistor Q1in Figure 14chops the input DC voltage into a squarewave.This squarewave is then converted back into a DC voltage of lower magnitude by the low pass filter consisting of L1and C1.The duty cycle,D,of the squarewave relates the output voltage to the input volt-age by the following equation:V out =D x V in =V in x (t on )/(t on +t off ).Figure 15is a 15V to 5V buck regulator with an output current,I o ,of 350mA.The circuit becomes discontinuous at 20%of I o(max),has 10mV of output voltage ripple,an effi-ciency of 75%,a load regulation of 30mV (70mA to 350mA)and a line regulation of 10mV (12≤V in ≤18V).Component values are selected as follows:R1=(V o −1)x R2where R2=10k ΩR3=V/I sw(max)R3=0.15Ωwhere:V is the current limit sense voltage,0.11VI sw(max)is the maximum allowable current thru the output transistor.L1is the inductor and may be found from the inductance calculation chart (Figure 16)as follows:Given V in =15VV o =5VI o(max)=350mA f OSC =50kHzDiscontinuous at 20%of I o(max).Note that since the circuit will become discontinuous at 20%of I o(max),the load current must not be allowed to fall below 70mA.00871125FIGURE 13.Synchronizing Devices00871105FIGURE 14.Basic Buck RegulatorLM2578A/LM3578A11Typical Applications(Continued)00871106V in =15V R3=0.15ΩV o =5V C1=1820pF V ripple =10mV C2=220µF I o =350mA C3=20pF f osc =50kHz L1=470µH R1=40k ΩD1=1N5818R2=10k ΩFIGURE 15.Buck or Step-Down RegulatorL M 2578A /L M 3578A 12LM2578A/LM3578A Typical Applications(Continued)00871131FIGURE16.DC/DC Inductance Calculator13Typical Applications(Continued)Step 1:Calculate the maximum DC current through the inductor,I L(max).The necessary equations are indicated at the top of the chart and show that I L(max)=I o(max)for the buck configuration.Thus,I L(max)=350mA.Step 2:Calculate the inductor Volts-sec product,E-T op ,according to the equations given from the chart.For the Buck:E-T op =(V in −V o )(V o /V in )(1000/f osc )=(15−5)(5/15)(1000/50)=66V-µs.with the oscillator frequency,f osc ,expressed in kHz.Step 3:Using the graph with axis labeled “Discontinuous At %I OUT ”and “I L(max,DC)”find the point where the desired maximum inductor current,I L(max,DC)intercepts the desired discontinuity percentage.In this example,the point of interest is where the 0.35A line intersects with the 20%line.This is nearly the midpoint of the horizontal axis.Step 4:This last step is merely the translation of the point found in Step 3to the graph directly below it.This is accom-plished by moving straight down the page to the point which intercepts the desired E-T op .For this example,E-T op is 66V-µs and the desired inductor value is 470µH.Since this example was for 20%discontinuity,the bottom chart could have been used directly,as noted in step 3of the chart instructions.For a full line of standard inductor values,contact Pulse Engineering (San Diego,Calif.)regarding their PE526XX series,or A.I.E.Magnetics (Nashville,Tenn.).A more precise inductance value may be calculated for the Buck,Boost and Inverting Regulators as follows:BUCKL =V o (V in −V o )/(∆I L V in f osc )BOOSTL =V in (V o −V in )/(∆I L f osc V o )INVERTL =V in |V o |/[∆I L (V in +|V o |)f osc ]where ∆I L is the current ripple through the inductor.∆I L is usually chosen based on the minimum load current expected of the circuit.For the buck regulator,since the inductor current I L equals the load current I O ,∆I L =2•I O(min)∆I L =140mA for this circuit.∆I L can also be interpreted as ∆I L =2•(Discontinuity Factor)•I Lwhere the Discontinuity Factor is the ratio of the minimum load current to the maximum load current.For this example,the Discontinuity Factor is 0.2.The remainder of the components of Figure 15are chosen as follows:C1is the timing capacitor found in Figure 1.C2≥V o (V in −V o )/(8f osc 2V in V ripple L1)where V ripple is the peak-to-peak output voltage ripple.C3is necessary for continuous operation and is generally in the 10pF to 30pF range.D1should be a Schottky type diode,such as the 1N5818or 1N5819.BUCK WITH BOOSTED OUTPUT CURRENTFor applications requiring a large output current,an external transistor may be used as shown in Figure 17.This circuit steps a 15V supply down to 5V with 1.5A of output current.The output ripple is 50mV,with an efficiency of 80%,a load regulation of 40mV (150mA to 1.5A),and a line regulation of 20mV (12V ≤V in ≤18V).Component values are selected as outlined for the buck regulator with a discontinuity factor of 10%,with the addition of R4and R5:R4=10V BE1B f /I pR5=(V in −V −V BE1−V sat )B f /(I L(max,DC)+I R4)where:V BE1is the V BE of transistor Q1.V sat is the saturation voltage of the LM2578A output transis-tor.V is the current limit sense voltage.B f is the forced current gain of transistor Q1(B f =30for Figure 17).I R4=V BE1/R4I p =I L(max,DC)+0.5∆I LL M 2578A /L M 3578A 14Typical Applications(Continued)BOOST REGULATORThe boost regulator converts a low input voltage into a higher output voltage.The basic configuration is shown in Figure 18.Energy is stored in the inductor while the transis-tor is on and then transferred with the input voltage to the output capacitor for filtering when the transistor is off.Thus,V o =V in +V in (t on /t off ).The circuit of Figure 19converts a 5V supply into a 15V supply with 150mA of output current,a load regulation of 14mV (30mA to 140mA),and a line regulation of 35mV (4.5V ≤V in ≤8.5V).R1=(V o −1)R2where R2=10k Ω.R3=V/(I L(max,DC)+0.5∆I L )where:∆I L =2(I LOAD(min))(V o /V in )∆I L is 200mA in this example.R4,C3and C4are necessary for continuous operation and are typically 220k Ω,20pF,and 0.0022µF respectively.C1is the timing capacitor found in Figure 1.C2≥I o (V o −V in )/(f osc V o V ripple ).00871108V in =15V R4=200ΩV o =5V R5=330ΩV ripple =50mV C1=1820pF I o =1.5AC2=330µFf osc =50kHz C3=20pF R1=40k ΩL1=220µH R2=10k ΩD1=1N5819R3=0.05ΩQ1=D45FIGURE 17.Buck Converter with Boosted Output Current00871109FIGURE 18.Basic Boost Regulator00871111V in =5V R4=200k ΩV o =15V C1=1820pF V ripple =10mV C2=470µF I o =140mA C3=20pF f osc =50kHz C4=0.0022µF R1=140k ΩL1=330µH R2=10k ΩD1=1N5818R3=0.15ΩFIGURE 19.Boost or Step-Up RegulatorLM2578A/LM3578A15Typical Applications(Continued)D1is a Schottky type diode such as a 1N5818or 1N5819.L1is found as described in the buck converter section,using the inductance chart for Figure 16for the boost configuration and 20%discontinuity.INVERTING REGULATORFigure 20shows the basic configuration for an inverting regulator.The input voltage is of a positive polarity,but the output is negative.The output may be less than,equal to,or greater in magnitude than the input.The relationship be-tween the magnitude of the input voltage and the output voltage is V o =V in x (t on /t off ).Figure 21shows an LM2578A configured as a 5V to −15V polarity inverter with an output current of 300mA,a load regulation of 44mV (60mA to 300mA)and a line regulation of 50mV (4.5V ≤V in ≤8.5V).R1=(|V o |+1)R2where R2=10k Ω.R3=V/(I L(max,DC)+0.5∆I L ).R4=10V BE1B f /(I L (max,DC)+0.5∆I L )where:V,V BE1,V sat ,and B f are defined in the “Buck Converter with Boosted Output Current”section.∆I L =2(I LOAD(min))(V in +|V o |)/V INR5is defined in the “Buck with Boosted Output Current”section.R6serves the same purpose as R4in the Boost Regulator circuit and is typically 220k Ω.C1,C3and C4are defined in the “Boost Regulator”section.C2≥I o |V o |/[f osc (|V o |+V in )V ripple ]L1is found as outlined in the section on buck converters,using the inductance chart of Figure 16for the invert con-figuration and 20%discontinuity.BUCK-BOOST REGULATORThe Buck-Boost Regulator,shown in Figure 22,may step a voltage up or down,depending upon whether or not the desired output voltage is greater or less than the input voltage.In this case,the output voltage is 12V with an input voltage from 9V to 15V.The circuit exhibits an efficiency of 75%,with a load regulation of 60mV (10mA to 100mA)and a line regulation of 52mV.R1=(V o −1)R2where R2=10k ΩR3=V/0.75AR4,C1,C3and C4are defined in the “Boost Regulator”section.D1and D2are Schottky type diodes such as the 1N5818or 1N5819.where:V d is the forward voltage drop of the diodes.V sat is the saturation voltage of the LM2578A output transis-tor.V sat1is the saturation voltage of transistor Q1.L1≥(V in −V sat −V sat1)(t on /I p )00871110FIGURE 20.Basic Inverting Regulator00871112V in =5V R4=190ΩV o =−15V R5=82ΩV ripple =5mV R6=220k ΩI o =300mA C1=1820pF I min =60mAC2=1000µFf osc =50kHz C3=20pF R1=160k ΩC4=0.0022µF R2=10k ΩL1=150µH R3=0.01ΩD1=1N5818FIGURE 21.Inverting RegulatorL M 2578A /L M 3578A16。

AT89C52 中文资料
AT89S52 低功耗高性能CMOS 8 位单片机，片内8k Bytes ISP(In-system
programmable)的可反复擦写1000 次的FLASH 只读程序存储器，器件采用ATMEL 公司之高密度、非易失性存储技术制造，兼容标准MCS-51 指令系统及80C51 引脚结构，片上Flash 允许程序存储器在系统可编程，亦适于常规编程器。

单芯片上，拥有8 位CPU 及在系统可编程FLASH，使AT89S52 为众多嵌入式控制应用系统提供高灵活、超有效之解决方案。

AT89S52 之特点：40 个引脚，8k Bytes Flash 片内程序存储器，256 bytes
的随机存取数据存储器(RAM)，32 个外部双向输入/输出(I/O)口，5 个中断优先级2 层中断嵌套中断，2 个16 位可编程定时计数器,2 个全双工串行通信口，看门狗(WDT)电路，片内时钟振荡器。

AT89C52 低电压高性能CMOS 8 位单片机，片内8k bytes 的可反复擦写的FLASH 只读程序存储器及256 bytes 的随机存取数据存储器(RAM)，器件采用ATMEL 公司的高密度、非易失性存储技术生产，兼容标准MCS-51 指令
系统，片内置通用8 位中央处理器及FLASH 存储单元，功能强大之
AT89C52 单片机可为您提供许多较复杂系统控制之应用场合。

AT89C52 有40 个引脚，32 个外部双向输入/输出(I/O)端口，同时内含2 个。

PRECHARGEThe PRECHARGE command is used to de-activate the open row in a particular bank orin all banks. The bank(s) are available for a subsequent row access a specified time (t RP)after the PRECHARGE command is issued, except in the case of concurrent auto pre-charge. A READ or WRITE command to a different bank is allowed during a concurrentauto precharge as long as it does not interrupt the data transfer in the current bank anddoes not violate any other timing parameters. Input A10 determines whether one or allbanks are precharged. In the case where only one bank is precharged, inputs BA[2:0] se-lect the bank; otherwise, BA[2:0] are treated as “Don’t Care.”After a bank is precharged, it is in the idle state and must be activated prior to any READor WRITE commands being issued to that bank. A PRECHARGE command is treated asa NOP if there is no open row in that bank (idle state) or if the previously open row isalready in the process of precharging. However, the precharge period is determined bythe last PRECHARGE command issued to the bank.REFRESHThe REFRESH command is used during normal operation of the DRAM and is analo-gous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersis-tent, so it must be issued each time a refresh is required. The addressing is generated bythe internal refresh controller. This makes the address bits a “Don’t Care” during a RE-FRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs(maximum when T Cื 85°C or 3.9μs maximum when T Cื 95°C). The REFRESH periodbegins when the REFRESH command is registered and ends t RFC (MIN) later.To allow for improved efficiency in scheduling and switching between tasks, some flexi-bility in the absolute refresh interval is provided. A maximum of eight REFRESH com-mands can be posted to any given DRAM, meaning that the maximum absolute intervalbetween any REFRESH command and the next REFRESH command is nine times themaximum average interval refresh rate. Self refresh may be entered with up to eight RE-FRESH commands being posted. After exiting self refresh (when entered with postedREFRESH commands), additional posting of REFRESH commands is allowed to the ex-tent that the maximum number of cumulative posted REFRESH commands (both pre-and post-self refresh) does not exceed eight REFRESH commands.At any given time, a maximum of 16 REFRESH commands can be issued within2 x t REFI.Figure 38: Refresh ModeDon’t CareIndicates breakin time scale CK CK#Command CKE AddressA10BA[2:0]DQ 4DM 4DQS, DQS#4Notes: 1.NOP commands are shown for ease of illustration; other valid commands may be possi-ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see Power-Down Mode (page 174)).2.The second REFRESH is not required, but two back-to-back REFRESH commands are shown.3.“Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks).4.For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.5.Only NOP and DES commands are allowed after a REFRESH command and until t RFC (MIN) is satisfied.SELF REFRESHThe SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in self refresh mode, the DRAM retains data without ex-ternal clocking. Self refresh mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous oper-ating range (see Input Clock Frequency Change (page 117)). All power supply inputs (including V REFCA and V REFDQ ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. V REFDQ may float or not drive V DDQ /2 while in self refresh mode under the following conditions:•V SS < V REFDQ < V DD is maintained •V REFDQ is valid and stable prior to CKE going back HIGH •The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid •All other self refresh mode exit timing requirements are met。

1Features•256 x 256 channel non-blocking switch •Programmable frame integrity for wideband channels•Automatic identification of ST-BUS/GCI interface backplanes•Per channel tristate control •Patented message mode•Non-multiplexed microprocessor interface •Single +5 volt supply•Available in DIP-40, PLCC-44 and QFP-44 packages•Pin compatible with MT8980 deviceApplications•Medium size digital switch matrices•Hyperchannel switching (e.g., ISDN H0)•ST-BUS/MVIP ™ interface functions •Serial bus control and monitoring•Centralized voice processing systems •Data multiplexerDescriptionThe MT8985 Enhanced Digital Switch device is an upgraded version of the popular MT8980D DigitalSwitch (DX). It is pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs and any ST-BUS/MVIP environment. It provides simultaneous connections for up to 256 64kb/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. As the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. The constant throughput delay feature allows grouped channels such as ISDN H0 to be switched through the device maintaining its sequence integrity. The MT8985 is ideal for medium sized mixed voice/data switch and voice processing applications.September 2005Ordering InformationMT8985AE 40 Pin PDIP Tubes MT8985AP 44 Pin PLCC Tubes MT8985AL 44 Pin MQFP Trays MT8985APR 44 Pin PLCC Tape & Reel MT8985AP144 Pin PLCC*TubesMT8985APR144 Pin PLCC*Tape & Reel MT8985AE140 Pin PDIP*Tubes MT8985AL144 Pin MQFP*Trays*Pb Free Matte Tin-40°C to +85°CCMOS ST-BUS TM FamilyMT8985Enhanced Digital SwitchData SheetFigure 1 - Functional Block Diagramhttps:///MT8985Data SheetChanges SummaryThe following table captures the changes from the May 2005 issue.Figure 2 - Pin ConnectionsPage ItemChange7Figure 3 - “Address Memory Map“•corrected Address Memory MapDTA STi0STi1STi2STi3STi4STi5STi6STi7VDD F0i C4i A0A1A2A3A4A5DS CSTo ODE STo0STo1STo2STo3STo4STo5STo6STo7VSS D0D1D2D3D4D5D6D7CS1654324443424140789101112131415163938373635343332313023181920212224252627281729STi3STi4STi5STi6STi7VDD F0i C4i A0A1A2STo3STo4STo5STo6STo7VSS D0D1D2D3D4N C S T i 1D T A O D E S T o 1N CS T i 2S T i 0C S T o S T o 0S T o 2N C A 4D S C S D 6N CA 3A 5R /W D 740 PIN PLASTIC DIP44 PIN PLCC2345678910111213141516171819201R/W4039383736353433323130292827262524232221D 5394443424140383736353412345678910333231302928272625241712131415161819202122112344 PIN QFPSTi3STi4STi5STi6STi7VDD F0i C4i A0A1A2N C A 4D S C S D 6N CA 3A 5R /W D 7D 5STo3STo4STo5STo6STo7VSS D0D1D2D3D4N C S T i 1D T A O D E S T o 1N CS T i 2S T i 0C S T o S T o 0S T o 2https:///MT8985Data SheetPin DescriptionPin #Name Description40 DIP44PLCC 44QFP1240DTAData Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output.2-93-57-1141-431-5STi0-STi7ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 channels at data rates of 2.048 Mbit/s.10126V DD +5 Volt Power Supply rail.11137F0iFrame Pulse (Input): This input accepts and automatically identifies framesynchronization signals formatted according to different backplane specifications such as ST-BUS and GCI.12148C4iClock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.13-1815-1719-219-1113-15A0-A5Address 0 to 5 (Inputs). These lines provide the address to MT8985 internalregisters.192216DSData Strobe (Input). This is the input for the active high data strobe on themicroprocessor interface. This input operates with CS to enable the internal read and write generation.202317R/W Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. 212418CSChip Select (Input). Active low input enabling a microprocessor read or write ofcontrol register or internal memories.22-2925-2729-3319-2123-27D7-D0Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to datain the internal control register, connect memory high, connect memory low and datamemory.303428V SSGround Rail.31-3835-3941-4329-3335-37STo7-STo0ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. Thesestreams are composed of 32 channels at data rates of 2.048 Mbit/s.394438ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serialoutputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control.40139CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations.6, 18,28, 4012,2234,44NCNo Connection.https:///MT8985Data SheetFunctional DescriptionWith the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. Existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels.The MT8985 device provides both functions and allows existing systems based on the MT8980D to be easily upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The MT8985 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis.By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces through the ST-BUS interface. Different digital backplanes can be accepted by the MT8985 device without user's intervention. The MT8985 device provides an internal circuit that automatically identifies the polarity and format of frame synchronization input signals compatible to ST-BUS and GCI interfaces.Device OperationA functional block diagram of the MT8985 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 µs wide frames each containing 32 8-bit channels. Eight input (STi0-7) and eight output (STo0-7) serial streams are provided in the MT8985 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications.https:///Data MemoryThe received serial data is converted to parallel format by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memory. The sequential addressing of the Data Memory is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams.Depending on the type of information to be switched, the MT8985 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, the variable delay mode can be selected ensuring minimum throughput delay between input and output data. In multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of the information through the switch.Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input (connection mode) or it can be originated from the microprocessor (message mode). If a channel is configured in connection mode, the source of the output data is the Data Memory. If a channel is configured in message mode, the source of the output data is the Connect Memory Low. Data destined for a particular channel on the serial output stream is read from the Data or Connect Memory Low during the previous channel time slot. This allows enough time for memory access and internal parallel to serial conversion.Connection and Message ModesIn connection mode, the addresses of input source for all output channels are stored in the Connect memory Low. The Connect Memory Low locations are mapped to each location corresponding to an output 64 kb/s channel. The contents of the Data memory at the selected address are then transferred to the parallel to serial converters. By having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch.MT8985Data SheetIn message mode the CPU writes data to the Connect Memory Low locations which correspond to the output link and channel number. The contents of the Connect Memory Low are transferred to the parallel to serial converter one channel before it is to be output. The Connect Memory Low data is transmitted each frame to the output until it is changed by the CPU.The per-channel functions available in the MT8985 are controlled by the Connect Memory High bits, which determine whether individual output channels are selected into specific conditions such as: message or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. In addition, the Connect Memory High provides one bit to allow the user to control the state of the CSTo output pin.If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual per-channel programming on the Connect Memory High bits.The Connect Memory data is received via the Microprocessor Interface at D0-D7 lines. The addressing of the MT8985 internal registers, Data and Connect memories is performed through address input pins and some bits of the device's Control register. The higher order address bits come from the Control register, which may be written or read through the microprocessor interface. The lower order address bits come directly from the external address line inputs. For details on the device addressing, see Software Control and Control register description.Serial Interface TimingThe MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be implemented. The MT8985 frame synchronization pulse can be formatted according to ST-BUS or GCI interface specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT8985 device https:///automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the 4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries.Delay through the MT8985The transfer of information from the input serial streams to the output serial streams results in a delay through the MT8985 device. The delay through the MT8985 device varies according to the mode selected in the V/C bit of the connect memory high.Variable Delay ModeThe delay in this mode is dependent only on the combination of source and destination channels and it is not dependent on the input and output streams. The minimum delay achievable in the MT8985 device is 3 time slots. In the MT8985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the information is input.The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later.Any switching configuration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode:MT8985Data SheetConstant Delay ModeIn this mode frame integrity is maintained in all switching configurations by making use of a multiple Data-Memory buffer technique where input channels written in any of the buffers during frame N will be read out during frame N+2. In the MT8985, the minimum throughput delay achievable in Constant Delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay.To summarize, any input time slot from input frame N will be always switched to the destination time slot on output frame N+2. In Constant Delay mode, the device throughput delay is calculated according to the following formula:DELAY = [32 + (32 - IN) + (OUT - 1)]; (expressed in number of time slots)Where:IN is the number of the input time slot (from 1 to 32).OUT is the number of the output time slot (from 1 to 32).Microprocessor PortThe MT8985 microprocessor port has pin compatibility with Zarlink MT8980 Digital Switch device providing a non-multiplexed bus architecture. The parallel port consists of an 8 bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control registers, Connection Memory High, Connection Memory Low and the Data Memory. All locations are read/written except for the data memory which can be read only.Accesses from the microport to the connection memory and the data memory are multiplexed with accesses from the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA). In the MT8985 device,the DTA output provides a maximum acknowledgement delay of 800 ns for read/write operations in the Connection Memory. However, for operations in the Data Memory (Message Mode), the maximum acknowledgement delay can be 1220 ns.Input ChannelOutput Channel Throughput Delay n m=n, n+1 or n+2m-n + 32 timeslotsnm>n+2m-n time slotsn m<n 32-(n-m) time slotshttps:///MT8985Data SheetFigure 3 - Address Memory MapNote: "x" Don’t careSoftware ControlThe address lines on the microprocessor interface give access to the MT8985 internal registers and memories. If the A5,A1,A0 address line inputs are LOW, then the MT8985 Internal Control Register is addressed (see Figure 3).If A5 input line is HIGH, then the remaining address input lines are used to select Memory subsections of 32locations corresponding to the number of channels per input or output stream. As explained in the Control register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of the MT8985 Data and Connect memories.The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream Address bits (see Figure 4). The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output ST-BUS streams. Bit 7 (Split Memory) of the Control register allows split memory operation whereby reads are from the Data memory and writes are to the Connect Memory LOW.The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the contents of the Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless the ODE input pin is LOW. If ME bit is HIGH, then the MT8985 behaves as if bits 2 (Message Channel) and 0(Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value.If ME bit is LOW, then bit 2 and 0 of each Connect Memory HIGH location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated ST-BUS output channel is in Message mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output.If the ODE input pin is LOW, then all serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable)of the CMH location enables (if HIGH) or disables (if LOW) the output drivers for the corresponding individual ST-BUS output stream and channel.The contents of bit 1 (CSTo) of each Connection Memory High location (see Figure 5) is output on CSTo pin once every frame. The CSTo pin is a 2048 Mbit/s output which carries 256 bits. If CSTo bit is set HIGH, the corresponding bit on CSTo output is transmitted in HIGH. If CSTo bit is LOW, the corresponding bit on the CSTo output is transmitted in LOW. The contents of the 256 CSTo bits of the CMH are transmitted sequentially on to the CSTo output pin and are synchronous to the ST-BUS streams. To allow for delay in any external control circuitry the contents of the CSTo bit is output one channel before the corresponding channel on the ST-BUS streams. For example, the contents of CSTo bit in position 0 (ST0, CH0) of the CMH, is transmitted synchronously with ST-BUS channel 31, bit 7. The contents of CSTo bit in position 32 (ST1, CH0) of the CMH is transmitted during ST-BUS channel 31 bit 6. Bit V/C (Variable/Constant Delay) on the Connect Memory High locations allow per-channel selection between Variable and Constant throughput delay capabilities.A5A4A3A2A1A0LOCATION 011111111000•••••1000•••••1000•••••1000•••••1001•••••1Control Register Channel 0Channel 1•••••Channel 31https:///MT8985Data SheetFigure 4 - Control Register Bitsx = Don’t careInitialization of the MT8985On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT8985 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition.BIT NAME DESCRIPTION7SM Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to theConnection Memory Low, except when the Control Register is accessed again. The Memory Select bits need to be set to specify the memory for the operations. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.6MEMessage Enable. When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when in High Impedance. When 0, the Connection Memory bits for each channel determine what is output.4-3MS1-MS0Memory Select Bits. The memory select bits operate as follows:0-0 - Not to be used0-1 - Data Memory (read only from the CPU)1-0 - Connection Memory Low 1-1 - Connection Memory High2-0STA2-0Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations.SMMEXMS1MS0STA2STA1STA076543210https:///MT8985Data SheetFigure 5 - Connection Memory High Bitsx = Don’t careFigure 6 - Connection Memory Low BitsDuring the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMH b 0s.BIT NAME DESCRIPTION6V/C Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis.2MCMessage Channel. When 1, the contents of the corresponding location in Connection Memory Low are output on the corresponding channel and stream. When 0, the contents of the programmed location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream.1CSTo CSTo Bit. This bit drives a bit time on the CSTo output pin.OEOutput Enable. This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it.BIT NAME DESCRIPTION7-5SAB2-0*Source Stream Address bits. These three bits are used to select eight source streams for the connection. Bit 7 of each word is the most significant bit.4-0*CAB4-0*Source Channel Address bits 0-4. These five bits are used to select 32 different source channels for the connection (The ST-BUS stream where the channel is present is defined by bits SAB2-0). Bit 4 is the most significant bit.*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.XV/CXXXMCCSToOE76543210SAB2SAB1SAB0CAB4CAB3CAB2CAB1CAB07654321https:///MT8985Data Sheet ApplicationsTypical Exchange, PBX or MultiplexerFigure 7 shows a typical implementation of line cards being interconnected through a central routing matrix that can scale up in channel capacity to accommodate different number of ports depending on the application. In a configuration where the switched services utilize concatenated or grouped time slots to carry voice, data and video (channels of 128, 256 Kb/s, ISDN H0 and others), the central routing matrix has to guarantee constant throughput delay to maintain the sequence integrity between input and output channels. Figure 7 shows an example where the MT8985 device guarantees data integrity when data flows from the T1/E1 to the S/U interface links and vice-versa. Modern technologies available today such as Frame Relay network using dedicated fractional T1 are one of the key applications for the MT8985 device.Figure 7 - Typical Exchange, PBX or Multiplexer ConfigurationMT8985Data SheetLow Latency Isochronous NetworkIn today's local working group environment, there is an increasing demand for solutions on interconnection of desktop and telephone systems so that mixed voice, data and video services can be grouped together in a reliable https:///network allowing the deployment of multimedia services. Existing multimedia applications require a network with predictable data transfer delays that can be implemented at a reasonable cost. The Low Latency Isochronous Network is one of the alternatives that system designers have chosen to accommodate this requirement (see Figure 8a). This network can be implemented using existing TDM transmission media devices such as ISDN Basic (S or U) and Primary rates trunks (T1 and CEPT) to transport mixed voice and data signals in grouped time slots; for example, 2B channels in case of ISDN S or U interfaces or up to 32 channels in case of a CEPT link.Figure 8b shows a more detailed configuration whereby several PCs are connected to form an Isochronous network. Several services can be interconnected within a single PC chassis through the standardized Multi Vendor Integration Protocol (MVIP). Such an interface allows the distribution and interconnection of services like voice mail, integrated voice response, voice recognition, LAN gateways, key systems, fax servers, video cards, etc.The information being exchanged between cards through the MVIP interface on every computer as well as between computers through T1 or CEPT links is, in general, of mixed type where 64Kb/s and N*64Kb/s channels are grouped together. When such a mixed type of data is transferred between cards within one chassis or from one computer to another, the sequence integrity of the concatenated channels has to be maintained. The MT8985 device suits this application and can be used to form a complete non-blocking switch matrix of 512 channels (see Figure 9). This allows 8 pairs of ST-BUS streams to be dedicated to the MVIP side whereas the remaining 8 pairs are used for local ancillary functions in typical dual T1/E1 interface applications (Figure 10).Another application of the MT8985 in an MVIP environment is to build an ISDN S-interface card (Figure 11). In this card, 7 pairs of ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface.MT8985Data Sheet To Video, Data,MT8985Data SheetFigure 9 - 512-Channel Switch Array8 Input Streams From MVIP8 Input On-Board ST-BUS Streams8 Output Streams to MVIP8 Output On-Board ST-BUS StreamsMVIP DirectionMVIP EnableMT8985 #1CSToMT8985 #2CSToMT8985#3MT8985#4https:///MT8985Data SheetFigure 10 - Dual T1/E1 Card Functional Block DiagramFDL HDLC MT8952B T1/E1MH89760Bor MH89790B HDLC MT8952BANALOG D-PHONE MT8992/93SWITCH MT8985SWITCH MT8985SWITCH MT8985SWITCH MT8985DPLL MT8941PC INTERFACEMVIP HEADERMVIP STo0-7MVIP STi0-7FDL HDLC MT8952BT1/E1MH89760Bor MH89790B HDLC MT8952B512 Channel Switch Matrixhttps:///MT8985Data SheetFigure 11 - S-Access Card Functional Block DiagramMVIP HEADERSWITCH MATRIX SINTERFACEHDLCDIGITAL PHONEDPLL DTMF RECEIVER PC INTERFACEHDLCSTi7-1STo7-1STi0STo0MT8930BMT8941MT8992/93MT8870MVIP STi1-7MVIP STo1-7MT8985https:///。

AT89S51概述1 一般概述该AT89S51是一个低功耗，高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。

该设备是采用Atmel的高密度非易失性存储器技术和符合工业标准的80C51指令集和引脚。

芯片上的Flash程序存储器可重新编程的系统或常规非易失性内存编程。

通过结合通用8位中央处理器的系统内可编程闪存的单芯片，AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。

在AT89S51提供以下标准功能：4K字节的Flash闪存，128字节的RAM ，32个I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器，5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。

此外，AT89S51设计的静态逻辑操作到零频率和支持两种软件可选节电模式。

空闲模式停止的CPU ，同时允许的RAM ，定时器/计数器，串行接口和中断系统继续运作。

在掉电模式保存RAM内容，可停止振荡器，停用所有其他芯片的功能，直到下一个外部中断或硬件复位。

2 端口端口0是一个8位漏极开路双向I / O端口。

作为一个输出端口，每个引脚可汇8的TTL 输入。

当1写入端口0引脚，该引脚可作为高阻抗输入。

端口0也可以配置为复低阶地址/数据总线，在访问外部程序和数据存储器。

在这种模式下，P0了内部无上拉。

端口还收到0字节的代码在Flash编程和产出代码波特率的核查。

外部上拉需要在使用。

端口1是一个8位双向I / O端口内部上拉。

端口1输出缓冲器可以驱动四个TTL。

当1写入端口1引脚，他们的退出高足态上拉，可作为输入。

作为输入，端口1引脚的外部被拉低将电源电流（IIL ）由于内部上拉。

端口1还收到低字节为了解决在Flash编程和核查。

端口2是一个8位双向I / O端口内部上拉。

端口2输出缓冲器可以驱动四的TTL输入。

当1写入端口2，他们的退出高阻态上拉，可作为输入。

1Zarlink Semiconductor Inc.Features•Central office quality DTMF transmitter/receiver •Low power consumption •High speed Intel micro interface •Adjustable guard time •Automatic tone burst mode•Call progress tone detection to -30dBmApplications•Credit card systems •Paging systems•Repeater systems/mobile radio •Interconnect dialers •Personal computersDescriptionThe MT8888C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones.The MT8888C utilizes an Intel micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic.September 2005Ordering InformationMT8888CE 20 Pin PDIP Tubes MT8888CS 20 Pin SOIC Tubes MT8888CN 24 Pin SSOP Tubes MT8888CP 28 Pin PLCC Tubes MT8888CE120 Pin PDIP*Tubes MT8888CS120 Pin SOIC*Tubes MT8888CN124 Pin SSOP*Tubes MT8888CP128 Pin PLCC*TubesMT8888CPR 28 Pin PLCC Tape & Reel MT8888CSR 20 Pin SOIC Tape & Reel MT8888CSR120 Pin SOIC*Tape & Reel MT8888CPR128 Pin PLCC*Tape & Reel*Pb Free Matte Tin-40°C to +85°CMT8888CIntegrated DTMF Transceiverwith Intel Micro InterfaceData SheetFigure 1 - Functional Block DiagramTONEIN+IN-GS OSC1OSC2V DD V RefV SSESt St/GTD0D1D2D3IRQ/CPRDCS WR RS0∑D/A ConvertersRow and Column CountersTransmit Data RegisterData Bus BufferTone Burst Gating Cct.+-Oscillator Circuit Bias Circuit Control LogicDigital Algorithm and Code ConverterControl LogicSteering LogicStatus Register Control RegisterA Control RegisterBReceive Data RegisterInterrupt LogicI/O ControlLow Group Filter High Group Filter Dial Tone Filterhttps://MT8888CData SheetFigure 2 - Pin ConnectionsPin DescriptionPin #NameDescription202428111 IN+Non-inverting op-amp input.222IN-Inverting op-amp input.334GS Gain Select . Gives access to output of front end differential amplifier forconnection of feedback resistor.446V Ref Reference Voltage output (V DD /2).557V SSGround (0V ).668OSC1DTMF clock/oscillator input. Connect a 4.7M Ω resistor to VSS if crystal oscillator isused.779OSC2Oscillator output. A 3.579545MHz crystal connected between OSC1 and OSC2completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.81012TONE Output from internal DTMF transmitter.91113WR Write microprocessor input. TTL compatible.101214CS Chip Select input. Active Low. This signal must be qualified externally by address latch enable (ALE) signal, see Figure 14.111315RS0Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.121417RDRead microprocessor input. TTL compatible.131518IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, thisoutput goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8.14-1718-2119-22D0-D3Microprocessor Data Bus . High impedance when CS = 1 or RD = 1.TTL compatible.1234567891011122019181716151413IN+IN-GS VRef VSS OSC1OSC2TONE WR CS VDD St/GT ESt D3D2D1D0IRQ/CP RD RS0NC 123456789101112131415162423222120191817IN+IN-GS VRef VSS OSC1OSC2NC TONE WR CS VDD St/GT ESt D3D2D1D0NC NC IRQ/CP RD RS024 PIN SSOP20 PIN PLASTIC DIP/SOIC 28 PIN PLCC456789101125242322212019•G S NC NC NC D3D2D1NC VRef VSS OSC1OSC2NC NCR D 32128272612131415161718N C I N -I N +V D D S t /G T E S TT O N E W R C S R S O N C I R Q /C PD0https://MT8888CData Sheet1.0 Functional DescriptionThe MT8888C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.The Intel micro interface allows microcontrollers, such as the 8080, 80C31/51 and 8085, to access the MT8888C internal registers.2.0 Input ConfigurationThe input arrangement of the MT8888C provides a differential-input operational amplifier as well as a bias source (V Ref ), which is used to bias the inputs at V DD /2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration.3.0 Receiver SectionSeparation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). These filters incorporate notches at 350Hz and 440Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.182226EStEarly Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.192327St/GTSteering Input/Guard Time output (bidirectional). A voltage greater than V TSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than V TSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.202428V DD Positive power supply (5V typical).8, 9,16,173,5,10,11,16,23,25NCNo Connection.Pin Description (continued)Pin #Name Description202428https://MT8888CData SheetFigure 3 - Single-Ended Input ConfigurationFigure 4 - Differential Input ConfigurationCR INR FIN+IN-GSV RefVOLTAGE GAIN (A V ) = R F / R INMT8888CC1C2R1R2R3R4R5IN+IN-GSV RefMT8888CDIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10 nFR1 = R4 = R5 = 100 k ΩR2 = 60k Ω, R3 = 37.5 k ΩR3 = (R2R5)/(R2 + R5)VOLTAGE GAIN (A V diff) - R5/R1INPUT IMPEDANCE(Z IN diff) = 2R12 + (1/ωC)2https://MT8888CData SheetNote:0= LOGIC LOW, 1= LOGIC HIGHFollowing the filter section is a decoder employing digital counting techniques to determine the frequencies of theincoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.4.0 Steering CircuitBefore registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes v c (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (t GTP ), v c reaches the threshold (V TSt ) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is activated and drives v c to V DD . GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active.The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, theF LOW F HIGH DIGIT D 3D 2D 1D 06971209100016971336200106971477300117701209401007701336501017701477601108521209701118521336810008521477910019411336010109411209*10119411477#11006971633A 11017701633B 11108521633C11119411633D 000Table 1 - Functional Encode/Decode Tablehttps://MT8888CData Sheetreceiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.Figure 5 - Basic Steering Circuit5.0 Guard Time AdjustmentThe simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7):t REC≥ t DPmax +t GTPmax- t DAmint REC≤ t DPmin+t GTPmin- tDAmaxt ID ≥ t DAmax +t GTAmax - t DPmin t DO ≤ t DAmin +t GTAmin - t DPmaxV DDV DD St/GT EStC1VcR1MT8888Ct GTA = (R1C1) In (V DD / V TSt )t GTP = (R1C1) In [V DD / (V DD -V TSt )]https://MT8888CData SheetFigure 6 - Guard Time AdjustmentThe value of t DP is a device parameter (see AC Electrical Characteristics) and t REC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (t GTP )and tone absent (t GTA ) guard times. This may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.Increasing t REC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9.6.0 Call Progress FilterA call progress mode, using the MT8888C, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common,however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and consequently the IRQ/CP pin will remain low.V DDSt/GTEStV DDSt/GTEStC1R1R2C1R1R2t GTA = (R1C1) In (V DD /V TSt )t GTP = (R P C1) In [V DD / (V DD -V TSt )]R P = (R1R2) / (R1 + R2)t GTA = (R p C1) In (V DD /V TSt )t GTP = (R1C1) In [V DD / (V DD -V TSt )]R P = (R1R2) / (R1 + R2)a)decreasing tGTP; (tGTP < tGTA)b)decreasing tGTA; (tGTP > tGTA)https://MT8888CData SheetFigure 7 - Receiver Timing DiagramFigure 8 - Call Progress ResponseV inEStSt/GTRX 0-RX 3b3b2Read Status Register IRQ/CPEVENTSABCDEFt RECt RECt IDt DOTONE #nTONE #n + 1TONE #n + 1t DPt DAt GTPt GTAt PStRXt PStb3DECODED TONE # (n-1)# n # (n + 1)VTSthttps://MT8888CData SheetFigure 9 - Description of Timing Events7.0 DTMF GeneratorThe DTMF transmitter employed in the MT8888C is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (f LOW and f HIGH ) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 94Hz. The high group frequencies are 1209, 1336, 1477 and 1633Hz. Typically, the high group to low group amplitude ratio (twist) is 2dB to compensate for high group attenuation on long loops.The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.EXPLANATION OF EVENTS A)TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.B)TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.C)END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR.D)TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E)ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.F)END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR.EXPLANATION OF SYMBOLS V in DTMF COMPOSITE INPUT SIGNAL.ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.RX 0-RX 34-BIT DECODED DATA IN RECEIVE DATA REGISTERb3DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL.b2INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ.IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS CLEARED AFTER THE STATUS REGISTER IS READ.t REC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.t REC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.t ID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.t DO MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.t DP TIME TO DETECT VALID FREQUENCIES PRESENT.t DA TIME TO DETECT VALID FREQUENCIES ABSENT.t GTP GUARD TIME, TONE PRESENT.t GTAGUARD TIME, TONE ABSENT.https://MT8888CData SheetThe lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8kHz. It can be seen from Figure 8 that the distortion products are very low in amplitude.Figure 10 - Spectrum Plot8.0 Burst ModeIn certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51ms ±1ms,which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode)is selected, the burst/pause duration is doubled to 102ms ±2ms. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter.Scaling Information10 dB/DivStart Frequency = 0 Hz Stop Frequency = 3400 HzMarker Frequency = 697 Hz and 1209 Hzhttps://MT8888CData Sheet9.0 Single Tone GenerationA single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control RegisterB description for details.10.0 Distortion CalculationsThe MT8888C is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage.Figure 11 - Equation 1. THD (%) For a Single ToneThe Fourier components of the tone output correspond to V 2f .... V nf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2. V L and V H correspond to the low group amplitude and high group amplitude, respectively and V 2IMD is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10.Figure 12 - Equation 2. THD (%) For a Dual ToneACTIVE INPUT OUTPUT FREQUENCY (Hz) %ERROR SPECIFIEDACTUAL L1697699.1+0.30L2770766.2-0.49L3852847.4-0.54L4941948.0+0.74H112091215.9+0.57H213361331.7-0.32H314771471.9-0.35H416331645.0+0.73Table 2 - Actual Frequencies Versus Standard RequirementsTHD (%) = 100V fundamentalV 22f + V 23f + V 24f + .... V 2nfV 2L + V 2HV 22L + V 23L + .... V 2nL + V 22H +V 23H + .. V 2nH + V 2IMDTHD (%) = 100https://MT8888CData Sheet11.0 DTMF Clock CircuitThe internal clock circuit is completed with the addition of a standard television color burst crystal. The crystal specification is as follows:Frequency:3.579545 MHz Frequency Tolerance:±0.1% Resonance Mode:Parallel Load Capacitance:18pFMaximum Series Resistance:150 ohms Maximum Drive Level:2mWe.g.CTS Knights MP036S Toyocom TQC-203-A-9SA number of MT8888C devices can be connected as shown in Figure 13 such that only one crystal is required.Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected.Figure 13 - Common Crystal Connection12.0 Microprocessor InterfaceThe MT8888C incorporates an Intel microprocessor interface which is compatible with fast versions (16 MHz) of the 80C51. No wait cycles need to be inserted.Figure 19 and Figure 20 are the timing diagrams for the Intel 8031, 8051 and 8085 (5 MHz) microcontrollers. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS is generated.Figure 14 summarizes the connection of these Intel processors to the MT8888C transceiver.The microprocessor interface provides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is accomplished with two control registers (see Table 6 and Table 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the current transceiver state (see Table 8).A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers.The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a squarewave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 15).MT8888C OSC1OSC2MT8888C OSC1OSC2MT8888C OSC1OSC23.579545 MHzhttps://MT8888C Data SheetRS0WR RD FUNCTION001Write to Transmit Data Register010Read from Receive Data Register101Write to Control Register110Read from Status RegisterTable 3 - Internal Register Functionsb3b2b1b0RSEL IRQ CP/DTMF TOUTTable 4 - CRA Bit Positionsb3b2b1b0C/R S/D TEST BURSTENABLETable 5 - CRB Bit Positionshttps://BIT NAME DESCRIPTIONb0TOUT Tone Output Control. A logic high enables the tone output; a logic low turns the tone output off. This bit controls all transmit tone functions.b1CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;a logic low enables DTMF mode. In DTMF mode the device is capable of receiving andtransmitting DTMF signals. In CP mode a rectangular wave representation of the receivedtone signal will be present on the IRQ/CP output pin if IRQ has been enabled (controlregister A, b2=1). In order to be detected, CP signals must be within the bandwidthspecified in the AC Electrical Characteristics for Call Progress.Note: DTMF signals cannot be detected when CP mode is selected.b2IRQ Interrupt Enable. A logic high enables the interrupt function; a logic low deactivates the interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has beenreceived for a valid guard time duration, or 2) the transmitter is ready for more data (burstmode only).b3RSEL Register Select. A logic high selects control register B for the next write cycle to the control register address. After writing to control register B, the following control register write cyclewill be directed to control register A.Table 6 - Control Register A DescriptionMT8888C Data SheetBIT NAME DESCRIPTIONb0BURST Burst Mode Select. A logic high deactivates burst mode; a logic low enables burst mode.When activated, the digital code representing a DTMF signal (see Table 1) can be writtento the transmit register, which will result in a transmit DTMF tone burst and pause of equaldurations (typically 51 msec). Following the pause, the status register will be updated (b1 -Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has beenenabled.When CP mode (control register A, b1) is enabled the normal tone burst and pausedurations are extended from a typical duration of 51 msec to 102 msec.When BURST is high (deactivated) the transmit tone burst duration is determined by theTOUT bit (control register A, b0).b1TEST Test Mode Control. A logic high enables the test mode; a logic low deactivates the test mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), thesignal present on the IRQ/CP pin will be analogous to the state of the DELAYEDSTEERING bit of the status register (see Figure 7, signal b3).b2S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the dual tone (DTMF) output. The single tone generation function requires furtherselection of either the row or column tones (low or high group) through the C/R bit (controlregister B, b3).b3C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selectsa row tone output. This function is used in conjunction with the S/D bit (control register B,b2).Table 7 - Control Register B DescriptionBIT NAME STATUS FLAG SET STATUS FLAG CLEAREDb0IRQ Interrupt has occurred. Bit one(b1) or bit two (b2) is set.Interrupt is inactive. Cleared after Status Register is read.b1TRANSMIT DATAREGISTER EMPTY(BURST MODE ONLY) Pause duration has terminatedand transmitter is ready for newdata.Cleared after Status Register isread or when in non-burst mode.b2RECEIVE DATA REGISTER FULL Valid data is in the Receive DataRegister.Cleared after Status Register isread.b3DELAYED STEERING Set upon the valid detection ofthe absence of a DTMF signal.Cleared upon the detection of a valid DTMF signal.Table 8 - Status Register Description https://。

uc3875中文资料篇一：关于uc3875UC3875相移谐振控制器（PhaeShiftReonantController）特点：FEATURESZeroto100%DutyCycleControl输出PWM脉冲0到100%占空比dutycycle(占空比)ModeTopologie（拓扑）电压或电流型拓扑相兼容PracticalOperationatSwitching（开关）Frequencie（频率）to1MHz开关工作频率1MHZFour2ATotemPoleOutput4个2A图腾柱输出TotemPole（图腾柱）（图腾柱输出（TotemPole的音译）结构介绍图腾柱就是上下各一个三极管，上管为NPN，c极(集电极)接正电源，下管为PNP，c极(集电极)接地。

两个b极(基极)接一起，接输入，上管和下管的e极(发射极)接到一起，接输出，像一个“图腾柱”。

用同一信号驱动两个b极。

驱动信号为高时，NPN导通；信号为低时，PNP导通。

利用两个晶体管构成推挽输出。

用来匹配电压，或者提高IO口的驱动能力。

上下两个输出管，从直流角度看是串联，两管联接处为输出端。

上管导通下管截止输出高电平，下管导通上管截止输出低电平，如果电路逻辑可以上下两管均截止则输出为高阻态。

在开关电源中，类似的电路常称为半桥。

）10MHzErrorAmplifier（放大器）10MHZ误差放大器（误差放大器是指用来放大“误差”信号的放大器，与其他放大器的区别主要在被处理信号类型不同。

在控制环路中，误差放大器将误差信号（输出与参考之差）放大，以提高控制系统的灵敏度，提高调节精度（降低调节误差）。

）UndervoltageLockout欠压锁定（UVLO）（电压不足时，为不工作的状态）LowStartupCurrent–150A低的软上升电流OutputActiveLowDuringUVLOSoft-StartControl软启动控制TrimmedReference二十个管脚1.VREF基准电压可输出精确的5V基准电压,其电流可以达到60mA。

附件1：外文资料翻译译文AT89C52中文资料AT89C52是美国Atmel公司生产的低电压、高性能CMOS 8位单片机，片内含8KB的可反复檫写的程序存储器和12B的随机存取数据存储器（RAM），器件采用Atmel公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内配置通用8位中央处理器（CPU）和Flash存储单元，功能强大的AT89C52单片机可灵活应用于各种控制领域。

AT89C52单片机属于AT89C51单片机的增强型，与Intel公司的80C52在引脚排列、硬件组成、工作特点和指令系统等方面兼容。

其主要工作特性是：•与MCS-51产品指令和引脚完全兼容•8k字节可重擦写Flash闪速存储器•1000次擦写周期•具有3个可编程定时器•全静态操作：0Hz-24MHz•256×8字节内部RAM•32个可编程I/O口线•3个16位定时/计数器•8个中断源•可编程串行uart通道•低功耗空闲和掉电模式单片机正常工作时，都需要有一个时钟电路和一个复位电路。

本设计中选择了内部时钟方式和按键电平复位电路，来构成单片机的最小电路。

功能特性描述：AT89C52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。

片上Flash允许程序存储器在系统可编程，亦适于常规编程器。

AT89C52方框图P0 口：P0 口是一组8 位漏极开路型双向I/O 口，也即地址/数据总线复用口。

作为输出口用时，每位能吸收电流的方式驱动8 个TTL逻辑门电路，对端口P0 写“1”时，可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8 位）和数据总线复用，在访问期间激活内部上拉电阻。

在Flash 编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。

ATT7053C 用户手册钜泉光电科技（上海）股份有限公司Tel: ************Fax: ************Email: *********************Web: 版本更新说明版本号修改时间修改内容V1.0 2017-7-18 创建初稿；V1.1 2018-04-13 1.修改校表参数寄存器40H bit8，Qselect改为Qselect0.2.修改手册为ATT7053C，和芯片的丝印一致；3.增加包装信息；V1.2 2018-09-06 1.修改包装信息，与出厂信息一致。

目录1.芯片概况 (5)1.1.芯片简介 (5)1.2.芯片特性 (5)1.3.整体框图 (6)1.4.引脚定义 (6)2.电源管理 (8)2.1.电源监测系统 (8)2.2.系统复位方式 (8)3.系统功能 (9)3.1.波形采样功能 (9)3.2.有效值测量 (9)3.3.有功功率计算 (9)3.4.无功功率计算 (10)3.5.视在功率计算 (10)3.6.电能/频率转换 (10)3.7.移采样点方式相位校正 (10)3.8.自定义电量模块 (10)3.9.直流测量 (11)3.10.起动/潜动 (11)3.11.计量可靠性机制 (11)3.12.Rx Pin 暂停电能累加功能 (11)3.13.中断源 (11)3.14.锰铜掉线检测功能 (11)3.15.脉冲加倍功能 (12)3.16.自动防窃电功能 (12)3.17.电压SAG/PEAK功能 (13)3.18.电压过零丢失 (13)3.19.广播电量备份及相序检测 (13)3.20.ADC波形缓存功能 (14)3.21.校表参数校验 (14)4.通信接口 (15)4.1.SPI接口 (15)4.2.UART接口 (19)4.3.特殊命令 (26)5.寄存器 (28)5.1.计量参数寄存器 (28)5.2.校表参数寄存器 (38)6.电气规格 (62)6.1.绝对最大额定值 (62)6.2.电气特性 (62)7.校表过程 (64)8.芯片信息 (67)8.1.封装信息 (67)8.2.芯片包装信息 (68)9.典型应用 (69)1.芯片概况1.1.芯片简介ATT7053C是一颗带SPI和UART通讯接口的高精度单相多功能计量芯片。

CMOS ICFunctionPowerPC405- Loaded with 16 Kbytes I-Cache and 8 Kbytes D-Cache- Operates at 192 MHz at maximum- 5-tiered pipeline- Incorporates PIT (Programmable Interval Timer), FIT (Fixed Interval Timer) and Watch dog timer- MAC (16 × 16 + 32): 2 cycle, 1 cycle throughput- JTAG SupportSDRAM Memory Controller- 11 × 8 to 13 × 11 addressing for SDRAM (2- and 4-bank)- 32-bit memory interface support- Programmable address compare for each bank of memory- 4 MB to 256 MB per bank- 512 MB of address space- Up to 96 MHz Memory- Programmable address mapping and timing- Auto refresh- Page Mode accesses with up to 4 open pages- Sync DRAM configuration via mode set command- Power Management (self-refresh)External Peripheral Bus Controller (EBC)- Up to eight ROM, EPROM, SRAM, flash, and slave peripheral I/O banks supported- Up to 48 MHz operation- Burst and non-burst devices- 8-, 16-, 32-bit byte-addressable data bus width support- Latch data on ready, synchronous or asynchronous- Programmable 2K clock time-out counter with disable for ready- Programmable access timing per device- Programmable address mappingDMA Controller- Memory-to-memory transfers- Buffered peripheral to memory transfers- Buffered memory to peripheral transfers- Four channels- IrDA (two-channels: send & receive)- USB Device- IEEE1284- Scatter/gather capability for programming multiple DMA operations- Address increment or decrement- Internal 32-byte data buffering capability- Support memory mapped peripheralsUART- Provides one 8-pin UART and one 4-pin UART interface- Register compatibility with NS16550 register set- Complete status reporting capability- Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode- Fully programmable serial-interface characteristicsGeneral Purpose IO (GPIO) Controller- Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses- All GPIOs are pin-shared with other functions- Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-stated if output bit is 1)Universal Interrupt Controller (UIC)- Supports 7 external and 25 internal interrupts- Edge triggered or level-sensitive (positive / negative)- Non-critical or critical interrupt to PPC405 processor core- Programmable critical interrupt priority ordering- Programmable critical interrupt vector for faster vector processingPower Management (CPM: Clock & Power Management)- Sleep control is applicable to each independent macroLCD Controller- Complies with Mono-STN, Color-STN and TFT- Deals with both Single-Scan and Dual-Scan- Applicable to resolution of 1/4 VGA-SVGA- Programmable LCD Timing GenerationTPC (Touch Panel Controller)- Read speed is changeable to 10 to 200 points/second- Offers up to 1024 × 1024 resolution with 10 bit AD Converter- Lessens chattering noise generated by pens and/or noise from LCD using standardization treatment- 2-point calibrationUSB (Universal Serial Bus)- Supports both Host and Device- Compliant to USB1.1 and OHCI1.2- Deals with both Full Speed (12 Mbps) and Low Speed (1.5 Mbps)- Supports Isochronous, Interrupt, Control and Bulk transfer- Applicable to both 2 ports (Host) and 1 port (Device)IrDA- 1 channel- Compliant to IrDA1.1- Transmission rate up to 4 Mbps (Max)- Supports dual DMA channel operationPCMCIA- Based on PCMCIA interface standard Ver 2.0- Equipped with card write protect function- 2 channelsIEEE1284- Supports compatibility, Nibble, Byte, ECP, and Negotiation Modes (No support for EPP and ECP with RLE) - Software configurable as either host or peripheral interface- Supports DMAHDLC (High level Data Link Control)- Full duplex, 2 channels- Flag transmission/detection- Insert/delete of 0- CRC generation/inspection (X16 + X12 + X5 + 1: CRC-CCITT)- Abort transmission/detection- Detection of address field (1 byte)- Auto-transmission of address field (1 byte)- FIFO (receiver and transmitter: 16 bytes)- overflow/underflow detection- Random number generation (M series)- Compliant to both master and slave modesIOM2 (ISDN Oriented Modular interface 2)- Applicable to terminal (Multiplexed 3 IOM channels)- Slave operationSCP (Serial Communication Port)- Full duplex- Synchronous transmission- Programmable clock rateRTC (Real Time Clock)- Low power operation- 12-hour and 24-hour modes- Summer time support- Supports memory area (114 bytes) capable of back-upGPT (General Purpose Timer)- 32 bits time base- Incorporates 5 compare timersPS2- Parity error and stop bit detection, reporting of ack_sending completionSCI- Handles transmission protocols T = "0" (asynchronous character) and T = "1" (asynchronous block) as described in ISO/IEC 7816-3- Implements cyclical and longitudinal redundancy checking (CRC and LRC), as well as parity checking in hardware - Can be configured with 32-byte or 16-byte FIFO for input or outputKey Scan (16 × 12)- Performs 16 by 12 software key scanKey Scan (6 × 4)-Performs 6 by 4 automatic key scan (hardware key scan)-Three key scan modes are supported-Single key depression detect mode-Single key depression/release detect mode-Status change detect modeJTAG- IEEE 1149.1 test access port- IBM RISC watch debugger supportLC77700B (IAPr TM: Internet Access Processor) Functional Block DiagramContinued from preceding page.Address Block0xEF60_1100 - 0xEF60_117C GPIO 40xEF60_1200 - 0xEF60_1258 USB Host0xEF60_1360 - 0xEF60_138F USB Device0xEF60_1400 - 0xEF60_1404 Key Scan (16 × 12)0xEF60_1500 - 0xEF60_1508 Key Scan (6 × 4)0xEF60_1600 - 0xEF60_16FF OPB ArbiterDCR Address MapAddress Block0x010 - 0x011 HS_PLB (SDRAM Controller)0x012 - 0x013 EBC0x014 - 0x01A PCMCIA0x028 - 0x02F PLB to OPB Bridge (BGO)0x040 - 0x04F Clock/Reset/Pin Strap/CPM0x080 - 0x08F PLB Arbiter0x0A8 - 0x0A9 OPB to PLB Bridge (BGI)0x0C0 - 0x0C8 UIC0x100 - 0x125 DMA Controller0x140 - 0x149 LCD ControllerNotes:DCR address map is accessed by software running on the PPC405 processor through the use of MTDCR and MFDCR commands.DCR address space is addressable with up to 10 bits (1024 or 1K unique address). Each address represents a single 32-bit (word) register, or 1 kilo word (KW) (which equals 4 KB).Package27 mm, 456-Ball E-PBGA PackageSupply VoltageBottom ViewPin Assignment (Top View)A B C D E F G H J K L MN P R T U V WY AA AB AC AD AEAF26 G G TS1E PRTD 5 PRTD 1 G RTCP S_N PRTB USY RTCV DD RXD0 G IOM2DD IOM2DCL PC_CE 01_N PC_CE 11_N G PC_BV D01_N PC_IO RD_N USB1D_N UXTAL1G SCCL K PNLO Y0 NC2 NC4G2625 TCLK G TS2O PRTD 7 TS4 PRTD 4 PRTD 0 PRTE RR_N PRTDBE N_N RXTA L0 TXD0DSR0_N IOM2DU PC_RE SET0PC_VS 01_N PC_P OE_N PHOS T_N HDLC0RTS_N UXTA L0TXD1PD31 PD30 PNLOX0NC5 G G2524 TDI PRTP E G TS2E TS1O PRTD 3 PRTA CK_N PRTSI _N PRTS LCT PRTA F RI0_N DCD0_N PC_CE 02_N PC_CE 12_N PC_R EG_N PC_CD 02_N PC_IO WR_N USB1D HDLC0CTS_N RXD1NC3 PD29 PNLO X1 GPNLX IN CTS1_N2423 MD0 TS3 TS5 G TCK PRTD 6 PRTD 2 PRTS TB_N PRTI_N RXTA L1 DTR0_N CTS0_N RTS0_N PC_WE _N PC_O E_N PC_CD 01_N RI1_N PC_BV D02_N IOM2FSC DTR1_N PD28 PNLO PD G PNLY IN ADC VDDNC12322 MD1 MD2 LCDD0 TS6 G OV DD OV DD OV DD G V DD V DD V DD G G V DD V DD V DD G OV DD OV DD OV DD GPNLP DIN ADC GND RTS1_N SCVE N 2221 G MD3 LCDD 1 CTS2_N OV DD OV DD PD27 SCRS T PCLK G 2120 MD5 MD4 LCDD 10 IRDA TX OV DD OV DD SCDE T ADCR EF DSR1_N PNLO Y12019 MD6 LCDD 11 LCDD 2 MD7 OV DD OV DD DCD1_N SCIO PD26PD231918 MD8 LCDD 12 LCDD13TMS G G PD25 PD22 PD24PD191817 MD9 MD10 LCDD 3 LCDL INE V DDV DD PD20 PD18 PD21PD161716 G LCDD 14 LCDD 15 LCDRS T_N V DDTB TB TB TB TB TB V DD PD15 PD14 PD17G1615 MD11 LCDD 16 LCDF RM LCDV DDEN V DD TB TB TB TB TB TB V DD PD13 PD12 PD11IREQ51514 IRDA RX LCDD 17 LCDD 4 TRST _N G TB TB TB TB TB TB G PCS7_N PD10IREQ 6 IREQ 21413 MD12 LCDD 18 LCDVEEEN TDO G TB TB TB TB TB TB GPCS6_N PC_VS 02_N IREQ 3 IREQ 11312 LCDD 20 LCDD 19 LCDSH IFT IRDAC TR_N V DD TB TB TB TB TB TB V DD PCS5_N PCRDYBSY1NPD9IREQ 0 1211 G MD14 TEST EN LCDE N V DD TB TB TB TB TB TB V DD PCS4_N PCRDYBSY0NPD8G 1110 MD15 MD16 LCDD 5 MD13 V DD V DD PD5 KOUT15_N KOUT14_N PD7109 MD17 LCDD 21 MD18 LCDD 22 G G PWBE 3_N USB0D_N KOUT13_NPD69 8 MD19 MD20 LCDD 6 LCD MUX OV DD OV DD PWBE 2_N PD4 PD3USB0D 8 7MD21 MD22 MD23 MD24 OV DDOV DD KOUT10_N KOUT11_N PD1PD27 6 G LCDD 7 MD25 LCDD 23OV DDOV DDPA26 PA27 PD0G 6 5 MD26 MD27 LCDD 8 SHALT_N G OV DD OV DD OV DD G V DD V DD V DDGGV DD V DD V DDGOV DD OV DD OV DDGPA24PC_WP0PA28PA295 4 MD28 MD29 LCDD 9G MBS0_N MBA1KIN2_N MCL KEN KIN4_N KOUT 1_N KIN6_N PA9KIN8_N KOUT 2_N KOUT 3_N KOUT 4_N PWAI T_N KOUT 6_N KOUT 7_N PBEN _N PSDA TA PA21 G PA25PCS2_NKOUT 12_N4 3 MD30 MD31 G MDQM 1_N KOUT0_N MBA0MBS1_N MA4 MCA S_N MA8 KIN5_NPA8MA11KIN10_N PA11KOUT 5_N PA16PWBE 1_N PWBE 0_N KOUT 8_N KOUT 9_N PA22 PA23 GPCS1_NPCS0_N 3 2 G G MDQM 0_N KIN1_N MDQM 2_N MDQM3_N MA0 MA3 MA5 KIN3_NMA9PA7KIN7_N KIN9_N PA10PA12PA15PA17PRW_N POEN _N SXTA L1 SRST _N SPVD D PCS3_NGIREQ 4 2 1 G MCL K KIN0_N MWE _N MRAS_N G MA1 MA2 MA6 MA7 G PA6MA12MA10KIN11_N G PA13PA14PA18PA19G PA20 SXTA L0 PSCLKGG 1 A B C D E F G H J K L MN P R T U V W Y AA AB AC AD AEAFPin ListsMultiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.Notes:1. Must pull down (recommended value is 1k Ω)2. If not used, must pull up (recommended value is 3k Ω at3.3V) 3. If not used, must pull down (recommended value is 1k Ω)4. Strapping input during reset; either pull-up or pull-down as required5. Pulled down with 11 k Ω resistance in I/O cells6. Pulled up with 14 k Ω resistance in I/O cells7. When loading and storing the following data, assigned as LSB -a. Full word data, assigned as LSB -b. Word data -c. Byte dataBall SignalType Notes Name Descriptions I/OSDRAM InterfaceA23 MD0 SDRAM data bus 0 I/O 3.3VLVTTLA22 MD1 SDRAM data bus 1 I/O 3.3VLVTTLB22 MD2 SDRAM data bus 2 I/O 3.3VLVTTLB21 MD3 SDRAM data bus 3 I/O 3.3VLVTTLB20 MD4 SDRAM data bus 4 I/O 3.3VLVTTLA20 MD5 SDRAM data bus 5 I/O 3.3VLVTTLA19 MD6 SDRAM data bus 6 I/O 3.3VLVTTLD19 MD7 SDRAM data bus 7 I/O 3.3VLVTTLA18 MD8 SDRAM data bus 8 I/O 3.3VLVTTLA17 MD9 SDRAM data bus 9 I/O 3.3VLVTTLB17 MD10 SDRAM data bus 10 I/O 3.3VLVTTLA15 MD11 SDRAM data bus 11 I/O 3.3VLVTTLA13 MD12 SDRAM data bus 12 I/O 3.3VLVTTLD10 MD13 SDRAM data bus 13 I/O 3.3VLVTTLB11 MD14 SDRAM data bus 14 I/O 3.3VLVTTLA10 MD15 SDRAM data bus 15 I/O 3.3VLVTTLB10 MD16 SDRAM data bus 16 I/O 3.3VLVTTLA9 MD17 SDRAM data bus 17 I/O 3.3VLVTTLC9 MD18 SDRAM data bus 18 I/O 3.3VLVTTLA8 MD19 SDRAM data bus 19 I/O 3.3VLVTTLB8 MD20 SDRAM data bus 20 I/O 3.3VLVTTLA7 MD21 SDRAM data bus 21 I/O 3.3VLVTTLB7 MD22 SDRAM data bus 22 I/O 3.3VLVTTLC7 MD23 SDRAM data bus 23 I/O 3.3VLVTTLD7 MD24 SDRAM data bus 24 I/O 3.3VLVTTLC6 MD25 SDRAM data bus 25 I/O 3.3VLVTTLA5 MD26 SDRAM data bus 26 I/O 3.3VLVTTLB5 MD27 SDRAM data bus 27 I/O 3.3VLVTTLA4 MD28 SDRAM data bus 28 I/O 3.3VLVTTLB4 MD29 SDRAM data bus 29 I/O 3.3VLVTTLA3 MD30 SDRAM data bus 30 I/O 3.3VLVTTLB3 MD31 SDRAM data bus 31 I/O 3.3VLVTTLN1 MA12 SDRAM address bus 12 (MSB) O 3.3VLVTTLN3 MA11 SDRAM address bus 11 O 3.3VLVTTLP1 MA10 SDRAM address bus 10 O 3.3VLVTTLL2 MA9 SDRAM address bus 9 O 3.3VLVTTLK3 MA8 SDRAM address bus 8 O 3.3VLVTTLK1 MA7 SDRAM address bus 7 O 3.3VLVTTLJ1 MA6 SDRAM address bus 6 O 3.3VLVTTLJ2 MA5 SDRAM address bus 5 O 3.3VLVTTLH3 MA4 SDRAM address bus 4 O 3.3VLVTTLH2 MA3 SDRAM address bus 3 O 3.3VLVTTLH1 MA2 SDRAM address bus 2 O 3.3VLVTTLG1 MA1 SDRAM address bus 1 O 3.3VLVTTLG2 MA0 SDRAM address bus 0 (LSB) O 3.3VLVTTLF3 MBA0 SDRAM bank address (Up to 4 banks) O 3.3VLVTTLF4 MBA1 SDRAM bank address (Up to 4 Banks) O 3.3VLVTTLE1 MRAS_N SDRAM row address strobe O 3.3VLVTTLJ3 MCAS_N SDRAM column address strobe O 3.3VLVTTLC2 MDQM0_N SDRAM DQM for byte lanes 0 O 3.3VLVTTLD3 MDQM1_N SDRAM DQM for byte lanes 1 O 3.3VLVTTLE2 MDQM2_N SDRAM DQM for byte lanes 2 O 3.3VLVTTLContinued on next page.Continued from preceding page.Ball SignalName Descriptions I/OType Notes F2 MDQM3_N SDRAM DQM for byte lanes 3 O 3.3VLVTTLE4 MBS0_N SDRAM chip select 0 O 3.3VLVTTLG3 MBS1_N SDRAM chip select 1 O 3.3VLVTTLD1 MWE_N SDRAM write enable O 3.3VLVTTLH4 MCLKEN SDRAM clock enable O 3.3VLVTTLB1 MCLK SDRAMclock O 3.3VLVTTLExternal Peripheral Interface [PCMCIA Interface] [GPIO]AE6 PD0 Peripheral data bus 0 I/O 3.3VLVTTL 4AE7 PD1 Peripheral data bus 1 I/O 3.3VLVTTL 4AF7 PD2 Peripheral data bus 2 I/O 3.3VLVTTL 4AE8 PD3 Peripheral data bus 3 I/O 3.3VLVTTL 4AD8 PD4 Peripheral data bus 4 I/O 3.3VLVTTL 4AC10 PD5 Peripheral data bus 5 I/O 3.3VLVTTL 4AF9 PD6 Peripheral data bus 6 I/O 3.3VLVTTL 4AF10 PD7 Peripheral data bus 7 I/O 3.3VLVTTL 4AE11 PD8 Peripheral data bus 8 I/O 3.3VLVTTL 4AE12 PD9 Peripheral data bus 9 I/O 3.3VLVTTLAD14 PD10 Peripheral data bus 10 I/O 3.3VLVTTLAE15 PD11 Peripheral data bus 11 I/O 3.3VLVTTLAD15 PD12 Peripheral data bus 12 I/O 3.3VLVTTLAC15 PD13 Peripheral data bus 13 I/O 3.3VLVTTLAD16 PD14 Peripheral data bus 14 I/O 3.3VLVTTLAC16 PD15 Peripheral data bus 15 I/O 3.3VLVTTL 4AF17 PD16 Peripheral data bus 16 I/O 3.3VLVTTL 4AE16 PD17 Peripheral data bus 17 I/O 3.3VLVTTL 4AD17 PD18 Peripheral data bus 18 I/O 3.3VLVTTL 4AF18 PD19 Peripheral data bus 19 I/O 3.3VLVTTL 4AC17 PD20 Peripheral data bus 20 I/O 3.3VLVTTL 4AE17 PD21 Peripheral data bus 21 I/O 3.3VLVTTL 4AD18 PD22 Peripheral data bus 22 I/O 3.3VLVTTLAF19 PD23 Peripheral data bus 23 I/O 3.3VLVTTLAE18 PD24 Peripheral data bus 24 I/O 3.3VLVTTLAC18 PD25 Peripheral data bus 25 I/O 3.3VLVTTLAE19 PD26 Peripheral data bus 26 I/O 3.3VLVTTLAC21 PD27 Peripheral data bus 27 I/O 3.3VLVTTLAA23 PD28 Peripheral data bus 28 I/O 3.3VLVTTLAB24 PD29 Peripheral data bus 29 I/O 3.3VLVTTLAB25 PD30 Peripheral data bus 30 I/O 3.3VLVTTLAA25 PD31 Peripheral data bus 31 I/O 3.3VLVTTLM1 PA6[GPIO1_B28] Peripheral address bus 6 (MSB)[GPIO 1 Bit 28]O[I/O]3.3V LVTTL 2 or 3M2 PA7[GPIO1_B29] Peripheral address bus 7[GPIO 1 Bit 29]O[I/O]3.3V LVTTL 2 or 3M3 PA8 Peripheral address bus 8 O 3.3VLVTTLM4 PA9 Peripheral address bus 9 O 3.3VLVTTLR2 PA10 Peripheral address bus 10 O 3.3VLVTTLR3 PA11 Peripheral address bus 11 O 3.3VLVTTLT2 PA12 Peripheral address bus 12 O 3.3VLVTTLU1 PA13 Peripheral address bus 13 O 3.3VLVTTLV1 PA14 Peripheral address bus 14 O 3.3VLVTTLU2 PA15 Peripheral address bus 15 O 3.3VLVTTLU3 PA16 Peripheral address bus 16 O 3.3VLVTTLV2 PA17 Peripheral address bus 17 O 3.3VLVTTLContinued on next page.W1 PA18 Peripheral address bus 18 O 3.3VLVTTLY1 PA19 Peripheral address bus 19 O 3.3VLVTTLAB1 PA20 Peripheral address bus 20 O 3.3VLVTTLAB4 PA21 Peripheral address bus 21 O 3.3VLVTTLAB3 PA22 Peripheral address bus 22 O 3.3VLVTTLAC3 PA23 Peripheral address bus 23 O 3.3VLVTTLAC5 PA24 Peripheral address bus 24 O 3.3VLVTTLAD4 PA25 Peripheral address bus 25 O 3.3VLVTTLAC6 PA26 Peripheral address bus 26 O 3.3VLVTTLAD6 PA27 Peripheral address bus 27 O 3.3VLVTTLAE5 PA28 Peripheral address bus 28 O 3.3VLVTTLAF5 PA29 Peripheral address bus 29 (LSB) O 3.3VLVTTL 7-a W3 PWBE0_N Peripheral write byte enable 0 O 3.3VLVTTLV3 PWBE1_N Peripheral write byte enable 1 O 3.3VLVTTLAC8 PWBE2_N[PA30] Peripheral write byte enable 2[Peripheral address bus 30 (LSB)]O[O]3.3V LVTTL 7-bAC9 PWBE3_N[PA31] Peripheral write byte enable 3[Peripheral address bus 31 (LSB)]O[O]3.3V LVTTL 7-cAF3 PCS0_N[PCS7_N] Peripheral chip select 0[Peripheral chip select 7]O[O]3.3V LVTTLAE3 PCS1_N Peripheral chip select 1 O 3.3VLVTTL AE4 PCS2_N Peripheral chip select 2 O 3.3VLVTTL AD2 PCS3_N Peripheral chip select 3 O 3.3VLVTTL AC11 PCS4_N Peripheral chip select 4 O 3.3VLVTTL AC12 PCS5_N Peripheral chip select 5 O 3.3VLVTTLAC13 PCS6_N[PC_ENIF_N] Peripheral chip select 6[Output buffer enable]O[O]3.3V LVTTLAC14 PCS7_N[PCS0_N] Peripheral chip select 7[Peripheral chip select 0]O[O]3.3V LVTTLY2 POEN_N Peripheral read enable O 3.3VLVTTLW2 PRW_N Peripheral read write control O 3.3VLVTTLU4 PWAIT_N Asynchronous wait for access while low I 3.3VLVTTL 6 Y4 PBEN_N Enable control of external buffer O 3.3VLVTTLAE21 PCLK Clock for peripheral device O 3.3VLVTTLLCD Interface [PCMCIA Interface] [GPIO]D16 LCDRST_N[GPIO0_B24] LCD reset[GPIO 0 bit 24]I[I/O]3.3V LVTTL 2 or 3D11 LCDEN[GPIO0_B25] LCD panel enable, display on[GPIO 0 bit 25]O[I/O]3.3V LVTTL 2 or 3C13 LCDVEEEN[GPIO0_B26] LCD bias power enable[GPIO 0 bit 26]O[I/O]3.3V LVTTL 2 or 3D15 LCDVDDEN[GPIO0_B27] LCD logic power enable[GPIO 0 bit 27]O[I/O]3.3V LVTTL 2 or 3D8 LCDMUX[GPIO0_B28] LCD multi purpose pin[GPIO 0 bit 28]O[I/O]3.3V LVTTL 2 or 3C12 LCDSHIFT[GPIO0_B29] LCD shift clock[GPIO 0 bit 29]O[I/O]3.3V LVTTL 2 or 3D17 LCDLINE[GPIO0_B30] LCD line pulse[GPIO 0 bit 30]O[I/O]3.3V LVTTL 2 or 3C15 LCDFRM[GPIO0_B31] LCD frame pulse[GPIO 0 bit 31]O[I/O]3.3V LVTTL 2 or 3C22 LCDD0[GPIO0_B0] LCD display data 0[GPIO 0 bit 0]O[I/O]3.3V LVTTL 2 or 3C21 LCDD1[GPIO0_B1] LCD display data 1[GPIO 0 bit 1]O[I/O]3.3V LVTTL 2 or 3C19 LCDD2[GPIO0_B2] LCD display data 2[GPIO 0 bit 2]O[I/O]3.3V LVTTL 2 or 3Continued on next page.C17 LCDD3[GPIO0_B3] LCD display data 3[GPIO 0 bit 3]O[I/O]3.3V LVTTL 2 or 3C14 LCDD4[GPIO0_B4] LCD display data 4[GPIO 0 bit 4]O[I/O]3.3V LVTTL 2 or 3C10 LCDD5[GPIO0_B5] LCD display data 5[GPIO 0 bit 5]O[I/O]3.3V LVTTL 2 or 3C8 LCDD6[GPIO0_B6] LCD display data 6[GPIO 0 bit 6]O[I/O]3.3V LVTTL 2 or 3B6 LCDD7[GPIO0_B7] LCD display data 7[GPIO 0 bit 7]O[I/O]3.3V LVTTL 2 or 3C5 LCDD8[GPIO0_B8] LCD display data 8[GPIO 0 bit 8]O[I/O]3.3V LVTTL 2 or 3C4 LCDD9[GPIO0_B9] LCD display data 9[GPIO 0 bit 9]O[I/O]3.3V LVTTL 2 or 3C20 LCDD10[GPIO0_B10] LCD display data 10[GPIO 0 bit 10]O[I/O]3.3V LVTTL 2 or 3B19 LCDD11[GPIO0_B11] LCD display data 11[GPIO 0 bit 11]O[I/O]3.3V LVTTL 2 or 3B18 LCDD12[GPIO0_B12] LCD display data 12[GPIO 0 bit 12]O[I/O]3.3V LVTTL 2 or 3C18 LCDD13[GPIO0_B13] LCD display data 13[GPIO 0 bit 13]O[I/O]3.3V LVTTL 2 or 3B16 LCDD14[GPIO0_B14] LCD display data 14[GPIO 0 bit 14]O[I/O]3.3V LVTTL 2 or 3C16 LCDD15[GPIO0_B15] LCD display data 15[GPIO 0 bit 15]O[I/O]3.3V LVTTL 2 or 3B15 LCDD16[PC_RESET1][GPIO0_B16] LCD display data 16[PCMCIA card reset][GPIO 0 bit 16]O[O][I/O]3.3V LVTTL 2 or 3B14 LCDD17[PC_CD11_N][GPIO0_B17] LCD display data 17[PCMCIA card detect 1][GPIO 0 bit 17]O[I][I/O]3.3V LVTTL 2 or 3B13 LCDD18[PC_CD12_N][GPIO0_B18] LCD display data 18[PCMCIA card detect 2][GPIO 0 bit 18]O[I][I/O]3.3V LVTTL 2 or 3B12 LCDD19[PC_VS11_N][GPIO0_B19] LCD display data 19[PCMCIA voltage sense 1][GPIO 0 bit 19]O[I][I/O]3.3V LVTTL 2 or 3A12 LCDD20[PC_VS12_N][GPIO0_B20] LCD display data 20[PCMCIA voltage sense 2][GPIO 0 bit 20]O[I][I/O]3.3V LVTTL 2 or 3B9 LCDD21[PC_BVD11_N][GPIO0_B21] LCD display data 21[PCMCIA battery detect 1][GPIO 0 bit 21]O[I][I/O]3.3V LVTTL 2 or 3D9 LCDD22[PC_BVD12_N][GPIO0_B22] LCD display data 22[PCMCIA battery detect 2][GPIO 0 bit 22]O[I][I/O]3.3V LVTTL 2 or 3D6 LCDD23[PC_WP1][GPIO0_B23] LCD display data 23[PCMCIA card write protect][GPIO 0 bit 23]O[I][I/O]3.3V LVTTL 2 or 3Key Scan 16 × 12 [Key Scan 6 × 4] [Smart Card Interface] [GPIO]E3 KOUT0_N[AKO0_N][GPIO1_B0] Matrix keyboard output line 0[Automatic matrix key scan output line 0][GPIO 1 bit 0]O[O][I/O]3.3V LVTTL 2 or 3K4 KOUT1_N[AKO1_N][GPIO1_B1] Matrix keyboard output line 1[Automatic matrix key scan output line 1][GPIO 1 bit 1]O[O][I/O]3.3V LVTTL 2 or 3P4 KOUT2_N[AKO2_N][GPIO1_B2] Matrix keyboard output line 2[Automatic matrix key scan output line 2][GPIO 1 bit 2]O[O][I/O]3.3V LVTTL 2 or 3Continued on next page.R4 KOUT3_N[AKO3_N][GPIO1_B3] Matrix keyboard output line 3[Automatic matrix key scan output line 3][GPIO 1 bit 3]O[O][I/O]3.3V LVTTL 2 or 3T4 KOUT4_N[AKO4_N][GPIO1_B4] Matrix keyboard output line 4[Automatic matrix key scan output line 4][GPIO 1 bit 4]O[O][I/O]3.3V LVTTL 2 or 3T3 KOUT5_N[AKO5_N][GPIO1_B5] Matrix keyboard output line 5[Automatic matrix key scan output line 5][GPIO 1 bit 5]O[O][I/O]3.3V LVTTL 2 or 3V4 KOUT6_N[GPIO1_B6] Matrix keyboard output line 6[GPIO 1 bit 6]O[I/O]3.3V LVTTL 2 or 3W4 KOUT7_N[GPIO1_B7] Matrix keyboard output line 7[GPIO 1 bit 7]O[I/O]3.3V LVTTL 2 or 3Y3 KOUT8_N[GPIO1_B8] Matrix keyboard output line 8[GPIO 1 bit 8]O[I/O]3.3V LVTTL 2 or 3AA3 KOUT9_N[GPIO1_B9] Matrix keyboard output line 9[GPIO 1 bit 9]O[I/O]3.3V LVTTL 2 or 3AC7 KOUT10_N[GPIO1_B10] Matrix keyboard output line 10[GPIO 1 bit 10]O[I/O]3.3V LVTTL 2 or 3AD7 KOUT11_N[GPIO1_B11] Matrix keyboard output line 11[GPIO 1 bit 11]O[I/O]3.3V LVTTL 2 or 3AF4 KOUT12_N[GPIO1_B12] Matrix keyboard output line 12[GPIO 1 bit 12]O[I/O]3.3V LVTTL 2 or 3AE9 KOUT13_N[GPIO1_B13] Matrix keyboard output line 13[GPIO 1 bit 13]O[I/O]3.3V LVTTL 2 or 3AE10 KOUT14_N[GPIO1_B14] Matrix keyboard output line 14[GPIO 1 bit 14]O[I/O] 3.3VLVTTL(GPIS1)[B28:29 = 01]2 or 3AD10 KOUT15_N[SC_DTSC][GPIO1_B15] Matrix keyboard output line 15[Smart card DTSC][GPIO 1 bit 15]O[O][I/O]3.3V LVTTL 2 or 3C1 KIN0_N[AKI0_N][GPIO1_B16] Matrix keyboard input line 0[Automatic matrix key scan input line 0][GPIO 1 bit 16]I[I][I/O]3.3V LVTTL 2 or 3D2 KIN1_N[AKI1_N][GPIO1_B17] Matrix keyboard input line 1[Automatic matrix key scan input line 1][GPIO 1 bit 17]I[I][I/O]3.3V LVTTL 2 or 3G4 KIN2_N[AKI2_N][GPIO1_B18] Matrix keyboard input line 2[Automatic matrix key scan input line 2][GPIO 1 bit 18]I[I][I/O]3.3V LVTTL 2 or 3K2 KIN3_N[AKI3_N][GPIO1_B19] Matrix keyboard input line 3[Automatic matrix key scan input line 3][GPIO 1 bit 19]I[I][I/O]3.3V LVTTL 2 or 3J4 KIN4_N[GPIO1_B20] Matrix keyboard input line 4[GPIO 1 bit 20]I[I/O]3.3V LVTTL 2 or 3L3 KIN5_N[GPIO1_B21] Matrix keyboard input line 5[GPIO 1 bit 21]I[I/O]3.3V LVTTL 2 or 3L4 KIN6_N[GPIO1_B22] Matrix keyboard input line 6[GPIO 1 bit 22]I[I/O]3.3V LVTTL 2 or 3N2 KIN7_N[GPIO1_B23] Matrix keyboard input line 7[GPIO 1 bit 23]I[I/O]3.3V LVTTL 2 or 3N4 KIN8_N[GPIO1_B24] Matrix keyboard input line 8[GPIO 1 bit 24]I[I/O]3.3V LVTTL 2 or 3P2 KIN9_N[GPIO1_B25] Matrix keyboard input line 9[GPIO 1 bit 25]I[I/O]3.3V LVTTL 2 or 3P3 KIN10_N[GPIO1_B26] Matrix keyboard input line 10[GPIO 1 bit 26]I[I/O]3.3V LVTTL 2 or 3R1 KIN11_N[GPIO1_B27] Matrix keyboard input line 11[GPIO 1 bit 27]I[I/O]3.3V LVTTL 2 or 3Continued on next page.PS2 Interface [GPIO]AD1 PSCLK[GPIO1_B30] PS2 keyboard clock[GPIO 1 bit 30]I/O[I/O]3.3V LVTTL 2 or 3AA4 PSDATA[GPIO1_B31] PS2 keyboard data[GPIO 1 bit 31]I/O[I/O]3.3V LVTTL 2 or 3Smart Card Interface [GPIO]AB26 SCCLK[GPIO3_B14] Smart card clock[GPIO 3 bit 14]O[I/O]3.3V LVTTL 2 or 3AC20 SCDET[GPIO3_B15] Smart card detection[GPIO 3 bit 15]I[I/O]3.3V LVTTL 2 or 3AD19 SCIO[GPIO3_B16] Smart card data[GPIO 3 bit 16]I/O[I/O]3.3V LVTTL 2 or 3AD21 SCRST[GPIO3_B17] Smart card reset[GPIO 3 bit 17]O[I/O]3.3V LVTTL 2 or 3AF22 SCVEN[GPIO3_B18] Smart card V CC enable[GPIO 3 bit 18]O[I/O]3.3V LVTTL 2 or 3IrDA [UART 2] [GPIO]A14 IRDARX[RXD2][GPIO2_B28] IrDA receive data[UART 2 receive data][GPIO 2 bit 28]I[I][I/O]3.3V LVTTL 3D20 IRDATX[TXD2][GPIO2_B29] IrDA transmit data[UART 2 transmit data][GPIO 2 bit 29]O[O][I/O]3.3V LVTTL 2 or 3D12 IRDACTR_N[RTS2_N][GPIO2_B30] IrDA transceiver enable[UART 2 request to send ][GPIO 2 bit 30]O[O][I/O]3.3V LVTTL 2 or 3UART 0 Interface [SCP] [GPIO]K26 RXD0[GPIO3_B24] UART 0 receive data[GPIO 3 bit 24]I[I/O]3.3V LVTTL 2 or 3L25 TXD0[GPIO3_B25] UART 0 transmit data[GPIO 3 bit 25]O[I/O]3.3V LVTTL 2 or 3N23 RTS0_N[GPIO3_B26] UART 0 request to send[GPIO 3 bit 26]O[I/O]3.3V LVTTL 2 or 3M23 CTS0_N[GPIO3_B27] UART 0 clear to send[GPIO 3 bit 27]I[I/O]3.3V LVTTL 2 or 3M24 DCD0_N[SCP_RX][GPIO3_B28] UART 0 DCD[Sync serial RX][GPIO 3 bit 28]I[I][I/O]3.3V LVTTL 2 or 3M25 DSR0_N[SCP_TX][GPIO3_B29] UART 0 DSR[Sync serial TX][GPIO 3 bit 29]I[O][I/O]3.3V LVTTL 2 or 3L23 DTR0_N[SCP_CLK][GPIO3_B30] UART 0 DTR[Sync serial Clock][GPIO 3 bit 30]O[O][I/O]3.3V LVTTL 2 or 3L24 RI0_N[GPIO3_B31] UART 0 RI[GPIO 3 bit 31]I[I/O]3.3V LVTTL 2 or 3UART 1 Interface [HDLC 0] [HDLC 1] [GPIO]Y24 RXD1[HDLC1_RX][GPIO3_B0] UART 1 receive data[HDLC 1 receive data][GPIO 3 bit 0]I[I][I/O]3.3V LVTTL 2 or 3Y25 TXD1[HDLC1_TX][GPIO3_B1] UART 1 transmit data[HDLC 1 transmit data][GPIO 3 bit 1]O[O][I/O]3.3V LVTTL 2 or 3AE22 RTS1_N[HDLC1_RTS_N][GPIO3_B2] UART 1 request to send[HDLC 1 request to send][GPIO 3 bit 2]O[O][I/O]3.3V LVTTL 2 or 3AF24 CTS1_N[HDLC1_CTS_N][GPIO3_B3] UART 1 clear to send[HDLC 1 clear to send][GPIO 3 bit 3]I[I][I/O]3.3V LVTTL 2 or 3Continued on next page.。

技术规格书阿尔卡特朗讯企业通信M7桌面话机阿尔卡特朗讯企业通信M7桌面话机阿尔卡特朗讯企业通信M7桌面话机专为追求舒适通话和高稳定性的企业用户而设计，可提供丰富的通信功能。

M7桌面话机造型高雅，选用高质量的音频元器件，采用优化音腔设计，在免提模式下支持超宽带音频技术，同时具有回声消除和卓越的全双工通话性能，为客户提供沉浸式音频体验。

M7桌面话机带有4向导航键、8个线路键、4个应用软键兼具3.5英寸的大型彩色屏幕，友好的用户界面设计让您与用户的沟通既快速又方便。

M7桌面话机配备两个USB 接口(TYPE A/C)，极大地扩展了M7的功能，使其不仅仅是个单纯的话机还可以连接外部设备进行扩展，如扩展模块（EM20或EM200）、耳机、会议模块等；M7支持音频转接功能（Audio Hub ），可连接PC 作为外部扬声器，从而享受超宽带音频效果；M7桌面话机通过USB 可连接Wi-Fi 外接模块，转变成为Wi-Fi 桌面电话。

M7桌面话机支持标准的SIP 协议，能够兼容市场上主流的SIP 通信服务器并提供丰富的电话功能。

M7桌面电话支持以太网供电模式(POE)，并配备可调节的脚架。

Bluetooth 4.1 连接蓝牙耳机可实现无线连接，最远离办公桌10米超带宽音质免提模式下支持超宽带音频3.5英寸大型彩色屏幕和4向导航按钮轻松导航并方便与同事或客户联系造型高雅，带可调支架适合多种使用环境：办公桌、酒店客房和医院床边等可定制面板显示组织机构的标志，打造品牌知名度标准SIP 协议，提供丰富的电话功能可以获取首选云PBX 服务商提供的业务功能，例如电话管理及电话会议等轻松部署支持ALE 快速配置平台/快速定向平台，配置和部署非常轻松/zh-cn 阿尔卡特朗讯（Alcatel-Lucent ）的名称和商标均由诺基亚（Nokia ）授权于ALE （Alcatel-Lucent Enterprise ）使用。

若要查阅ALE 公司旗下公司使用的其他商标，请访问：/zh-cn/legal/trademarks-copyright 。