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Bipolar logic 1960’s
ECL 3-input Gate Motorola 1966
4
Wafer， die， chip
Single die
From http://www.amd.com
Wafer
Going up to 12” (30cm)
5
CMOS Process
6
A Modern CMOS Process
photoresist removal (ashing)
photoresist coating
process step
spin, rinse, dry
acid etch
stepper exposure
photoresist development
8
a single photolithographic cycle (from [Fullman]).
集成电路 版图设计与
解析
.
1
1、Introduction
IC – Integrated circuits Wafer, die and chip CMOS Process Modern CMOS Process Photo-Lithographic Process Mask View
2
3
Chip View
21
CMOS Inverters
PMOS
VDD
横栅结构
In Polysilicon
NMOS
1.2m =2
Out Metal1
GND
22
Layout Editor
23
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um. 24
n+
xd
Drain
W
xd
n+
Ld Top view
tox
n+
L
Gate-bulk overlap
Gate oxide
n+
Cross section
16
Vias and Contacts
Via 1
Metal to 1 Active Contact
1 Metal to Poly Contact
2 4
5
3、Mask Design
库单元设计 标准单元设计 门阵列设计 数据通路单元设计 存储器设计 其他单元设计：PAD、ESD
25
（1）Cell Design
Standard Cells
General purpose logic Can be synthesized Same height, varying width
VDD
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
Cell height is “12 pitch”
Out
2
In
Cell boundary
Rails ~10
19
CMOS Inverter
N Well
VDD
PMOS
VDD 2
PMOS
Contacts
In
Out
In
Out
Metal 1
NMOS
Polysilicon
NMOS
GND
20
Two CMOS Inverters
Share power and ground
纵栅结构
Abut cells
VDD Connect in Metal
3
2
2 2
17
Select Layer
2 3
1 3
2
5
Select 2
3
Substrate
Well
18
CMOS Inverter Layout
GND
In
VDD
A
A’
Out (a) Layout
A
A’
p-substrate n+
n p+
Field Oxide
(b) Cross-Section along A-A’
gate-oxide
Tungsten n+
p-well
p-epi p+
TiSi2
AlCu SiO2
poly
n-well
SiO2 p+
Dual-Well Trench-Isolated CMOS Process
7
Photo-Lithographic Process
oxidation
optical mask
0 or 6 10
3
Select
3 2
Different Potential
9
2
Polysilicon
2
Metal1
3
Contact
or Via
2
Hole
3
2
Metal2
4
3
14
Transistor Layout
Transistor
1
3
2
5
15
MOSFET
Polysilicon gate
Source
CMOS工艺
P+
VDD
Out In
GND
In
Layout
N+区 光 刻
VDD
M2 Out
VDD
M1
CMOS Inverter 9
Mask View
10
2、Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width
Color
Yellow Green Green Red Blue Magenta Black Black Black
Representation
12
Layers in 0.25 m CMOS process
13
Intra-Layer Design Rules
Same Potential
Well Active
GND 29
Standard Cells
With minimal diffusion routing
VDD With silicided diffusion
VDD
M2
Out
In
In
Out
In
M1
GND
VDD
Out GND 30
scalable design rules: lambda parameter absolute dimensions (micron rules)
11
CMOS Process Layers
Layer
Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via
Datapath Cells
For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width
26
Standard Cell Layout Methodology – 1980s
Routing channel
VDD
signals
GND
27
Standard Cell Layout Methodology – 1990s
Mirrored Cell
No Routing
VDD
channels
wk.baidu.com
VDD
M2
M3
Mirrored Cell
GND
GND
28
N Well
Standard Cells
