66577-7中文资料

FEATURES:• Cable connection for RG 58 and 142, 223, 141MATERIALS:Body and Fitting – Brass per QQ-B-626, Alloy 360, ½ HardCenter Contact – Gold Plated Brass per QQ-B-626, Alloy 360, ½ Hard Dielectric – PTFEGaskets and Seals: Silicone RubberFinish: Body and Fittings: Tarnish resistantCenter Contact: Gold flash over silver plate per QQ-S-365 RATINGS:Nominal Impedance: 50 OhmsDielectric Withstanding Voltage: 2500 VRMS, 1 Min., 60 Hz. ORDERING INFORMATION: Model 4787All dimensions are in inches. Tolerances (except noted): .xx = ±.02” (,51 mm), .xxx = ± .005” (,127 mm).All specifications are to the latest revisions. Specifications are subject to change without notice.Registered trademarks are the property of their respective companies.Made in USAFIGURE #1A. Slide clamp nut, flat washer and Vee gasket over cable.B. Strip cable jacket to dimensions shown.FIGURE #1AC. Slide braid clamp over braid positioned with the inner shoulder against the cable jacketD. Fold braid over braid clamp.E. Strip DielectricFIGURE #2F. Solder center contact to cable center conductor.FIGURE #3G. Slide clamp nut, flat washer and Vee gasket forward against braid clamp.A. Place connector body over end of cable, thread clamp nut into body and tighten.All dimensions are in inches. Tolerances (except noted): .xx = ±.02” (,51 mm), .xxx = ± .005” (,127 mm).All specifications are to the latest revisions. Specifications are subject to change without notice.Registered trademarks are the property of their respective companies.Made in USA。

April 1996NEC Electronics Inc.A10616EU1V0DS00CMOS-8LHD3.3-Volt, 0.5-Micron CMOS Gate ArraysPreliminary DescriptionNEC's CMOS-8LHD gate-array family combines cell-based-level densities with the fast time-to-market and low development costs of gate arrays. With a unique heterogeneous cell architecture, CMOS-8LHD provides the very dense logic and RAM capabilities required to build devices for fast computer and communications systems.NEC delivers high-speed, 0.5-micron, drawn gate length (Leff=0.35-micron), three-level metal, CMOS technology with an extensive family of macros. I/O macros include GTL, HSTL, and pECL. TTL CMOS I/Os are provided with 5-V tolerance for applications requiring interface to 5-V logic. PCI signaling standards are also supported,including 3.3-V, 66 MHz PCI. The technology is enhanced by a set of advanced features, including phase-locked loops, clock tree synthesis, and high-speed memory. The CMOS-8LHD gate-array family of 3.3-V devices consists of 12 masters, offered in densities of 75K raw gates to 1.123 million raw gates. Usable gates range from 45K to 674K used gates.The gate-array family is supported by NEC's OpenCAD ®design system, a mixture of popular third-party EDA tools,and proprietary NEC tools. NEC proprietary tools include the GALET floorplanner, which helps to reduce design time and improve design speed, and a clock tree synthesis tool that automatically builds a balanced-buffer clock tree to minimize on-chip clock skew.Figure 1. CMOS-8LHD Package Options: BGA & QFPTable 1. CMOS-8LHD Family Features and BenefitsCMOS-8LHD ApplicationsThe CMOS-8LHD family is ideal for use in personal computer systems, engineering workstations, and telecommunications switching and transmission systems, where extensive integration and high speeds are primary design goals. With power dissipation of 0.21 µW/MHz/gate, CMOS-8LHD is also suited for lower-power applications where high performance is required.OpenCAD is a registered trademark of NEC Electronics Inc.CMOS-8LHD2Cell-Based Array ArchitectureThe CMOS-8LHD gate-array family is built with the Cell-Based Array (CBA) architecture licensed from the Silicon Architects Group of Synopsys. CBA architecture uses two types of cells: compute cells and drive cells.This heterogeneous cell architecture enables very high-density design. Compute cells are used to optimize intramacro logic. Drive cells are optimized for intermacro interconnect. The two cell types are also used to build macros with up to three different power/performance/area points.CBA has a rich macrocell library that is optimized for synthesis. RAM blocks are efficiently created from the CBA architecture, using compute cells as memory cores, and sense amplifiers and drive cells as word and address predecoder drivers.As shown in Figure 2, CBA is divided into I/O and array regions. The I/O region contains input and output buffers. The array region contains the gates used to build logic, RAM blocks, and other design features.Power Rail ArchitectureCMOS-8LHD provides additional flexibility for mixedvoltage system designs. As shown in Figure 2, the arrays contain two power rails: a 3.3-V rail, and V DD2.The V DD2 rail is used for interfaces such as 5-V PCI buffers where a clamping diode allows protection for up to an 11-V voltage spike, per the PCI revision 2.1specification.Figure 2. CBA Layout and Cell ConfigurationThe V DD2 rail is separated into sections to give flexibility for including two or more buses requiring special I/O voltage on one device. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones.Packaging and TestNEC utilizes BIST test structures for RAM testing. NEC also offers advanced packaging solutions including Plastic Ball Grid Arrays (PBGA), Plastic Quad Flat Packs (PQFP), and Pin Grid Arrays (PGA). Please call your local NEC ASIC design center representative for a listing of available master/package combinations.PublicationsThis data sheet contains preliminary specifications for the CMOS-8LHD gate-array family. Additional infor-mation will be available in NEC's CMOS-8LHD Block Library and CMOS-8LHD Design Manual . Call your local NEC ASIC design center representative or the NEC literature line for additional ASIC design information; see the back of this data sheet for locations and phone numbers.Table 2. CMOS-8LHD Base Array Line-upDevice Raw Gates Used Gates (1)Total Pads66562750404502416466563997925987518866565125216751292126656617963210777925266568202400121440268665692681281608763086657029792017875232466571359744215845356665725008643005184206657362054437232646866575802240481344532(1) Actual gate utilization varies depending on circuit implementation.Utilization is 60% for 3LM.3CMOS-8LHDInput/Output CapacitanceV DD =V I =0-V; f =1 MHzTerminal Symbol Typ Max Unit Input C IN 1020pF Output C OUT 1020pF I/OC I/O1020pF(1)Values include package pin capacitancePower ConsumptionDescription Limits Unit Internal gate (1)0.21µW/MHz Input buffer 2.546µW/MHz Output buffer10.60µW/MHzAbsolute Maximum RatingsPower supply voltage, V DD –0.5 to +4.6-VInput voltage, V I3.3-V input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 3.3-V fail-safe input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 5 V-tolerant (at V I < V DD + 3.0-V)–0.5 to +4.6-V Output Voltage, V O3.3-V output buffer (at V O < V DD + 0.5-V)–0.5 to +4.6-V 5-V-tolerant output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-V 5-V open-drain output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-VLatch-up current, I LATCH >1 A (typ)Operating temperature, T OPT –40 to +85°C Storage temperature, T STG–65 to +150°C (1) Assumes 30% internal gate switching at one timeCaution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions.Recommended Operating ConditionsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C3.3-V Interface 5-V Interface5-V PCI 3.3-V PCIBlock BlockLevel LevelParameterSymbol Min Max Min Max Min Max Min Max Unit I/O power supply voltage V DD 3.0 3.6 3.0 3.6 3.0 5.5 3.0 3.6V Junction temperature T J 0+1000+1000+1000+100°C High-level input voltage V IH 2.0V DD 2.0 5.5 2.0V CC 0.5 V CCV CC V Low-level input voltage V IL 00.800.800.800.3 V CCV Positive trigger voltage V P 1.50 2.70 1.50 2.70————V Negative trigger voltage V N 0.60 1.60.60 1.6————V Hysteresis voltage V H 1.10 1.3 1.10 1.3————V Input rise/fall time t R , t F 0200020002000200ns Input rise/fall time, Schmittt R , t F1010————nsAC CharacteristicsV DD = 3.3-V ±0.3-V; T j = –40 to +125°C ParameterSymbol MinTypMax Unit Conditions Toggle frequency (F611)f TOG356MHzD-F/F; F/O = 2 mmDelay time2-input NAND (F322)t PD181ps F/O = 1; L = 0 mmt PD 186ps F/O = 2; L = typ (0.42 mm)Flip-flop (F611)t PD 573ps F/O = 1; L = 0 mm t PD 688ps F/O = 2; L = typ t SETUP 410ps —t HOLD 540ps —Input buffer (FI01)t PD 268ps F/O = 1; L = 0 mm t PD 312ps F/O = 2; L = typ Output buffer (9 mA) 3.3-V (FO01)t PD 1.316ns C L = 15 pF Output buffer (9 mA) 5-V-tolerant (FV01)t PD 1.228ns C L = 15 pF Output buffer (9 mA) 5-V-swing (FY01)t PD 1.517ns C L = 15 pF Output rise time (9 mA) (FO01)t R 1.347ns C L = 15 pF Output fall time (9 mA) (FO01)t F1.284nsC L = 15 pFCMOS-8LHD4(3)Rating is for only one output operating in this mode for less than 1 second.(4)Normal type buffer: I OH < I OL .(5)Balanced buffer: I OH = I OL .(6)Resistor is called 50ký to maintain consistency with previous families.Notes:(1)Static current consumption increases if an I/O block with on-chip pull-up/pull-down resistor or an oscillator is used. Call an NEC ASIC design center repre-sentative for assistance in calculation.(2)Leakage current is limited by tester capabilities. Specification listed representsthis measurement limitation. Actual values will be significantly lower.DC CharacteristicsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C ParameterSymbol Min Typ Max Unit Conditions Quiescent current (1)µPD66578I DDS 2.0300µA V I = V DD or GND µPD66575, 66573, 66572I DDS 1.0300µA V I = V DD or GND Remaining mastersI DDS 0.5200µA V I = V DD or GND Off-state output leakage current3.3-V buffers, 3.3-V PCII OZ ±10µA V O = V DD or GND 5-V-tolerant buffers, 5-V PCI I OZ ±14µA V O = V DD or GND 5-V open-drainI OZ ±14µA V O = V DD or GND Output short circuit current (3)I OS –250mA V O = GND Input leakage current (2)5-V PCI I IH +70, –70µA V IN = 2.7-V, 0.5-V 3.3-V PCI I I ±10µA V IN = V DD or GND RegularI I ±10–5±10µA V I = V DD or GND 50 k Ω pull-up I I –180–40µA V I = GND 5 k Ω pull-up I I –1400–350mA V I = GND 50 k Ω pull-down I I 30160µA V I = V DDResistor values50 k Ω pull-up (6)R pu 2075k Ω5 k Ω pull-upR pu 2.68.6k Ω50 k Ω pull-down (6)R pu 22.5100k ΩInput clamp voltageV IC –1.2V I I = 18 mA Low-level output current (ALL buffer types)3 mA I OL 3mA V OL = 0.4-V 6 mA I OL 6mA V OL = 0.4-V 9 mA I OL 9mA V OL = 0.4-V 12 mA I OL 12mA V OL = 0.4-V 18 mA I OL 18mA V OL = 0.4-V 24 mAI OL 24mA V OL = 0.4-V High-level output current (5-V-tolerant block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –3mA V OH = V DD –0.4-V 9 mA I OH –3mA V OH = V DD –0.4-V 12 mA I OH –3mA V OH = V DD –0.4-V 18 mA I OH –4mA V OH = V DD –0.4-V 24 mAI OH –4mA V OH = V DD –0.4-V High-level output current (3.3-V interface block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –6mA V OH = V DD –0.4-V 9 mA I OH –9mA V OH = V DD –0.4-V 12 mA I OH –12mA V OH = V DD –0.4-V 18 mA I OH -18mA V OH = V DD –0.4-V 24 mAI OH -24mA V OH = V DD –0.4-V Output voltage (5-V PCI)High-level output voltage V OH 2.4mA I OH = 2 mALow-level output voltage V OL 0.55mA I OL = 3 mA, 6 mA Output voltage (3.3-V PCI)High-level output voltage V OH 0.9 V DDmA I OH = 500 µA Low-level output voltage V OL 0.1 V DDmA I OL = 1500 µA Low-level output voltageV OL 0.1V I OL = 0 mA High-level output voltage, 5-V TTL V OH V DD –0.2V I OL = 0 mA High-level output voltage, 3.3-VV OHV DD –0.1VI OH = 0 mACMOS-8LHD5CMOS-8LHD6Document No. A10616EU1V0DS00For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782or FAX your request to: 1-800-729-9288©1996 NEC Electronics Inc./Printed in U.S.A.NEC ASIC DESIGN CENTERSWEST•3033 Scott Boulevard Santa Clara, CA 95054TEL 408-588-5008FAX 408-588-5017•One Embassy Centre9020 S.W. Washington Square Road,Suite 400Tigard, OR 97223TEL 503-671-0177FAX 503-643-5911THIRD-PARTY DESIGN CENTERSSOUTH CENTRAL/SOUTHEAST•Koos Technical Services, Inc.385 Commerce Way, Suite 101Longwood, FL 32750TEL 407-260-8727FAX 407-260-6227•Integrated Silicon Systems Inc.2222 Chapel Hill Nelson Highway Durham, NC 27713TEL 919-361-5814FAX 919-361-2019•Applied Systems, Inc.1761 W. Hillsboro Blvd., Suite 328Deerfield Beach, FL 33442TEL 305-428-0534FAX 305-428-5906NEC Electronics Inc.CORPORATE HEADQUARTERS2880 Scott Boulevard P.O. Box 58062Santa Clara, CA 95052TEL 408-588-6000No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY,WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding informa-tion set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems,aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. “Standard” quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools,industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-disaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death.If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL’s willingness to support a given application.SOUTH CENTRAL/SOUTHEAST•16475 Dallas Parkway, Suite 380Dallas, TX 75248TEL 972-735-7444FAX 972-931-8680•Research Triangle Park2000 Regency Parkway, Suite 455Cary, NC 27511TEL 919-460-1890FAX 919-469-5926•Two Chasewood Park 20405 SH 249, Suite 580Houston, TX 77070TEL 713-320-0524FAX 713-320-0574NORTH CENTRAL/NORTHEAST•The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701TEL 508-935-2200FAX 508-935-2234•Greenspoint Tower2800 W. Higgins Road, Suite 765Hoffman Estates, IL 60195TEL708-519-3945FAX 708-882-7564。

AS4497.1—1997Australian Standard®Roundslings—Synthetic fibrePart1:Product specificationThis Australian Standard was prepared by Committee ME/25,Lifting Tackle.It was approved on behalf of the Council of Standards Australia on8August1997and published on5October1997.The following interests are represented on Committee ME/25:Australian Chamber of Commerce and IndustryAustralian Chamber of ManufacturesAustralian Forging GroupAustralian Maritime Safety AuthorityDepartment of DefenceInstitution of Engineers,AustraliaMetal Trades Industry Association of AustraliaNational Association of Testing Authorities,AustraliaVictorian WorkCover AuthorityWork Health Authority,N.T.WorkCover N.S.W.Workplace Standards Authority(Tasmania)Review of Australian Standards.To keep abreast of progress in industry,Australian Standards are subject to periodic review and are kept up to date by the issue of amendments or new editions as necessary.It is important therefore that Standards users ensure that they are in possession of the latest edition,and any amendments thereto.Full details of all Australian Standards and related publications will be found in the Standards Australia Catalogue of Publications;this information is supplemented each month by the magazine‘The Australian Standard’,which subscribing members receive,and which gives details of new publications,new editi ons and amendments,and of withdrawn Standards.Suggestions for improvements to Australian Standards,addressed to the head office of Standards Australia, are welcomed.Notification of any inaccuracy or ambiguity found in an Australian Standard should be made without delay in order that the matter may be investigated and appropriate action taken.This Standard was issued in draft form for comment as DR96096.AS4497.1—1997Australian Standard®Roundslings—Synthetic fibrePart1:Product specificationFirst published as AS4497.1—1997.PUBLISHED BY STANDARDS AUSTRALIA(STANDARDS ASSOCIATION OF AUSTRALIA)1THE CRESCENT,HOMEBUSH,NSW2140ISBN0733714374AS4497.1—19972PREFACEThis Standard was prepared by the Standards Australia Committee ME/25on Lifting Tackle.Cognizance was taken of the CEN draft for comment94/709222DC,Draft European Standard Textile slings—Safety,Part2:Specification for round slings made of man-made fibres(prEN1492-2).The terms‘normative’and‘informative’have been used in this Standard to define the application of the appendix to which they apply.A‘normative’appendix is an integral part of a Standard,whereas an‘informative’appendix is only for information and guidance.©Copyright STANDARDS AUSTRALIAUsers of Standards are reminded that copyright subsists in all Standards Australia publications and software.Except where the Copyright Act allows and except where provided for below no publications or software produced by Standards Australia may be reproduced,stored in a retrieval system in any form or transmitted by any means without prior permission in writing from Standards Australia.Permission may be conditional on an appropriate royalty payment.Requests for permission and information on commercial software royalties should be directed to the head office of Standards Australia.Standards Australia will permit up to10percent of the technical content pages of a Standard to be copied for use exclusively in-house by purchasers of the Standard without payment of a royalty or advice to Standards Australia.Standards Australia will also permit the inclusion of its copyright material in computer software programs for no royalty payment provided such programs are used exclusively in-house by the creators of the programs.Care should be taken to ensure that material used is from the current edition of the Standard and that it is updated whenever the Standard is amended or revised.The number and date of the Standard should therefore be clearly identified.The use of material in print form or in computer software programs to be used commercially,with or without payment,or in commercial contracts is subject to the payment of a royalty.This policy may be varied by Standards Australia at any time.3AS4497.1—1997CONTENTSPage1SCOPE (4)2REFERENCED DOCUMENTS (4)3DEFINITIONS (4)4MATERIAL (12)5DESIGN AND MANUFACTURE (12)6MECHANICAL PROPERTIES (13)7MARKING (13)8TESTING OF MECHANICAL PROPERTIES (16)9PROOF TESTING (16)APPENDICESA INFORMATION THAT SHOULD BE SUPPLIED WITHENQUIRIES AND ORDERS (18)B CONDITIONS FOR APPLICATION OF TEST FORCES (19)C MEANS FOR DEMONSTRATING COMPLIANCE WITH THISSTANDARD (20)AS4497.1—19974STANDARDS AUSTRALIAAustralian StandardRoundslings—Synthetic fibrePart1:Product specification1SCOPE This Standard specifies requirements for roundslings made of synthetic fibre that are intended for lifting purposes.This Standard does not apply to slings that have been repaired.NOTES:1Guidance on information that should be supplied with enquiries and orders is given in Appendix A.2Recommendations for the care and use of roundslings are given in AS4497.2.2REFERENCED DOCUMENTS The following documents are referred to in this Standard:AS1199Sampling procedures and tables for inspection by attributes1399Guide to AS1199—Sampling procedures and tables for inspection by attributes2193Methods for calibration and grading of force-measuring systems of testing machines3585End fittings for flat-webbing slings3776Lifting components for Grade T chain slings4497Roundslings—Synthetic fibre4497.2Part2:Care and useAS/NZSISO9000Quality management and quality assurance standardsISO9000.1Part1:Guidelines for selection and useISO9904Quality management and quality system elementsISO9004.1Part1:GuidelinesSAAHB18Guidelines for third-party certification and accreditationHB18.28Guide28—General rules for a model third-party certification scheme for products3DEFINITIONS For the purpose of this Standard,the definitions below apply.3.1Competent person—a person having practical and theoretical knowledge andrelevant experience,sufficient to enable that person to detect and evaluate any defects and any weaknesses that may affect the intended performance of the equipment.3.2Effective length—the distance between the bearing points of the sling,includingany end fittings,while stretched out by hand(without noticeable tension)on a flat surface (see Figure1and Clause5.5).5AS4497.1—1997 3.3End fitting—a load-bearing metal fitting that is designed to be attached to the endof a sling(see Figures1(b)and3).3.4Load-bearing core—a hank of high-tenacity continuous-multifilament yarn that comprises the load-bearing part of a roundsling(see Figures2(b),2(c),2(d)and2(e)).3.5Protective sleeve—a sleeve placed over the woven cover(see Clause3.12), providing protection but having no effect on the breaking force of a sling.3.6Roundsling—an endless sling comprising a load-bearing core of high-tenacity continuous-multifilament yarn that is completely enclosed in a woven cover,with or without fittings or coupling components.3.7Shall—indicates that a statement is mandatory.3.8Should—indicates a recommendation.3.9Sling with end fittings—a sling having one or both ends terminated with a metal fitting(see Figure3(a)).Two end fittings on a sling need not be identical.If a sling is designed for choked slinging,one fitting should be able to pass through the other fitting.3.10Strop A roundsling modified by holding the two legs together to form an eye at each end(see Figures2(d)and2(e)).3.11Working load3.11.1Working load limit(WLL)—the maximum load that may be applied to the sling,in tension,under general conditions of use.3.11.2Safe working load(SWL)—the maximum load that may be applied to the sling under the particular conditions of use(see AS4497.2).3.12Woven cover—a tube of woven fabric or woven webbing that is joined along its length to enclose a load-bearing core of a roundsling.AS4497.1—19976FIGURE1ROUNDSLING7AS4497.1—1997FIGURE2(in part)TYPICAL ROUNDSLINGSCOPYRIGHTAS4497.1—19978(c)RoundslingFIGURE2(in part)TYPICAL ROUNDSLINGSCOPYRIGHT9AS4497.1—1997(d)Roundsling strop with protective sleeve and one side reinforcedFIGURE2(in part)TYPICAL ROUNDSLINGSAS4497.1—199710(e)Roundsling strop with protective sleeve and both sides reinforcedFIGURE2(in part)TYPICAL ROUNDSLINGS11AS4497.1—1997FIGURE3TYPICAL ROUNDSLING STROP ASSEMBLIESAS4497.1—1997124MATERIAL The load-bearing core and the sewing thread of roundslings shall be constructed from a high-tenacity continuous-multifilament synthetic fibre.Load-bearing fibres shall have a tenacity of not less than60cN/tex.Woven covers should be constructed of thermofixed fibres of the same material type as those of the core.Typical fibre materials include—(a)aramid polyamide for the core together with another material that resists ultravioletradiation for the cover;(b)nylon(i.e.polyamide),for both the core and the cover;(c)polyester,for both the core and the cover;and(d)ultraviolet-light-stabilized polypropylene,for both the core and the cover.5DESIGN AND MANUFACTURE5.1Core The core shall be formed from one or more yarns,wound together with11turns or more,and joined to form a single hank.Any joins in the yarns,other than those at the start and finish of the core,shall be separated from the start and finish of the core by four or more turns.Also,there shall be an extra turn for each additional join.NOTE:The core should be uniformly wound to ensure even distribution of the load.5.2Multileg slings The legs of multileg slings are normally interconnected by one ofthe following arrangements:(a)For two-leg slings,by attaching each of the legs directly to a master link.(b)For three-leg or four-leg slings,by using a master link assembly with twointermediate links,and attaching two of the sling legs directly to one of theintermediate links and the other sling leg or two sling legs directly to the otherintermediate link.5.3Overcrowding To prevent overcrowding of multileg slings,each link that supportstwo or more legs in a sling shall be of an adequate size that will allow these legs to support a load with an included angle between the legs of60°,without the legs contacting each other.5.4Cover The cover shall inhibit abrasion and the ingress of abrasive particles,be freefrom any defect likely to affect safety and be made with the ends overlapped and sewn.The edges of the cover material shall be finished in such a way that they cannot unravel.NOTES:1Finishes and coatings should not impair the performance of roundslings.2Sealing can be achieved by a variety of processes,such as close weaving or heat setting (also known as thermofixing).3Care should be taken that any heat sealing of a cover does not affect the core adversely.5.5Effective length The effective length(see Clause3.2)of slings of synthetic fibreshall be measured more than10min after the release of any forces and shall be expressed in metres.Such a measured length shall have an accuracy of±3percent of the nominal length.5.6Sewing Seam-stitching thread shall be of the same material as that of the cover andthe core,except where the core is of aramid polyamide.The stitches shall be made with a locking stitch.NOTE:To facilitate inspection,stitching threads may be of a different colour from that of the cover.13AS4497.1—19975.7Protective sleeves Any protective sleeves used on roundslings—(a)if completely enclosing the woven cover specifically to provide an increasedresistance to heat or protection against damage from weld splatter,may be ofdissimilar materials;or(b)if not covered by Item(a)above—(i)not sewn to sling—if not sewn to the sling,shall be capable of being moved,to enable the full length of the cover of the sling to be inspected;or (ii)sewn to sling—if sewn to the sling,shall be of the same fibre material and have the same mechanical properties as the cover.5.8End fittings Any end fittings shall have a working load limit of not less than thatof the sling and comply with AS3585or AS3776.The interface between the cover andthe end fitting shall be such that the strength of the sling leg will not be compromised by either overcrowding or the interface contact area.6MECHANICAL PROPERTIES6.1Yarn component The yarn component of each sling(i.e.the roundsling except forany metal end fittings)shall be capable of withstanding a test force equivalent to T timesthe working load limit of the sling under the conditions specified in Appendix B,whereT=8.2for nylon fibres and T=7for other fibres.NOTES:1This test force is generally referred to as the minimum breaking strength.2The higher factor for nylon fibres is to allow for a15percent reduction of strength when wet by water.6.2End fittings Clause5.8requires any end fitting to comply with AS3585orAS3776,which include requirements for mechanical properties.NOTE:Fittings and coupling components may have different factors of safety from that for the yarn components of the roundsling to which they are connected.7MARKING7.1Information7.1.1Mandatory Each sling shall be permanently legibly marked with the following information:(a)Working load limit.(b)SWL for various lifting configurations.The SWL of multileg slings shall be stated on the tag attached to the master link.NOTE:Where multileg sling assemblies are configured,ensure that there is no confusionbetween the working load limit of each leg with the SWL of the whole assembly.Also,referto AS4497.2.(c)Fibre material(e.g.nylon,polyester,polypropylene or aramid polyamide,asapplicable).(d)Month and year of manufacture of the sling.(e)Identification marking to correlate the sling to a test certificate or batch number.(f)Manufacturer’s identification.NOTE:In any lifting or handling system that consists of components of different capacities,it is dangerous for each of these components to be tagged with its different capacity.A tag specifically marked for a higher capacity component could inadvertently be understood to refer to the complete lifting system.AS4497.1—1997147.1.2Optional The following list of precautionary warnings should also be provided:(a)Consult sling manufacturer or supplier for configurations not shown on the sling tagor a relevant load chart.(b)Do not use sling if tag is removed.(c)Inspect sling for damage before each use.(d)Do not use sling if there is any sign of a cut cover,snagging,heat or chemicaldamage,excessive wear,damaged seams,any other defects or presence of grit,abrasive materials or other deleterious matter.(e)Do not tie knots in sling.(f)Protect sling from sharp edges of load.(g)Do not expose sling to temperatures above...NOTE:Insert a safe maximum rmation on safe temperatures is given underselection of material in AS4497.2.(h)Do not allow abrasive or other damaging grit to penetrate the fibres.(i)Consult with manufacturer’s recommendations,before immersing a sling in achemical solution.(j)Keep away from....NOTE:Insert‘acids’,‘alkalis’,or‘phenolic compounds’,as applicable.NOTES:1A typical label is shown in Figure4.2Manufacturers making a statement of compliance with this Standard on a product,packaging or promotional material related to that product are advised to ensure that such compliance iscapable of being verified.7.2Means The marking required by Clause7.1shall be given on—(a)for single-leg slings,a label of a suitable material that is permanently attached tothe woven cover of the sling by sewing;or(b)for multileg slings,a durable and corrosion-resistant tag that is permanently affixedto the master link.7.3Colour The colour of the label of the sling leg shall be used to identify the fibrematerial,using the following colour code:Fibre material ColourNylonPolyester Polypropylene Aramid polyamide Green Blue Brown YellowWhere the colour of the sling leg is used to identify its WLL,the following colour code shall be used:15AS4497.1—1997FIGURE4TYPICAL LABEL FOR A ROUNDSLINGAS4497.1—199716Working load limit,t Colour1 2 3 4Violet Green Yellow Grey568≥10Red Brown Blue Orange8TESTING OF MECHANICAL PROPERTIES Compliance of each design with the requirements of Clause6shall be demonstrated.NOTES:1The test of each design is known as the type test,which determines the adequacy of the design for achieving the required performance.2Each change in manufacturing process,grade of material,design,end fittings and size other than length necessitates separate type testing,to demonstrate compliance with the requirements of Clause6.3In addition to type testing,effective quality control necessitates systematic testing of each lot or batch to ensure continuing compliance with the requirements of Clause6.Such a lot may include slings that only vary in length.4Methods for demonstrating compliance with this Standard are given in Appendix C.9PROOF TESTING9.1Proof loading Each sling shall be subjected to a proof force that is not less than [2×9.81×(WLL,in tonnes)]kN applied under the conditions specified in Appendix B.9.2Requirements The sling shall—(a)withstand the application of the proof force,without sustaining damage that couldaffect its intended function or safety;and(b)after testing,be free from any deleterious permanent set or visible defects.A competent person(see Clause3.1)shall be satisfied that the sling complies with these requirements.9.3Test certificate The proof testing shall be recorded on a test certificate,which shall bear the following information:(a)Type of any end fittings.(b)Sling material.(c)Effective length.(d)For single-leg slings or endless slings,working load limit.(e)For multileg slings,working load limit or safe working load.(f)Proof force.(g)Date of proof test.(h)Number tested.(i)Identification marking correlating with the slings.(j)A declaration that the slings comply with this Standard.17AS4497.1—1997(k)The name and address of the manufacturer or supplier.(l)The name and address of the testing establishment.(m)The name of the signatory.(n)Type of certificate(e.g.NATA,certifying authority,supplier).NOTE:The manufacturer or supplier should retain the original test certificate for not less than 10years.AS4497.1—199718APPENDIX AINFORMATION THAT SHOULD BE SUPPLIED WITHENQUIRIES AND ORDERS(Informative)The following information should be supplied with enquiries and orders for roundslings:(a)Working load limit.(b)Effective length(see Clause3.2).(c)Material.(d)End fittings,if any,which may be different on each end.(e)Any protective sleeves or coatings.(f)Nature of loads to be handled.(g)Manner of use(e.g.direct loading,basket hitch,choke hitch).(h)Size of hook or details of other lifting devices with which the sling is to be used.(i)Significant environmental conditions(e.g.exposure to chemicals,heat,moisture,sunlight,abrasive substances including grit).(j)Any required means for demonstrating compliance with this Standard(see Appendix C).(k)Any required additional testing such as non-destructive testing.(l)Type of certificate(e.g.NATA,certifying authority,supplier).(m)Whether a copy of the test certificate is to be supplied.19AS4497.1—1997APPENDIX BCONDITIONS FOR APPLICATION OF TEST FORCES(Normative)The following conditions apply to the application of test forces to roundslings:(a)The testing machine shall be calibrated in accordance with AS2193and shall becapable of Class A results when testing mechanical properties(see Clause6)andClass C results when proof testing(see Clause9).(b)Manufacturing processes,other than any proof loading and any application oftemporary protective coatings for storage purposes,shall be completed.(c)Where end fittings are part of the slings,either—(i)test the complete sling;or(ii)test the sling components separately,including—(A)the end fittings in accordance with AS3585or AS3776;and(B)the components,incorporating an interface that is similar to that of theend fittings.(d)Each end of the sling shall be held as follows:(i)For slings without end fittings—by means of an attachment with a suitablecontact radius and with the seam of the sling away from the attachment.(ii)For slings with end fittings—by means of an attachment with a contact radius.(e)The sling shall not be twisted along its length during the test.(f)Distribute the core evenly over the attachment,without any fold in the cover at thecontact section.(g)Keep the ends of the protective cover clear of the attachment.(h)The test force shall be applied to the sling in tension.AS4497.1—199720APPENDIX CMEANS FOR DEMONSTRATING COMPLIANCE WITH THIS STANDARD(Informative)C1SCOPE This Appendix sets out the following different means by which compliance with this Standard can be demonstrated by the manufacturer or supplier:(a)Evaluation by means of statistical sampling.(b)The use of a product certification scheme.(c)Assurance using the acceptability of the supplier’s quality system.(d)Other such means proposed by the manufacturer or supplier and acceptable to thecustomer.C2STATISTICAL SAMPLING Statistical sampling is a procedure which enables decisions to be made about the quality of batches of items after inspecting or testing onlya portion of those items.This procedure will only be valid if the sampling plan has beendetermined on a statistical basis and the following requirements are met:(a)The sample shall be drawn randomly from a population of product of knownhistory.The history shall enable verification that the product was made from knownmaterials at essentially the same time,by essentially the same processes and underessentially the same system of control.(b)For each different situation,a suitable sampling plan needs to be defined.Asampling plan for one manufacturer of given capability and product throughput maynot be relevant to another manufacturer producing the same items.In order for statistical sampling to be meaningful to the customer,the manufacturer or supplier needs to demonstrate how the above conditions have been satisfied.Sampling and the establishment of a sampling plan should be carried out in accordance with AS1199, guidance to which is given in AS1399.C3PRODUCT CERTIFICATION The purpose of product certification is to provide independent assurance of the claim by the manufacturer that products comply with the stated Standard.The certification scheme should meet the criteria described in SAA HB18.28in that,as well as full type testing from independently sampled production and subsequent verification of conformance,it requires the manufacturer to maintain effective quality planning to control production.The certification scheme serves to indicate that the products consistently conform to the requirements of the Standard.C4SUPPLIER’S QUALITY SYSTEM Where the manufacturer or supplier can demonstrate an audited and registered quality management system complying with the requirements of the appropriate or stipulated Australian or international Standard for a supplier’s quality system or systems,this may provide the necessary confidence that the specified requirements will be met.The quality assurance requirements need to be agreed between the customer and supplier and should include a quality or inspection and test plan to ensure product conformity.Guidance in determining the appropriate quality management system is given in AS/NZS ISO9000.1and AS/NZS ISO9004.1.21AS4497.1—1997 C5OTHER MEANS OF ASSESSMENT If the above methods are considered inappropriate,determination of compliance with the requirements of this Standard may be assessed by being based on the results of testing coupled with the manufacturer’s guarantee of product conformance.Irrespective of acceptable quality levels(AQLs)or test frequencies,the responsibility remains with the manufacturer or supplier to supply products that conform with the full requirements of the Standard.Thi s page has been l ef t i nt ent i onal l y bl ank.。

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0501功功ɡōnɡɑl 0502加加jiālk 0503劣劣lièitl 0504助助zhùeɡl 0505努努nǔücl 0506劫劫jiéfcln 0507劬劬qúqkl 0508劭劭shàoükl 0509効効xiào uqln 0510劻劻kuānɡɑɡln 0511劾劾héyntl 0512劼劼jiéfkln 0513劲劲jìn cɑl 0514勃勃bófpb 0515勐勐měnɡbll0516勇勇yǒnɡcel 0517勉勉miǎn qkql 0518勍勍qínɡyiln 0519勒勒lèɑfl 0520动动dònɡfcl 0521勖勖xùjhl 0522勘勘kānɑdwl 0523务务wùtl 0524胜胜shènɡetɡ0525劳劳láoɑpl 0527募募mùɑjdl 0528势势shìrüyl 0530勤勤qínɑkɡl 0532勚勚yìɑnml 0533勰勰xiéllln 0534勳勳xūn tɡll 0535劢劢mài dnl 0536励励lìddnl 0537勷勷xiānɡykkl 0538劝劝quàn cl 0539锝锝déqjɡf 0540勹勹bāo qtn 0541勺勺sháo qyi 0542匀匀yún qu 0543勿勿wùqre 0545包包bāo qn 0546匈匈xiōnɡqqb 0547匊匊jūqoi 0548匍匍púqɡey 0549匏匏páo dfnn 0550匐匐fúqɡk 0551勾勾ɡōu qci 0552匕匕bǐxtn0553化化huàwx 0554北北běi ux 0555匙匙chíjɡhx 0556碲碲dìduph 0557匚匚fānɡɑɡn 0558匜匜yíɑbü0559匝匝zāɑmh 0561匠匠jiànɡɑr 0562匡匡kuānɡɑɡd 0563匣匣xiáɑlk 0564匪匪fěiɑdjd 0565汇汇huìiɑn 0566匮匮kuìɑkh 0567匦匦ɡuǐɑlü0570啶啶dìnɡkpɡh 0571匸匸xìɑɡn 0572匹匹pǐɑqü0573匾匾biǎnɑynɑ0574匿匿nìɑɑdk 0575区区qūɑq 0576铥铥diūqtfc 0577十十shífɡh 0578千千qiān tfk 0579廿廿niànɑɡh 0580卅卅sàɡkk 0581升升shēnɡtɑk 0582午午wǔtfj 0583卉卉huìfɑj 0584半半bàn uf 0585卑卑bēi rtfj 0586卒卒zúywwf 0587卓卓zhuóhjj 0588协协xiéfl0589南南nán fm 0590博博bófɡe 0592卜卜bǔhhy 0593卞卞biàn yhu 0594占占zhàn hk 0595卡卡kǎhhu 0596卣卣yǒu hln 0597卦卦ɡuàffhy 0598氡氡dōnɡrntu 0599卩卩dān bnh 0602卯卯mǎo qtbh 0603印印yìn qɡb 0604危危wēi qdb 0606却却quèfcb 0607卵卵luǎn qyt 0608卷卷juǎn udbb 0609卸卸xièrhb 0610卺卺jǐn biɡb 0612卮卮zhīrɡbü0613即即jíücb 0615卿卿qīnɡqtüb 0616胨胨dònɡeɑi 0617厂厂chǎnɡdɡt 0618厄厄èdbü0622厘厘lídjfd 0623厍厍shèdlk 0624厚厚hòu djb 0625厝厝cuòdɑj 0626原原yuán dr 0627厕厕cèdmjk 0628厥厥juédubw 0630厌厌yàn ddi 0631厮厮sīdɑdr0632厉厉lìddn 0633厦厦shàddh 0634胴胴dònɡemɡ0635厶厶sīcny 0637去去qùfcu 0638叁叁sān cdd 0639参参cān cd 0641塅塅duàn fwdc 0642又又yòu ccc 0643叉叉chācyi 0644及及jíey 0645友友yǒu dc 0646反反fǎn rc 0647叔叔shūhic 0648取取qǔbc 0649受受shòu epc 0650叙叙xùwtc 0651叛叛pàn udrc 0652叟叟sǒuüh 0654丛丛cónɡwwɡ0655叠叠diécccɡ0656口口kǒu kkkk 0657古古ɡǔdɡh 0658句句jùqkd 0659另另lìnɡkl 0660叨叨dāo kün 0661叩叩kòu kbh 0662只只zhǐkw 0663叫叫jiào kn 0664召召zhàoükf 0665叭叭bākwy 0666叮叮dīnɡksh 0667叱叱chìkxn0668可可kěsk 0669台台tái ck 0670史史shǐkq 0671右右yòu dk 0672叵叵pǒɑkd 0673叶叶yèkf 0674司司sīnɡk 0675吁吁xūkɡfh 0676吃吃chīktn 0677各各ɡètk 0678合合héwɡk 0679吉吉jífk 0680吊吊diào kmh 0681同同tónɡm 0682名名mínɡqk 0683后后hòu rɡ0684吏吏lìɡkq 0685吐吐tǔkfɡ0686向向xiànɡtm 0687吓吓xiàkɡh 0689君君jūnütkd 0690吝吝lìn ykf 0691吞吞tūnɡdk 0692吟吟yín kwyn 0693吠吠fèi kdy 0694否否fǒuɡik 0695吩吩fēn kwü0696咐咐fùkwf 0697吆吆yāo kxy 0698含含hán wynk 0699吭吭kēnɡkym 0700吮吮shǔn kcq 0701呈呈chénɡkɡ0702吴吴wúkɡd 0703吵吵chǎo ki 0704呐呐nàkmw 0705吸吸xīke 0706吹吹chuīkqw 0707告告ɡào tfkf 0708吻吻wěn kqr 0709吼吼hǒu kbn 0710吾吾wúɡkf 0711呀呀yɑkɑ0712吕吕lǚkk 0713呃呃èkdb 0714呆呆dāi ks 0715咂咂zākɑm 0716呢呢ne knx 0717呦呦yōu kxl 0718呋呋fūkfw 0719周周zhōu mfk 0720咒咒zhòu kkm 0721吧吧bɑkc 0722呱呱ɡuākrc 0724味味wèi kfi 0725呵呵hēksk 0726呶呶náo küc 0727呷呷ɡāklh 0728呻呻shēn kjh 0729呼呼hūkt 0730命命mìnɡwɡkb 0731咀咀jǔkeɡ0732咄咄duōkbm 0733咆咆páo kqn 0734咕咕ɡūkdɡ0735和和hét0736咎咎jiùthk 0737咏咏yǒnɡkyn 0738咋咋zǎkthf 0739咖咖kāklk 0740哎哎āi kɑq 0741咤咤zhàkptɑ0742响响xiǎnɡktm 0743咪咪mīko 0744咧咧liěkɡq 0745咨咨zīuqwk 0746咫咫zhǐnyk 0747咬咬yǎo kuq 0748咯咯ɡēktk 0749咱咱zán kth 0750咳咳hāi kynw 0752咸咸xián dɡk 0754咽咽yān kld 0755哀哀āi yeu 0756品品pǐn kkk 0757哂哂shěn ksɡ0758哄哄hǒnɡkɑw 0759啊啊ākb 0760哇哇wākff 0761哈哈hākwɡ0762哉哉zāi fɑk 0763哪哪nǎkü0764咿咿yīkwüt 0765员员yuán km 0766哥哥ɡēsks 0767唔唔én kɡkɡ0768哦哦òktr 0769哩哩lǐkjf 0770哭哭kūkkdu0771哮哮xiāo kft 0772哲哲zhérrk 0773哺哺bǔkɡe 0774哼哼hēnɡkyb 0775哽哽ɡěnɡkɡj 0776哿哿ɡělksk 0777唁唁yàn kyɡ0778唆唆suōkcw 0780唉唉āi kct 0781唐唐tánɡyüh 0782唇唇chún dfek 0783哨哨shào kie 0784啦啦lākru 0785唏唏xīkqd 0786售售shòu wyk 0787唯唯wéi kwyɡ0788唱唱chànɡkjj 0789唳唳lìkynd 0790唾唾tuòktɡ0791啁啁zhōu kmf 0793啄啄zhuókeyy 0794商商shānɡum 0795问问wèn ukd 0796启启qǐynk 0797啖啖dàn koo 0798啥啥shákwfk 0799啜啜chuòkccc 0800哑哑yǎkɡo 0801唬唬hǔkhɑm 0802啤啤píkrt 0803啡啡fēi kdj 0804啻啻chìupmk 0805啼啼tíku0806喁喁yónɡkjm 0807喀喀kākpt 0808喂喂wèi klɡe 0809喃喃nán kfm 0810善善shàn uduk 0811喆喆zhéfkfk 0812喇喇lākɡk 0813喈喈jiēkxxr 0814喉喉hóu kwn 0815喊喊hǎn kdɡt 0816喏喏nuòkɑdk 0818喋喋diékɑns 0819喑喑yīn kuj 0820喘喘chuǎn kmd 0821喙喙huìkxe 0822唤唤huàn kqm 0823喜喜xǐfku 0824喝喝hēkjq 0825唧唧jīkücb 0826喧喧xuān kp 0827喻喻yùkwɡj 0828丧丧sànɡfue 0829乔乔qiáo tdj 0830单单dān ujfj 0831啾啾jiūkto 0832喹喹kuíkdf 0833嗅嗅xiùkthd 0834吗吗mɑkcɡ0835啬啬sèfulk 0836嗑嗑kēkfcl 0837嗓嗓sǎnɡkcc 0838嗔嗔chēn kfhw 0839呜呜wūkqnɡ0840嗪嗪qín kdwt 0841嗜嗜shìkftj 0842嗟嗟jiēkudɑ0843嗣嗣sìkmɑ0844嗤嗤chīkbhj 0845喔喔wōknɡf 0846喟喟kuìkle 0847哟哟yōkx 0849嗡嗡wēnɡkwc 0850呛呛qiànɡkwb 0851嗉嗉sùkɡxi 0852嗒嗒dākɑwk 0853喽喽lou koü0855叹叹tàn kcy 0856嘈嘈cáo kɡmj 0857嘉嘉jiāfkuk 0858嘏嘏ɡǔdnh 0859嘛嘛mɑky 0860唛唛mài kɡt 0862啧啧zékɡm 0863尝尝chánɡipf 0864嘘嘘xūkhɑɡ0865噻噻sāi kpf 0866嚎嚎háo kyp 0867嘎嘎ɡākdh 0868呕呕ǒu kɑqy 0869嗷嗷áo kɡqt 0870嗽嗽sòu kɡkw 0871嗾嗾sǒu kyt 0872嘬嘬chuài kjb 0873哗哗huákwx 0874哔哔bìkxxf 0875叽叽jīkmn0876啸啸xiào küi 0877嘲嘲cháo kfj 0878嘴嘴zuǐkhx 0879哓哓xiāo kɑt 0880嘶嘶sīkɑd 0881嗥嗥háo krd 0882嘹嘹liáo kdui 0883嘻嘻xīkfk 0884嘿嘿hēi klf 0886噌噌cēnɡkul 0887噍噍jiào kwyo 0888噎噎yēkfp 0889噢噢ōktmd 0891噤噤jìn kssi 0892器器qìkkd 0893噩噩èɡkkk 0894噪噪zào kkks 0895噫噫yīkujn 0896噬噬shìktɑ0897嗳嗳ài kep 0898哙哙kuài kwfc 0899喷喷pēn kfɑ0900噶噶ɡákɑj 0901哝哝nónɡkpe 0902哕哕yuěkmq 0903吨吨dūn kɡb 0904噱噱juékhɑe 0905咛咛nínɡkps 0906嚅嚅rúkfd 0908嚏嚏tìkfph 0909啮啮nièkhwb 0910嚚嚚yín kkɑk 0912冁冁chǎn ujfe0917严严yánɡod 0918咙咙lónɡkdx 0919嘤嘤yīnɡkmm 0920嚼嚼jiáo kel 0921啭啭zhuàn klfy 0922嗫嗫nièkbc 0923嚣嚣xiāo kkdk 0924嚷嚷rǎnɡkyk 0926囊囊nánɡɡkh 0927呓呓yìkɑn 0928嘱嘱zhǔknt 0930叻叻lèkln 0931囗囗wéi lhnɡ0932回回huílkd 0933囚囚qiúlwi 0934四四sìlh 0935囱囱cōnɡtlqi 0936因因yīn ld 0937囤囤dùn lɡb 0938困困kùn ls 0939囫囫húlqr 0940囷囷qūn lti 0941囹囹línɡlwy 0942固固ɡùldd 0943囿囿yòu lde 0944圃圃pǔlɡey 0945圄圄yǔlɡkd 0946圈圈quān lud 0947圉圉yǔlfu 0948国国ɡuól 0950囵囵lún lwxü0951圐圐kūllyü0952圙圙lüèlwdd0953围围wéi lfnh 0954园园yuán lfq 0955圆圆yuán lkmi 0956图图túltu 0957团团tuán lft 0958圜圜huán llɡ0960土土tǔffff 0961在在zài d 0962圩圩wéi fɡf 0963圬圬wūffn 0964圭圭ɡuīfff 0965圮圮pǐfnn 0966地地dìf 0967圻圻qífrh 0968址址zhǐfhɡ0969圾圾jīfe 0970坟坟fén fy 0971均均jūn fqu 0972坊坊fānɡfyn 0973坍坍tān fmyɡ0974坎坎kǎn fqw 0975坏坏huài fɡi 0976坐坐zuòwwf 0977坑坑kēnɡfym 0978坂坂bǎn frc 0979坌坌bèn wüff 0980坡坡pōfhc 0981坤坤kūn fjhh 0982坦坦tǎn fjɡ0983坭坭nífnx 0984坩坩ɡān fɑfɡ0985坷坷kěfsk 0986坼坼chèfry0987垂垂chuítɡɑ0988坪坪pínɡfɡu 0989坫坫diàn fhkɡ0990坰坰shǎnɡfmkɡ0991坳坳ào fx 0992型型xínɡɡɑjf 0993垓垓ɡāi fynw 0994坬坬ɡuàfrcy 0995垠垠yín füe 0996垢垢ɡòu fr 0997垣垣yuán fɡjɡ0998垃垃lāfuɡ0999坯坯pīfɡiɡ1000垛垛duǒfms 1001坨坨tuófpxn 1002埃埃āi fct 1003埋埋mái fjf 1004城城chénɡfd 1005埒埒lièfef 1006垮垮kuǎfdfn 1007埏埏shān fth 1008域域yùfɑkɡ1009埠埠bùfwn 1010垧垧shǎnɡftm 1011埭埭dài füi 1012垡垡fáwɑff 1013执执zhírüy 1014培培péi fuk 1015基基jīɑd 1016堂堂tánɡipkf 1017坚坚jiān jcf 1018堆堆duīfwy 1019垩垩èɡoɡf1020埤埤pífrt 1021埴埴zhíffhɡ1022埵埵duǒftɡf 1023埸埸yìfjq 1024堃堃kūn yyff 1025堙堙yīn fsf 1026堞堞diéfɑn 1027堡堡bǎo wksf 1028堠堠hòu fwnd 1029堤堤dīfjɡh 1030堪堪kān fɑd 1031尧尧yáoɑtɡq 1032报报bào rb 1033埔埔pǔfɡey 1034场场chǎnɡfnrt 1035堵堵dǔfft 1036埝埝niàn fwyn 1037堰堰yàn fɑjü1038垾垾hàn fjfh 1039塍塍chénɡeudf 1040块块kuài fnw 1041茔茔yínɡɑpff 1042塌塌tāfjn 1043塑塑sùubtf 1044塔塔tǎfɑwk 1045墓墓mùɑjdf 1046塚塚zhǒnɡfpey 1048塘塘tánɡfyü1049塞塞sāi pfjf 1050填填tián ffh 1051坞坞wùfqnɡ1052垲垲kǎi fmn 1053埙埙xūn fkmy1054埘埘shífjfy 1055堼堼hènɡffff 1056坝坝bàfmy 1057尘尘chén iff 1058堑堑qiàn lrf 1060塾塾shúybüf 1061塂塂xìnɡfɑwn 1062墀墀chífni 1063墁墁màn fjl 1064境境jìnɡfuj 1065墅墅shùjfcf 1066墉墉yōnɡfyüh 1067垫垫diàn rüyf 1068墄墄cèfdht 1069埫埫shǎnɡfimk 1071坠坠zhuìbwff 1073增增zēnɡfu 1074墟墟xūfhɑɡ1075墨墨mòlfof 1076墩墩dūn fyb 1077堕堕duòbdef 1080塄塄lénɡfly 1081塆塆wān fyox 1082墈墈kàn fɑdl 1083垦垦kěnüef 1084壁壁bìnkuf 1085壅壅yōnɡyxtf 1086坛坛tán ffc 1089壑壑hèhpɡ1090压压yādfy 1091壕壕háo fyp 1093垒垒lěi cccf 1094圹圹kuànɡfyt1096垄垄lǒnɡdxf 1097垆垆lúfhnt 1099壤壤rǎnɡfyk 1101圳圳zhèn fkh 1102士士shìfɡhɡ1103壬壬rén tfd 1104壮壮zhuànɡufɡ1105壹壹yīfpɡ1106壶壶húfpo 1108寿寿shòu dtf 1109壸壸kǔn fpɡɡ1110椴椴duàn swd 1111夂夂dōnɡttn 1112夆夆pánɡtdhj 1113簖簖duàn tonr 1114夊夊suīqyi 1115夏夏xiàdht 1116砘砘dùn dɡb 1118跺跺duòkhm 1119夕夕xīqtny 1120外外wài qh 1121夙夙sùmɡq 1122多多duōqq 1123夜夜yèywt 1124够够ɡòu qkqq 1125梦梦mènɡssq 1126夤夤yín qpɡw 1127夥夥huǒjsq 1128婀婀ēübs 1129大大dàdd 1130夭夭yāo tdi 1131天天tiānɡd 1132太太tài dy1133夫夫fūfw 1134夬夬juénwi 1135央央yānɡmd 1136失失shīrw 1137夯夯bèn dlb 1138夷夷yíɡxw 1139夸夸kuādfn 1140夹夹jiáɡuw 1141奄奄yǎn djn 1142奇奇qídskf 1143奈奈nài dfi 1144奉奉fènɡdwf 1145奎奎kuídfff 1146奏奏zòu dwɡ1147奂奂huàn qmd 1148契契qìdhü1149奔奔bēn dfɑ1150奕奕yìyod 1151奓奓zhàdqqu 1152套套tào ddu 1153奚奚xīexd 1154锇锇éqtrt 1155奘奘zànɡnhdd 1156奠奠diàn usɡd 1158奢奢shēdft 1159奥奥ào tmo 1160奁奁lián dɑq 1161夺夺duódf 1162奖奖jiǎnɡuqd 1163奭奭shìddjj 1164奋奋fèn dlf 1165奀奀ēnɡidu 1166女女nǚüüü1167奴奴núücy 1168奶奶nǎiüe 1169奸奸jiānüfh 1170好好hǎoüb 1171妁妁shuòüqy 1172如如rúük 1173妃妃fēiünn 1174妄妄wànɡynüf 1175妊妊rènütf 1176妒妒dùüynt 1177妍妍yánüɡɑ1178妓妓jìüfc 1179妖妖yāoütd 1180妗妗jìnüwy 1181妙妙miàoüit 1182妆妆zhuānɡuü1183妣妣bǐüxx 1184妤妤yúücbh 1185妥妥tuǒeü1186妨妨fánɡüy 1187妯妯zhóuüm 1188妹妹mèiüfi 1189妻妻qīɡü1190妾妾qièuüf 1191姆姆mǔüx 1192姊姊zǐütnt 1193始始shǐück 1194姗姗shānümm 1195姐姐jiěüeɡ1196姑姑ɡūüd 1197姒姒sìüny 1198姓姓xìnɡütɡ1199妲妲dáüjɡ1200妮妮nīünx 1201委委wěi tü1202姚姚yáoüiq 1203姜姜jiānɡuɡü1204姝姝shūür 1207姣姣jiāoüuq 1209姥姥lǎoüft 1210姨姨yíüɡ1212侄侄zhíwɡcf 1213姬姬jīüɑh 1215姻姻yīnüld 1216娃娃wáüff 1217姿姿zīuqwü1218威威wēi dɡü1219娉娉pīnɡümɡn 1220姮姮hénɡüɡjɡ1222娌娌lǐüjfɡ1223娑娑suōiitü1224娘娘niánɡüyü1225娱娱yúükɡd 1226娜娜nàüüf 1227娟娟juānüke 1228娠娠shēnüdf 1229娣娣dìüux 1230娥娥éütr 1231娩娩miǎnüqk 1232娓娓wěiüntn 1233娼娼chānɡüjj 1234姹姹chàüpt 1235娶娶qǔbcü1236娄娄lóu oü1237婆婆póihcü1238婉婉wǎnüpq1239婊婊biǎoüɡey 1240婕婕jiéüɡü1241婚婚hūnüq 1242婢婢bìürt 1244妇妇fùüü1245婪婪lán ssü1246娅娅yàüɡo 1247她她tāübn 1248妳妳nǐüqiy 1249婼婼ruòüɑdk 1250婷婷tínɡüyp 1251婺婺wùcbtü1252媒媒méiüɑf 1253媚媚mèiünh 1254媛媛yuánüefc 1257娲娲wāükm 1260媖媖yīnɡüɑmd 1261媳媳xíüthn 1262媵媵yìnɡeudü1263媸媸chīübh 1264媪媪ǎoüjl 1265妈妈māüc 1266媾媾ɡòuüfj 1268嫁嫁jiàüpe 1269嫂嫂sǎoüüh 1270嫄嫄yuánüdri 1271嫉嫉jíüut 1273嫌嫌xiánüu 1274媲媲pìütl 1276嫖嫖piáoüsf 1277妪妪yùüɑq 1278嫠嫠lífit 1279嫡嫡díüum1280嫣嫣yānüɡh 1281嫦嫦chánɡüiph 1282嫩嫩nènüɡk 1283嫪嫪làoünwe 1284嫘嫘léiülx 1285嫚嫚mànüjlc 1286嫜嫜zhānɡüujh 1287嫫嫫móüɑjd 1289妫妫ɡuīüyl 1290娆娆ráoüɑt 1291嬉嬉xīüfk 1292婵婵chánüuj 1293娇娇jiāoütdj 1294媭媭xūedmü1295嬖嬖bìnkuü1296嬗嬗shànüylɡ1297嫱嫱qiánɡüfuk 1298嬛嬛huánülɡe 1299嬴嬴yínɡynky 1300嫔嫔pínüpr 1301嬷嬷móüys 1303嬲嬲niǎo llü1305婴婴yīnɡmmü1306婶婶shěnüpj 1307孀孀shuānɡüfs 1309娈娈luán yoü1310妞妞niūünf 1311子子zǐbb 1312孑孑jiébnhɡ1313孔孔kǒnɡbnn 1314孕孕yùn ebf 1315孓孓juébyi 1316字字zìpb1317存存cún dhb 1318孚孚fúebf 1319孛孛bèi fpbf 1320孜孜zībty 1321孝孝xiào ftb 1322孟孟mènɡblf 1323季季jìtb 1324孤孤ɡūbr 1325孥孥núücbf 1326孩孩hái bynw 1327孙孙sūn bi 1328孰孰shúybüy 1329孱孱chán nbb 1330孳孳zīuxxb 1331学学xuéip 1332孺孺rúbfd 1334孪孪luán yob 1335孵孵fūqytb 1336宀宀bǎo pyy 1337宁宁nínɡps 1338它它tāpx 1339宄宄ɡuǐpüb 1341宅宅zhái ptɑ1342宇宇yǔpɡf 1343守守shǒu pf 1344安安ān pü1345宋宋sònɡpsu 1346完完wán pfq 1347宏宏hónɡpdc 1348宓宓mìpntr 1349宕宕dànɡpdf 1350宗宗zōnɡpfi 1351官官ɡuān pn1352宙宙zhòu pm 1353定定dìnɡpɡ1354宛宛wǎn pq 1355宜宜yípeɡ1356客客kèpt 1357宣宣xuān pɡj 1358室室shìpɡc 1359宥宥yòu pdef 1360宦宦huàn pɑh 1361宬宬chénɡpdnt 1362宫宫ɡōnɡpk 1363宰宰zǎi puj 1364害害hài pd 1365宴宴yàn pjü1366宵宵xiāo pi 1367家家jiāpe 1368宸宸chén pdfe 1369容容rónɡpww 1372宿宿sùpwdj 1374寂寂jìph 1376寄寄jìpds 1377寅寅yín pɡm 1378密密mìpnt 1379寇寇kòu pfqc 1381富富fùpɡk 1382寐寐mèi pnhi 1383寒寒hán pfj 1384寓寓yùpjm 1389寞寞mòpɑj 1390察察chápwfi 1391寡寡ɡuǎpde 1392寝寝qǐn puüc 1393寤寤wùpnhk1394寥寥liáo pnw 1395实实shípu 1396寨寨zhài pfjs 1399审审shěn pj 1400写写xiěpɡn 1401宽宽kuān pɑ1402寮寮liáo pdu 1403寰寰huán plɡ1404宠宠chǒnɡpdx 1405宝宝bǎo pɡy 1406宧宧yípɑhh 1407寸寸cùn fɡhy 1408寺寺sìff 1409封封fēnɡfffy 1410射射shètmdf 1411尅尅kèdqfi 1412将将jiānɡuqf 1413专专zhuān fny 1414尉尉wèi nfif 1415尊尊zūn usɡ1416寻寻xúnüf 1417对对duìcf 1418导导dǎo nf 1419蒽蒽ēnɑldn 1420小小xiǎo ih 1421少少shǎo it 1422尔尔ěr qiu 1423尖尖jiān id 1424尚尚shànɡimkf 1427尕尕ɡǎeiu 1428尢尢yóu dnü1429尤尤yóu dnü1431尪尪wānɡdnɡd1432就就jiùyi 1433尰尰zhǒnɡdntf 1434尴尴ɡān dnjl 1435尬尬ɡàdnw 1436铒铒ěr qbɡ1437尸尸shīnnɡt 1438尹尹yǐnüte 1439尺尺chǐnyi 1440尻尻kāo nüü1441尼尼nínx 1442尾尾wěi ntf 1443尿尿niào nii 1444局局júnnk 1445屁屁pìnxx 1446居居jūnd 1447届届jiènm 1448屈屈qūnbm 1449屉屉tìnɑn 1450屋屋wūnɡc 1452屎屎shǐnoi 1453屐屐jīntfc 1454屑屑xiènied 1455展展zhǎn nɑe 1456屏屏pínɡnuɑ1457屝屝fèi ndjd 1458屠屠túnft 1459屡屡lǚno 1460屣屣xǐnthh 1461层层cénɡnfc 1462履履lǚntt 1464屦屦jùntoü1466属属shǔntk 1468砩砩fúdxj1470屯屯túnɡb 1471岳岳yuèrɡm 1472山山shān mmm 1473屹屹yìmtnn 1474屺屺qǐmnn 1475峁峁mǎo mqt 1476岌岌jímeyu 1477岐岐qímfc 1478岑岑cén mwyn 1479岔岔chàwümj 1480峿峿yǔmɡkɡ1481冈冈ɡānɡmqi 1482岢岢kěmsk 1483岈岈yámɑh 1484岩岩yán mdf 1485岫岫xiùmmɡ1486岱岱dài wɑmj 1487岵岵hùmdɡ1488岷岷mín mnɑ1489岸岸àn mdfj 1490岣岣ɡǒu mqk 1491峒峒dònɡmmɡk 1492峙峙zhìmff 1493峋峋xún mqjɡ1494峨峨émtr 1495峭峭qiào mi 1496峰峰fēnɡmtd 1497岛岛dǎo qynm 1498峻峻jùn mcw 1499峡峡xiámɡu 1500峓峓yímɡxw 1501岘岘xiàn mmqn1502峪峪yùmwwk 1503崃崃lái mɡo 1504崇崇chónɡmpf 1505崎崎qímds 1506岽岽dōnɡmɑi 1507崑崑kūn mjxx 1508崔崔cuīmwy 1509崖崖yámdff 1510崙崙lún mwɡɑ1511岗岗ɡǎnɡmmq 1512崛崛juémnbm 1513峥峥zhēnɡmqü1514崩崩bēnɡmee 1515崚崚línɡmfwt 1516崧崧sōnɡmsw 1517崦崦yān mdj 1518嵇嵇jītdnm 1519崆崆kōnɡmpw 1520嵋嵋méi mnh 1521嵫嵫zīmux 1522嵊嵊shènɡmtu 1523嵌嵌qiàn mɑf 1524峧峧jiāo muqy 1525嵎嵎yúmjmy 1526岚岚lán mmqu 1527崀崀nǎnɡmyüe1529嵩嵩sōnɡmym 1530嵝嵝lǒu moü1531嵬嵬wéi mrq 1532嵯嵯cuómud 1533崌崌jūmndɡ1534嶂嶂zhànɡmuj1535崭崭zhǎn ml 1536岖岖qūmɑq 1537嶒嶒zhēnɡmulj 1538嵚嵚qīn mqqw 1539嵘嵘rónɡmɑps 1540峤峤qiáo mtdj 1541崤崤xiáo mqde 1542峄峄yìmcf 1543嶙嶙lín mo 1544嶷嶷yímx 1545岭岭lǐnɡmwyc 1546屿屿yǔmɡn 1547崾崾yǎo msü1548巉巉chán mqky 1549嵛嵛yúmwɡ1550巍巍wēi mtü1551峦峦luán yom 1552嶅嶅àoɡqtm 1553巅巅diān mfh 1554巖巖yán mkkt 1555崂崂láo mɑp 1556巛巛chuānünnn 1557川川chuān kthh 1558州州zhōu ytyh 1559巡巡xúnüp 1560巢巢cháoüjs 1561镄镄fèi qxj 1562工工ɡōnɡɑ1563左左zuǒdɑ1564巧巧qiǎoɑɡnn 1565巨巨jùɑnd 1566巫巫wūɑww 1567差差chàudɑ1568酚酚fēn sɡw 1569己己jǐnnɡ1570巳巳sìnnɡn 1571已已yǐnnnn 1572巴巴bācnh 1574巷巷xiànɡɑwn 1575巽巽xùn nnɑ1576钆钆ɡáqnn 1577巾巾jīn mhk 1578币币bìtmh 1579市市shìymhj 1580布布bùdmh 1581帆帆fān mhm 1582帋帋zhǐqɑmh 1583帑帑tǎnɡücm 1584帕帕pàmhr 1585希希xīqdm 1586帖帖tiēmhh 1587帗帗fúmhdc 1588帘帘lián pwm 1589帙帙zhìmhrw 1590帚帚zhǒuüpm 1591帛帛bórmh 1592帔帔pèi mhhc 1593帝帝dìup 1594帡帡pínɡmhuɑ1596帅帅shuài jmh 1597师师shījɡm 1598席席xíyɑm 1599帨帨shuìmhuq 1600帐帐zhànɡmht 1601带带dàiɡkp 1602帷帷wéi mhw1603常常chánɡipkh 1604帽帽mào mhj 1605帏帏wéi mhf 1606幄幄wòmhnf 1607幅幅fúmhɡ1608帧帧zhēn mhhm 1610幌幌huǎnɡmhjq 1611幔幔màn mhjc 1612幕幕mùɑjdh 1613帼帼ɡuómhl 1614帻帻zémhɡm 1615帜帜zhìmhkw 1616幡幡fān mhtl 1617幢幢zhuànɡmhu 1619幪幪měnɡmhɑe 1620帮帮bānɡdt 1621帱帱dào mhd 1625幛幛zhànɡmhuj 1626干干ɡān fɡɡh 1627平平pínɡɡu 1628年年nián rh 1629并并bìnɡuɑ1630幸幸xìnɡfuf 1632矸矸ɡān dfh 1633幺幺yāo xnny 1634幻幻huàn xnn 1635幼幼yòu xln 1636幽幽yōu xxm 1638酐酐ɡān sɡfh 1639广广ɡuǎnɡyyɡt 1640庀庀pǐyxü1641庹庹tuǒyɑny 1642庇庇bìyxx1643床床chuánɡysi 1644庋庋ɡuǐyfc 1645序序xùycb 1646底底dǐyqɑ1647庖庖páo yqn 1648店店diàn yhk 1649庚庚ɡēnɡyüw 1650府府fǔywf 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BUS IC DC/DC CONVERTER MOTOR DRIVER IC RIPPLE COUNTER80BLOCK DIAGRAMÿ Co-integrated pressure sensorFEATURESÿSupply voltage VDD 5VÿAmplified, calibrated, fully signal conditionedoutput of 4.0 VDC FS span (0.5 to 4.5V signal)ÿOutput ratiometric with supply voltageÿDigital Signal Processor for correction algorithmsÿMulti-order temperature compensation for gainand offsetÿFor gauge, differential, and absolute applicationsÿAdjustable output clampsÿProgrammable output filterÿEEPROM memory for End-of-line calibrationÿ– 40°C to + 125°C operating temperatureÿAvailable packages:ÿASIC plus: SO16w body with nozzleÿ bare dieÿ customer specificAPPLICATIONÿAutomotive pressure sensing(MAP, tire pressure, oil, fuel)ÿBarometric measurementÿMedical instrumentationÿIndustrialÿHVACDESCRIPTIONThe IC of OEM integrated pressure sensor combines state-of-the-art pressure sensor technology with signal conditioning toproduce a fully signal-conditioned, amplifi ed, temperature com-pensated sensor. The sensor utilizes a digital signal processor toallow multiorder linear correction to achieve increased accuracyover conventional amplifi ed pressure systems. The device is a co-integrated die. It is also available as an IC without the sensor andis therefore suitable for the use of a precision signal processor forseparate sensors.The system uses an on-chip EEPROM to store the calibration data.This allows the device to be calibrated end-of-line and so to com-pensate for packaging stress and/or parametric changes due tothe addition of protective gel. Sensor ID information can also bestored in the EEPROM.The chip is currently confi gured for operating pressure rangesfrom 350mbar FS up to 10bar (5PSI to 145PSI FS). For pressure rang-es below 350mbar (5PSI), the IC interfaces with an off-chip sensor.The range is extendable above 10bar.元器件交易网。

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BL67-PG-DPD1221B20018076C4312 BL67-GW-EN-IPD1121A2001 棕榈按钮手动阀- 11系列 8076C4311 BL67-GW-DND1123A2001 8077B6312 BL67-GW-EN1123A2001 8077C3322 BL67-GW-EN-PN 1121A2001 8077C3341W BL67-PG-EN 1223B1MBR 按钮手动阀- 12系列 8077B3904W BL67-PG-EN-IP D1223B2MBG 8077C4321 3900A1052-1Z 阀门/歧管组件 D1223B2FPG8077B3904Z 3900A0713-1W 1223B1FPG 8076C4342W 3900A0713-1Z D1223B1MBR8076B63213900A1052-3Z D1223B1FPG8077B6332W 3900A1052-1W 1223B1MBG 8077B6311 3900A1052-2Z 1223B2FPR 8077A4904Z 3900A1052-3W D1223B2FPR 8077C4351Z 3900A1052-4W 1223B2MBR 8077C4352Z 3900A0713-2Z D1223B1FPR 8077C4352W 3900A1052-2W 1223B1FPR 8076C3342Z 3900A1052-4Z 1223B2FPG 8077B6352Z 3900A0713-2W 1223B2MBG 8077C3312 W1413A1408Z 微型阀- W14系列 D1223B2MBR8077B6341W W1413A1409W D1223B1MBG 8077B6342W W1413A1408W D1223B1SLB选择开关阀- 12系列8077C3341Z W1413A1409Z 1223B2SLB8077C4312 D1223B2SLB8077C4332W 1223B1SLB 8077C4311 1123A2002 拨动手柄手动阀- 11系列8076C3331Z D1123A2002 8077C3351W D1121A2002 8077C3352Z 1121A2002 8076C4351W D3626A2003 杠杆手动阀- 36系列8077C3321 3626A2004 8076C4341Z 3623A2004 8077C3332W 3626A20038076C4321 D3623A20038076B6331W D3623A2004 8076C3311 D3626A2004 8076B6351Z 3623A2003 8076B6352W D3126A3013 重型单手柄手动阀- 31系列 8076C3322 3126A4014 8076B6341Z 3126A4013 8076B6351W D3126A4014 8076C3321 D3126A4010 8076C3332Z D3126A4012 8076C3342W 3126A3014 8076C3341Z 3126A3012 8076C4331Z 3126A6010 8076C4322 D3126A4013 8077B6322 D3126A3009 8077B6332Z D3126A4009 8077C3352W D3126A7010 8077C3342WD3126A30078076B6331Z D3126A5007 8077B6342Z 3126A5007 8076C3331W 3126A5010 8076B6361W 3126A3007 8076B6362W 3126A3010 8076C3332W 3126A4010 8076B6342W 3126A7010 8076B6332Z D3126A6007 8076C3352W 3126A3009 8076B6352Z D3126A5010 8076C3341W D3126A7007 8077B6361W D3126A4007 8077B3910Z D3126A6010 8077C3331Z 3126A6007 8077B6351W 3126A4007 8077C4331W D3126A3010 8077C3351Z 3126A7007 8077B3910W 3126A3013 8077C4341W 3126A4009 8077C4341Z 3126A4012 8077B6321 D3126A3012 8077B6331Z D3126A3014 8077B6341Z8077B6331W8077B6351Z8077C3342Z8077C4342W8077C4342Z8076C3362W8076C3352Z8076C4332W8076C4351Z8077C3362W8077C43228076C4342Z8076B63228077B6352W8077C3332Z8076C4332Z8076C4341W8077C4351W 8077C3311 8077C3331W 8077B6362W 8077C4361W 8076C3361W 8076C4361W 8076C4362W 8077A4907Z 8077A4907W 8077C3361W 8077C4362W 8076B6311 8076B6341W 8076B6312 8076B6332W 8076C3312 8076C3351Z 8476B6331Z SAE 提升阀- 84系列 8476B6342Z 8476B6322 8476C4342W 8476C4342Z 8476C4322 8476C3331W 8476B6341Z 8476C3351Z 8476C33128476B6351W 8476B6341W 8476B6352Z 8476B6321 8476B6361 8476C3341W 8476C3341Z 8476C3311 8476C3321 8476C4351Z 8476C3352W 8476C4331Z8476C4321 8476C3342W 8476B6352W 8476B6362 8476C3332W 8476B6351Z 8476C4331W 8476C3362 8476C3322 8476C4311 8476C3342Z 8476C3352Z 8476C4361 8476C4352W 8476C4332W 8476C4362 8476C3331Z 8476B6311 8476B6312 8476C3351W 8476B6331W 8476C3361 8476C4332Z 8476C4341Z 8476C4341W 8476C4351W 8476C4312 8476C4352Z 8476B6342W 8476B6332Z 8476B6332W 8476C3332ZD3643A2001踏板和脚踏板的手动阀- 36系列CP10DB97116Z阀门和阀门歧管-CP系列1613B2020W紧凑型提升阀- 16系列D3646A2002 CP14DB37118W 1614B2020Z D3643A2002 CP14NB47112W 1614B1020Z 3646A2002 CP16DB57113Z 1614B2322Z 3643A2002 CP16NB57113W D1613B2020W 3646A2001 CP14DB67117W 1616C2020ZD3646A2001 CP14DB67115W 1616C2020W 3643A2001 CP14DB67118WD1616C2020W RM4F210-08LG 手册脚踏阀- RM 系列CP16DB57116W 1614B2322W RM4F210-08G CP16NB57119ZD1614B2322W D1131A2002 机械凸轮滚子和柱塞阀- 11系列CP16DB67113W 1614B1020W 1133A2003 CP16DB67118W D1614B1020W D1131A2001 CP18NB77112W 1613B1020W D1133A2002 CP20NB97112W 1613B1020Z D1133A2003 CP20DB97115Z D1616C2020Z 1131A2003 CP24NB37112W D1614B1020Z 1131A2001 CP24NB37115Z D1613B2020Z 1131A2002 CP24NB37114W D1614B2020Z D1133A2001 CP24NB37114Z D1613B1020W D1131A2003 CP24DB67113W D1613B1020Z 1133A2002 CP24DB57116W D1614B2322Z 1133A2001 CP24DB57118W 1613B2020Z 2025A1900 吊坠控制手动阀 CP24DB67116W 1614B2020W 2025A2904 CP26DB57112Z D1614B2020W 2025A2901 CP26NB57114ZD9576K2901Z 那慕尔阀门系列3900A0379 CP26NB57114W 3476C1904W 3900A0378 CP26DB57113W3476C1904Z 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安装和操作手册Pressotronik PT77BC130003, 10/2011 Art. Nr. 90 32 052Bühler Technologies GmbH, Harkortstr. 29, D-40880 RatingenTel. +49 (0) 21 02 / 49 89-0, Fax. +49 (0) 21 02 / 49 89-20Internet: E-mail: fluidcontrol@1请在安装和使用前仔细阅读此手册。

敬请特别注意所有安全守则，以避免不必要的意外伤害事故。

Bühler Technologies GmbH /德国比勒科技有限责任公司对由不当操作以及在未授权情况下擅自改动机器设备所引起的后果不承担任何责任。

目录页码1 简介 (4)1.1 适用范围 (5)2 重要提示 (5)2.1 安装说明定义 (5)3 安装 (7)3.1 安装压力传感器-直立或倒立 (8)4 操作 (9)4.1 LED状态显示 (9)4.2 通用按键功能 (10)4.3 键盘锁激活 (11)4.4 菜单结构总览 (11)4.5 更改通用设置 (12)4.5.1 显示调转180度 (12)4.5.2 设置压力表示单位 (12)4.5.3 设置最大压力 (12)4.5.4 设置显示刷新率 (13)4.5.5 恢复出厂设置 (13)4.6 开关量输出 (14)4.6.1 开关量输出1: 开关量性质的定义 (15)4.6.2 开关量输出x: 上限（设置点） (16)4.6.3 开关量输出x: 下限（重置点） (16)4.6.4 开关量输出x: 设置点延时 (16)4.6.5 开关量输出x：重置点延时 (17)4.6.6 开关量输出x：测试开关量输出 (17)4.6.7 更改LED的开关量功能 (18)4.7 模拟输出 (19)4.7.1 模拟输出x: 设置上限值 (19)4.7.2 模拟量输出x: 设置下限值 (19)4.7.3 模拟量输出x: 设置输出特征 (19)4.7.4 模拟量输出 x: 测试模拟量输出 (20)4.8 诊断工具 (20)4.8.1 开启日志 (21)4.8.2 最大和最小压力 (21)4.8.3 用于记录数据的开关量输出设置 (22)4.8.4 记录最小/最大压力的延时 (22)5 维护和报废 (23)5.1 故障排除 (23)5.2 报废处理 (23)6 故障排除 (24)2 BC130003, 10/2011 Art. Nr. 90 32 052BC130003, 10/2011 Art. Nr. 90 32 052 37 所附文档 ............................................................................................................................... 24 8附录...................................................................................................................................... 25 8.1 压力变送器技术参数 ........................................................................................................................ 25 8.2 显示和控制单元技术参数................................................................................................................. 26 8.3 标准针脚分布图 Pressotronik 770 ................................................................................................... 27 8.4 标准针脚分布图 Pressotronik 771 ................................................................................................... 28 8.5 尺寸图.............................................................................................................................................. 29 8.6 实际设置 .......................................................................................................................................... 30 8.7 符合性声明 ...................................................................................................................................... 31 8.8 菜单结构总览 .. (32)4 BC130003, 10/2011 Art. Nr. 90 32 0521 简介本手册对Pressotronik PT 770-xx 和 PT 771-xx 压力控制器进行了说明描述。

Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.Document Number: MC33977Rev. 2.0, 1/2007Freescale Semiconductor Technical Data© Freescale Semiconductor, Inc., 2007. All rights reserved.Single Gauge DriverThe 33977 is a Serial Peripheral Interface (SPI) Controlled, stepper motor gauge driver Integrated Circuit (IC). This monolithic IC consists of a dual H-Bridge coil driver and its associated control logic. The H-Bridge drivers are used to automatically control the speed, direction, and magnitude of current through the coils of a two-phaseinstrumentation stepper motor, similar to an MMT-licensed AFIC 6405 of Switec MS-X156.xxx motor.The 33977 is ideal for use in instrumentation systems requiring distributed and flexible stepper motor gauge driving. The device also eases the transition to stepper motors from air core motors by emulating the damped air core pointer movement. Features •MMT-Licensed Two-Phase Stepper Motor Compatible •Switec MS-X15.xxx Stepper Motor Compatible •Minimal Processor Overhead Required•Fully Integrated Pointer Movement and Position State Machine with Air Core Movement Emulation•4096 Possible Steady State Pointer Positions •340° Maximum Pointer Sweep •Maximum Acceleration of 4500°/s 2•Maximum Pointer Velocity of 400°/s•Analog Microstepping (12 Steps/Degrees of Pointer Movement)•Pointer Calibration and Return to Zero (RTZ)•Controlled via 16-Bit SPI Messages •Internal Clock Capable of Calibration •Low Sleep Mode Current•Pb-Free Packaging Designated by suffix code EGFigure 1. 33977 Simplified Application DiagramORDERING INFORMATIONDevice Temperature Range (T A )PackageMC33977DW/R2- 40°C to 125°C24 SOICWMCZ33977EG/R233977SINGLE GAUGE DRIVERAnalog Integrated Circuit Device Data33977INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAMFigure 2. 33977 Simplified Internal Block DiagramH-BRIDGE COS+INTERNAL VPWRVDDCOSCOS-REGULATORLOGICSPIILIMOVERTEMPERATUREAND CONTROLSINOSCILLATORDETECTUNDER -ANDOVERVOLTAGE DETECTCS SCLK SO SIRSTRTZSIN+SIN-GND (8)MULTIPLEXERSIGMA-DELTAADCAGNDSTATE MACHINEVDDAnalog Integrated Circuit Device Data 33977PIN CONNECTIONSPIN CONNECTIONSFigure 3. 33977 Pin ConnectionsTable 1. 33977 Pin DefinitionsA functional description of each pin can be found in the Functional Pin Description section beginning onpage 10.PinPin Name Pin Function Formal Name Definition1234(MS Motor Pin #)COS+ (MS #4)COS- (MS #3)SIN+ (MS #1)SIN- (MS #2)OutputH-Bridge Outputs 0Each pin is the output of a half-bridge, designed to source or sink current.5 to 8, 17 to 20GND N/A Ground Ground pins9CS Input Chip Select This pin is connected to a chip select output of a Large Scale Integration (LSI) Master IC and controls which device is addressed.10SCLK Input Serial Clock This pin is connected to the SCLK pin of the master device and acts as a bit clock for the SPI port.11SOOutput Serial Output This pin is connected to the SPI Serial Data Input pin of the Master device or to the SI pin of the next device in a daisy chain.12SIInput Serial Input This pin is connected to the SPI Serial Data Output pin of the Master device from which it receives output command data.13RTZ Multiplexed Output Return to ZeroThis is a multiplexed output pin for the non-driven coil, during a Return to Zero (RTZ) event.14VDD Input Voltage This SPI and logic power supply input will work with 5.0 V supplies. 15RSTInputResetThis pin is connected to the Master and is used to reset the device, or place it into a sleep state by driving it to Logic [1]. When this pin is driven to Logic [0], all internal logic is forced to the default state. This input has an internal active pull-up. 16VPWRInput Battery Voltage Power supply21, 22, 23, 24NC–No ConnectThese pins are not connected to any internal circuitry, or any other pin, and may be connected to the board where convenient.NC NC NC NC GND GND GND GND VPWR RST VDD RTZCOS +COS -SIN+SIN-GND GND GND GND CS SCLK SO SIAnalog Integrated Circuit Device Data33977ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 2. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingsSymbolValueUnitELECTRICAL RATINGS Power Supply Voltage Steady-State V PWRSS-0.3 to 41VInput Pin Voltage (1)V IN -0.3 to 7.0V SIN± COSI± Continuous Current Per Output (2)I OUTMAX 40mA ESD Voltage (3)Human Body Model (HBM) Machine Model (MM)Charge Device Model (CDM)V ESD±2000 ±2000±200V THERMAL RATINGS Operating Temperature Ambient JunctionT A T J -40 to 125-40 to 150°CStorage Temperature T STG-55 to 150°C Thermal Resistance Junction-to-Ambient Junction-to-LeadR ΘJA R ΘJL 6020°C/W Peak Package Reflow Temperature During Reflow (4), (5)T PPRTNote 5°CNotes1.Exceeding voltage limits on Input pins may cause permanent damage to the device.2.Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperaturewill require maximum output current computation using package thermal resistances.3.ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, R ZAP = 1500 Ω), the Machine Model (MM)(C ZAP = 200 pF, R ZAP = 0 Ω), and the Charge Device Model (CDM).4.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.5.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Analog Integrated Circuit Device Data 33977ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 3. Static Electrical CharacteristicsCharacteristics noted under conditions 4.75 V < VDD < 5.25 V, and - 40°C < TA < 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitPOWER INPUT (VDD)Battery Supply Voltage Range Fully Operational Limited Operation (6),(7)V PWR6.54.0–2626VV PWR Supply CurrentGauge Outputs ON, No Output Loads I PWR–4.06.0mAVPWR Supply Current (All Outputs Disabled)Reset = Logic [0], V DD = 5.0 V Reset = Logic [0], V DD = 0 V I PWRSLP1I PWRSLP2––42156025µAOvervoltage Detection Level (8)V PWROV 263238V Undervoltage Detection Level (9)V PWRUV 5.0 5.6 6.2V Logic Supply Voltage Range (5.0 V Nominal Supply)V DD 4.5 5.0 5.5V Under V DD Logic Reset V DDUV––4.5VVDD Supply Current Sleep: Reset Logic [0]Outputs EnabledI DDOFF I DDON––401.0651.8µV mAPOWER OUTPUT (SIN-, SIN+, COS-, COS+)Microstep Output (Measured Across Coil Outputs)SIN± (COS±) (Refer to Pin Definitions onpage 3)R OUT = 200 Ω, PE6 = 0VSteps Pin Definitions 6, 18, 0, 125, 7, 17, 19 1, 11, 13, 234, 8, 16, 20 2, 10, 14, 223, 9, 15, 21 3, 9, 15, 212, 10, 14, 22 5, 7, 17, 191, 11, 13, 23 5, 7, 17, 190, 126, 18V ST6V ST5V ST4V ST3V ST2V ST1V ST0 4.820.94 V ST60.84 V ST60.68 V ST60.47 V ST60.23 V ST60.15.30.97 V ST60.87 V ST60.71 V ST60.50 V ST60.26 V ST60.06.01.0 V ST60.96 V ST60.8 V ST60.57 V ST60.31 V ST60.1Full Step Active Output (Measured Across Coil Outputs) (10)SIN± (COS±), Steps 1,3 (Pin Definitions 0 and 2)V FS4.95.36.0V Notes6.Outputs and logic remain active; however, the larger coil voltage levels may be clipped. The reduction in drive voltage may result in aloss of position control.7.The logic will reset at some level below the specified Limited Operational minimum.8.Outputs will disable and must be re-enabled via the PECCR command.9.Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.10.See Figure 7.Analog Integrated Circuit Device Data33977ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (SIN-, SIN+, COS-, COS+) (Continued)Microstep Full Step Output (Measured from Coil Low Side to Ground)SIN± (COS±) I OUT = 30 mA V LS0.00.10.3VOutput Flyback Clamp (11)V FB –V ST6 + 0.5V ST6 + 1.0V Output Current Limit (Output - V ST6)I LIM 40100170mA Overtemperature Shutdown (12) T SD 155–180°C Overtemperature Hysteresis (12)T HYST 8.0–16°C CONTROL I/O (SI, SCLK, CS, RST, SO)Input Logic High Voltage (12)V IH 2.0––V Input Logic Low Voltage (12)V IL ––0.8V Input Logic Voltage Hysteresis (12)V INHYST –100–mV Input Logic Pull-Down Current (SI, SCLK)I DWN 3.0–20µA Input Logic Pull-Up Current (CS, RST)I UP 5.0–20µA SO High State Output Voltage (I OH = 1.0 mA)V SOH 0.8 V DD––V SO Low State Output Voltage (I OL = 1.6 mA)V SOL –0.20.4V SO Tri-State Leakage Current (CS = 3.5 V)I SOLK -5.00.0 5.0µA Input Capacitance (13)C IN – 4.012pF SO Tri-State Capacitance (13)C SO––20pFANALOG TO DIGITAL CONVERTER (RTZ ACCUMULATOR COUNT)ADC Gain (12), (14)G ADC100188270Counts/V/msNotes 11.Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.12.This parameter is guaranteed by design; however, it is not production tested.13.Capacitance not measured. This parameter is guaranteed by design; however, it is not production tested. 14.Reference RTZ Accumulator (Typical) on page 30Table 3. Static Electrical Characteristics (continued)Characteristics noted under conditions 4.75 V < VDD < 5.25 V, and - 40°C < TA < 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitAnalog Integrated Circuit Device Data 33977ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTable 4. Dynamic Electrical CharacteristicsCharacteristics noted under conditions 4.75 V < VDD < 5.25 V, and - 40°C < TA < 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitPOWER OUTPUT AND CLOCK TIMINGS (SIN+, SIN-, COS+, COS-) CS SIN± (COS±) Output Turn ON Delay Time (Time from Rising CS Enabling Outputs to Steady State Coil Voltages and Currents)(15)t DLYON––1.0msSIN± (COS±) Output Turn OFF Delay Time (Time from Rising CS Disables Outputs to Steady State Coil Voltages and Currents) (15)t DLYOFF–– 1.0msUncalibrated Oscillator Cycle Time t CLU 0.651.01.7µs Calibrated Oscillator Cycle TimeCalibration Pulse = 8.0 µs, PECCR D4 = Logic [0]Calibration Pulse = 8.0 µs, PECCR D4 = Logic [1]t CLC1.00.91.11.0 1.21.1µsMaximum Pointer Speed (16) V MAX ––400°/s Maximum Pointer Acceleration (16)A MAX––4500°/s 2SPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) (17)Recommended Frequency of SPI Operationf SPI – 1.0 2.0MHz Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (18)t LEAD 167––ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (18)t LAG 167––ns SI to Falling Edge of SCLK (Required Setup Time) (18)t SISU –2583ns Falling Edge of SCLK to SI (Required Hold Time) (18)t SIHOLD –2583ns SO Rise Time C L = 200 pF t RSO–2550nsSO Fall Time C L = 200 pFt FSO–2550nsSI, CS, SCLK, Incoming Signal Rise Time (19)t RSI ––50ns SI, CS, SCLK, Incoming Signal Fall Time (19)t FIS ––50ns Falling Edge of RST to Rising Edge of RST (Required Setup Time) (18)t W RST –– 3.0µs Rising Edge of CS to Falling Edge of CS (Required Setup Time) (18), (20)t CS –– 5.0µs Falling Edge of RST to Rising Edge of CS (Required Setup Time) (18)t EN––5.0µsNotes15.Maximum specified time for the 33977 is the minimum guaranteed time needed from the microcontroller.16.The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideallycalibrated clock frequency of 1.0 MHz. These are not 100 percent tested.17.The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specifiedtemperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall be fully functional for slower clock speeds. Reference Figure 4 and 5.18.The required setup times specified for the 33977 are the minimum time needed from the microcontroller to guarantee correct operation. 19.Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 20.The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.Analog Integrated Circuit Device Data33977ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSSPI INTERFACE TIMING (CS, SCLK, SO, SI, RST) ‘ (CONTINUED)Time from Falling Edge of CS to SO Low Impedance (22)t SOEN ––145ns Time from Falling Edge of CS to SO High Impedance (23)t SODIS –1.34.0µs Time from Rising Edge of SCLK to SO Data Valid (24)0.2 V DD = SO = 0.8 V DD , C L = 200 pFt VALID–90150nsNotes21.The 33977 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specifiedtemperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 33 ns. The device shall be fully functional for slower clock speeds.22.Time required for output status data to be terminated at SO 1.0 k Ω load on SO.23.Time required for output status data to be available for use at SO 1.0 k Ω load on SO.24.Time required to obtain valid data out from SO following the rise of SCLK.Table 4. Dynamic Electrical Characteristics (continued)Characteristics noted under conditions 4.75 V < VDD < 5.25 V, and - 40°C < TA < 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitAnalog Integrated Circuit Device Data 33977ELECTRICAL CHARACTERISTICSTIMING DIAGRAMSTIMING DIAGRAMSFigure 4. Input Timing Switching CharacteristicsFigure 5. Valid Data Delay Time and Valid Time WaveformstWRSTRST0.2 V DDV INCSSCLKSI0.7 V DD0.7 V DDt LEAD t CSt LAG0.7 V DD 0.2 V DDt RSIV ILV IH V ILV IH t FISt SISUt SI(HOLD)0.7 V DD 0.2 V DDValidDon’t CareValidDon’t CareDon’t Caret RSIt FISSCLK50%1.0VV OLV OH3.5VV OLV OHV OLV OHt SO(DIS)0.2 V DDt RSOt RSO t VALIDt SO(EN)0.7 V DD0.2 V DD0.7 V DDLow-to-HighHigh-to-LowSOSOAnalog Integrated Circuit Device Data33977FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTIONFUNCTIONAL DESCRIPTIONINTRODUCTIONThis 33977 is a single-packaged, Serial PeripheralINterface (SPI) controlled, single stepper motor gauge driver integrated circuit (IC). This monolithic stepper IC consists of [deleted two per D. Mortensen] a dual output H-Bridge coil driver [deleted plural s for accurate tense] and theassociated control logic. The dual H-Bridge driver is used to automatically control the speed, direction, and magnitude of current through the coils of a two-phase instrumentation stepper motor, similar to an MMT-licensed AFIC 6405 of Switec MS-X 156.xxx motor.FUNCTIONAL PIN DESCRIPTIONCOSINE POSITIVE (COS0+)The H-Bridge pins linearly drive the sine and cosine coils of a stepper motor, providing four-quadrant operation.COSINE NEGATIVE (COS0-)The H-Bridge pins linearly drive the sine and cosine coils of a stepper motor, providing four-quadrant operation.SINE POSITIVE (SIN+)The H-Bridge pins linearly drive the sine and cosine coils of a stepper motor, providing four-quadrant operation.SINE NEGATIVE (SIN-)The H-Bridge pins linearly drive the sine and cosine coils of a stepper motor, providing four-quadrant operation.GROUND (GND)Ground pins.CHIP SELECT (CS)The pin enables communication with the master device. When this pin is in a logic [0] state, the 33977 is capable of transferring information to, and receiving information from, the master. The 33977 latches data in from the Input Shift registers to the addressed registers on the rising edge of CS.The output driver on the SO pin is enabled when CS is logic [0]. When CS is logic high, signals at the SCLK and SI pins are ignored and the SO pin is tri-stated (highimpedance). CS will only be transitioned from a logic [1] state to a logic [0] state when SCLK is logic [0]. CS has an internal pull-up (I UP ) connected to the pin, as specified in the section of the Static Electrical Characteristics Table.SERIAL CLOCK (SCLK)SCLK clocks the Internal Shift registers of the 33977device. The SI pin accepts data into the Input Shift register on the falling edge of the SCLK signal, while the Serial Output pin (SO) shifts data information out of the SO Line Driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic [0] state whenever the CS makes any transition.SCLK has an internal pull down (l DWN ), as specified in the section of the Static Electrical Characteristics Table. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). Refer to the data transfer Timing Diagrams on page 9.SERIAL OUTPUT (SO)The SO data pin is a tri-stateable output from the Shift register. The Status register bits are the first 16 bits shifted out. Those bits are followed by the message bits clocked in FIFO, when the device is in a daisy chain connection or being sent words that are multiples of 16 bits. Data is shifted on the rising edge of the SCLK signal. The SO pin will remain in a high impedance state until the CS pin is put into a logic low state.SERIAL INPUT (SI)The SI pin is the input of the SPI. Serial input information is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, beginning with the mostsignificant bit (MSB). Messages that are not multiples of 16 bits (e.g., daisy chained device messages) are ignored. After transmitting a 16-bit word, the CS pin must be de-asserted (logic [1]) before transmitting a new word. SI information is ignored when CS is in a logic high state.RETURN TO ZERO (RTZ)This is a multiplexed output pin for the non-driven coil, during a Return to Zero (RTZ) event.VOLTAGE (VDD)The SPI and logic power supply input will work with 5.0 V supplies.RESET (RST)If the master decides to reset the device, or place it into a sleep state, the RST pin is driven to a Logic [0]. A Logic [0] on the RST pin forces all internal logic to the known default state. This input has an internal active pull-up.VOLTAGE POWER (VPWR)This is the power supply pin.FUNCTIONAL DESCRIPTIONFUNCTIONAL INTERNAL BLOCK DESCRIPTION (OPTIONAL) FUNCTIONAL INTERNAL BLOCK DESCRIPTION (OPTIONAL)Figure 6. Functional Internal 33977 Block IllustrationSERIAL PERIPHERAL INTERFACE (SPI) This circuitry manages incoming messages and outgoing status data.LOGICThis design element includes internal logic including state machines and message decoding.INTERNAL REFERENCEThis design element is used for step value levels.UNDER AND OVERVOLTAGE DETECTION This design element detects when V PWR is out of the normal operating range.OSCILLATORThe internal oscillator generates the internal clock for all timing critical features.H-BRIDGE AND CONTROLThis circuitry contains the output coil drivers and the multiplexers necessary for four quadrant operation and RTZ sequencing. This circuitry is repeated for the Sine and Cosine coils.•Overtemperature — Each output includes an overtemperature sensing circuit•ILIM — Each output is current limitedRETURN TO ZERO (RTZ)This circuitry outputs the voltage present on the non-driven coil during RTZ operation.SPI LogicUnder andOscillator OvervoltageDetectH-Bridge and Control Internal ReferenceRTZFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESSTATE MACHINE OPERATIONThe 33977 is ideal for use in instrumentation systemsrequiring distributed and flexible stepper motor gauge driving.The device also eases the transition to stepper motors fromair core motors by emulating the air core pointer movementwith little additional processor bandwidth utilization. The two-phase stepper motor has maximum allowable velocities andacceleration and deceleration. The purpose of the steppermotor state machine is to drive the motor with the maximumperformance while remaining within the motor’s voltage,velocity, and acceleration constraints.A requirement of the state machine is to ensure thedeceleration phase begins at the correct time and pointerposition. When commanded, the motor [will deleted PV]accelerates constantly to the maximum velocity, and then itmoves toward the commanded position at the maximumvelocity. Eventually, the pointer reaches the calculatedlocation where the movement has to decelerate, safelyslowing to a stop at the desired position. During thedeceleration phase, the motor does [will deleted PV] notexceed the maximum deceleration.During normal operation, both stepper motor rotors aremicrostepped at 24 steps per electrical revolution, illustratedin Figure 7. A complete electrical revolution results in twodegrees of pointer movement. There is a second smaller[parentheses removed-unnecessary] state machine in the ICcontrolling these microsteps. The smaller state machinereceives clockwise or counter-clockwise index commands attimed intervals, thereby stepping the motor in the appropriatedirection by adjusting the current in each coil. Normalizedvalues are provided in Table 5.Figure 7. Clockwise MicrostepsTable 5. Coil Step ValueStep Angle SINE(Angle)*COS (Angle -30)*PE6=0COS (Angle -30)*PE6=100.00.0 1.00.866 1150.2590.9650.966 2300.50.866 1.0 3450.7070.7070.966 4600.8660.50.866 5750.9660.2590.707 690 1.00.00.500 71050.966-0.2590.259 81200.866-0.50.0 91350.707-0.707-0.259 101500.5-0.866-0.500FUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESThe motor is stepped by providing index commands at intervals. The time between steps defines the motor velocity and the changing time defines the motor acceleration.The state machine uses a table to define the allowed time and the maximum velocity. A useful side effect of the table is that it also allows the direct determination of the position at which the velocity should reduce to stop the motor at the desired position.Motor motion equations follow: [reworded for efficient use of space](The units of position are steps and velocity and acceleration are in steps/second and steps/second2.) From an initial position of 0 with an initial velocity (u), the motor position (s) at a time (t) is:For unit steps, the time between steps is:This defines the time increment between steps when the motor is initially traveling at a velocity u. In the ROM, this time is quantized to multiples of the system clock by rounding upwards, ensuring acceleration never exceeds the allowed value. The actual velocity and acceleration is calculated from the time step actually used. Using:andand solving for v in terms of u, s, and t gives:The correct value of t to use in the equation is thequantized value obtained above.From these equations, a set of recursive equations can be generated to give the allowed time step between motor indexes when the motor is accelerating from a stop to its maximum velocity.Starting from a position p of 0 and a velocity v of 0, these equations define the time interval between steps at each position. To drive the motor at maximum performance, index commands are given to the motor at these intervals. A table is generated giving the time step *t at an index position n. Note: [chgd for format consistency AND deleted that as PV] For p n = n, on the nth step, the motor [has deleted as PV] indexed by n positions and has been accelerating steadily at the maximum allowed rate. This is critical because it also indicates the minimum distance the motor must travel while decelerating to a stop. For example, the stopping distance isalso equal to the current value of n.The algorithm of pointer movement can be summarized in two steps:1.The pointer is at the previously commanded positionand is not moving.2. A command to move to a pointer position (other thanthe current position) has been received. Timed indexpulses are sent to the motor driver at an ever-increasing rate, according to the time steps in Table 6, until:aThe maximum velocity (default or selected) isreached after which the step time intervals will nolonger decrease.bThe distance in steps that remain to travel are less than the current step time index value. The motorthen decelerates by increasing the step timesaccording to Table 6 until the commandedposition is reached. The state machine controlsthe deceleration so that the pointer reaches thecommanded position efficiently.An example of the velocity table for a particular motor is provided in Table 6. This motor’s maximum speed is 4800111650.259-0.966-0.707 121800.0-1.0-0.866 13195-0.259-0.966-0.966 14210-0.5-0.867-1.0 15225-0.707-0.707-0.966 16240-0.866-0.5-0.866 17255-0.966-0.259-0.707 18270-1.00.0-0.500 19285-0.9660.259-0.259 20300-0.8660.50.0 21315-0.7070.7070.259 22330-0.50.8660.500 23345-0.2590.9660.707 * Denotes normalized valuesTable 5. Coil Step Values = ut + 1/2 at 2⇒t =- u + √u2 + 2aav2 = u2 + 2asv = u + atv = 2/t - up0 = 0v0 = 0∆t n =⎡-vn -1 + √v2n -1 + 2aa⎤where ⎡ ⎤ indicates rounding upv n = 2/∆tn - V n -1p n = nFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESmicrosteps/s (at 12 microsteps/degrees), and its maximum acceleration is 54000 microsteps/s2. The table is quantized to a 1.0 MHz clock.Table 6. Velocity TableVelocity Position Time BetweenSteps (µs)Velocity(µSteps/s)VelocityPositionTime BetweenSteps (µs)Velocity(µSteps/s)VelocityPositionTime BetweenSteps (µs)Velocity(µSteps/s)00.00.00763802631.61522573891.1 12721736.7773772652.51532563906.3 21360773.5783742673.81542553921.6 31127188.7793722688.21552543937.0 47970125.5803692710.01562543937.0 55858170.7813662732.21572533952.6 64564219.1823642747.31582523968.3 73720268.8833612770.11592513984.1 83132319.3843582793.31602504000.0 92701370.2853562809.01612494016.1 102373421.4863542824.91622484032.3 112115472.8873512849.01632484032.3 121908524.1883492865.31642474048.6 131737575.7893472881.81652464065.0 141594627.4903442907.01662454081.6 151473678.9913422924.01672444098.4 161369730.5923402941.21682444098.4 171278782.5933382958.61692434115.2 181199834.0943362976.21702424132.2 191129885.7953342994.01712414149.4 201066938.1963323012.01722414149.4 211010990.1973303030.31732404166.7 229601041.7983283048.81742394184.1 239161091.7993263067.51752384201.7 248771140.31003243086.41762384201.7 258421187.61013223105.61772374219.4 268121231.51023213115.31782364237.3 277841275.51033193134.81792654255.3 287601315.81043173154.61802354255.3 297371356.91053153174.61812344273.5 307161396.61063143184.71822334291.8 316971434.71073123205.11832334291.8 326801470.61083103225.81842324310.3 336631508.31093093236.21852314329.0 346481543.21103073257.31862314329.0 356341577.31113063268.01872304347.8。

中文摩斯编码表我把全部中文电报码给你发在下面,你最好打印下来.以便随时可以查阅:、9977 。

9975 .9978 .9992 .9993 —9994 —9995 (9991)‘9984 ’9985 “9986 ”9987 《9996 》9997 ×9973 ×9999÷9974 □9998 Ⅰ9941 Ⅱ9942 Ⅲ9943 Ⅳ9944 Ⅴ9945 Ⅵ9946Ⅶ9947 Ⅷ9948 Ⅸ9949 Ⅹ9950 ！9982 （9988 ）9989 ＋9971，9976 －9972 ／9970 09960 19961 29962 39963 4996459965 69966 79967 89968 99969 ：9980 ；9979 ＝9983？9981 A9874 B9875 C9876 D9877 E9878 F9879 G9880H9881 I9882 J9883 K9884 L9885 M9886 N9887 O9888O9800 P9889 Q9890 R9891 S9892 T9893 U9894 V9895W9896 X9897 Y9898 Z9899 Ω9959 А9768 Б9769 В9770Г9771 Д9772 Е9773 Ж9774 З9775 И9776 Й9799 К9777Л9778 М9779 Н9780 О9781 П9782 Р9783 С9784 Т9785У9786 Ф9787 Х9788 Ц9789 Ч9790 Ш9791 Щ9792 Ъ9796Ы9797 Ь9798 Э9793 Ю9794 Я9795 ㄅ9720 ㄆ9721 ㄇ9722ㄈ9723 ㄉ9724 ㄊ9725 ㄋ9726 ㄌ9727 ㄍ9728 ㄎ9729 ㄏ9730ㄐ9731 ㄑ9732 ㄒ9733 ㄓ9734 ㄔ9735 ㄕ9736 ㄖ9737 ㄗ9738ㄘ9739 ㄙ9740 ㄚ9744 ㄛ9745 ㄜ9746 ㄝ9747 ㄞ9748 ㄟ9749ㄠ9750 ㄡ9751 ㄢ9752 ㄣ9753 ㄤ9754 ㄥ9755 ㄦ9756 ㄧ9741ㄨ9742 ㄩ9743 ━9990 啊0759 阿7093 埃1002 挨2179 哎0740唉0780 哀0755 皑4114 癌4074 蔼5676 矮4253 艾5337 碍4293爱1947 隘7137 鞍7254 氨8637 安1344 俺0219 按2174 暗2542岸1489 胺5143 案2714 肮7542 昂2491 盎4138 凹0425 敖2407熬3581 翱5063 袄5984 傲0277 奥1159 懊2020 澳3421 芭5359捌2193 扒2091 叭0665 吧0721 笆4576 八9908 八9808 八0360八9708 疤4002 巴1572 拔2149 跋6405 靶7249 把2116 耙5090坝8218 坝1056 霸7218 霸6011 罢5007 爸3640 白4101 柏2672百4102 摆2369 佰0184 败2408 拜2157 稗4458 斑2432 班3803搬2289 扳2104 般5301 颁7317 板2647 版3652 扮2101 拌2142伴0133 瓣3904 半0584 办6586 绊4810 邦6721 帮1620 梆2735榜2831 膀5218 绑4834 棒2761 磅4319 蚌5732 镑6967 傍0266谤6196 苞5383 胞5165 包0545 褒5988 剥0475 薄5631 雹7192保0202 堡1027 饱7394 宝1405 抱2128 报1032 暴2552 豹6283鲍7637 爆3915 爆3615 杯2637 碑4301 悲1896 卑0585 北0554辈6543 背5154 贝6296 倍0223 狈3709 备0271 惫1994 焙3538被5926 奔1149 苯0058 本2609 笨4570 崩1514 绷4855 甭8005泵3119 蹦6498 迸6618 逼6656 鼻7865 比3024 鄙6766 笔4581彼1764 碧4310 蓖5557 蔽5599 毕3968 毙2426 毖3025 币1578庇1642 痹4036 闭7028 敝2411 弊1705 必1801 辟6582 壁1084 臂5242 避6699 陛7103 鞭7267 边6708 编4882 贬6312 扁2078 便0189 变6239 卞0593 辨6587 辩6589 辫4947 遍6664 标2871 彪1753 膘9136 表5903 鳖7667 别0446 瘪4085 彬1755 斌2430 濒3464 滨3453 宾6333 摈2363 兵0365 冰0393 柄2671 丙0014 秉4426 饼7399 炳3521 病4016 并1629 玻3788 菠5474 播2330 拨2328 钵6886 波3134 博0590 勃0514 搏2276 铂6896 箔4613 伯0130 帛1591 舶5306 脖9126 膊5225 渤3258 泊3124 驳7463 捌2193 扒2091 叭0665 吧0721 笆4576 八9908八9808 八0360八9708 疤4002 巴1572 拔2149 跋6405 靶7249 把2116 耙5090 坝8218 坝1056 霸7218 霸6011 罢5007 爸3640 白4101 柏2672 百4102 摆2369 佰0184 败2408 拜2157 稗4458 斑2432 班3803 搬2289 扳2104 般5301 颁7317 板2647 版3652 扮2101 拌2142 伴0133 瓣3904 半0584 办6586 绊4810 邦6721 帮1620 梆2735 榜2831 膀5218 绑4834 棒2761 磅4319 蚌5732 镑6967 傍0266 谤6196 苞5383 胞5165 包0545 褒5988 剥0475 薄5631 雹7192 保0202 堡1027 饱7394 宝1405 抱2128 报1032 暴2552 豹6283 鲍7637 爆3915 爆3615 杯2637 碑4301 悲1896 卑0585 北0554 辈6543 背5154 贝6296 倍0223 狈3709 备0271 惫1994 焙3538 被5926 奔1149 苯0058 本2609 笨4570 崩1514 绷4855 甭8005 泵3119 蹦6498 迸6618 逼6656 鼻7865 比3024 鄙6766 笔4581 彼1764 碧4310 蓖5557 蔽5599 毕3968 毙2426 毖3025 币1578 庇1642 痹4036 闭7028 敝2411 弊1705 必1801 辟6582 壁1084 臂5242 避6699 陛7103 鞭7267 边6708 编4882 贬6312 扁2078 便0189 变6239 卞0593 辨6587 辩6589 辫4947 遍6664 标2871 彪1753 膘9136 表5903 鳖7667 别0446 瘪4085 彬1755 斌2430 濒3464 滨3453 宾6333 摈2363 兵0365 冰0393 柄2671 丙0014 秉4426 饼7399 炳3521 病4016 并1629 玻3788 菠5474 播2330 拨2328 钵6886 波3134 博0590 勃0514 搏2276 铂6896 箔4613 伯0130 帛1591 舶5306 脖9126 膊5225 渤3258 泊3124 驳7463 捌2193 扒2091 叭0665 吧0721 笆4576 八9908 八9808 八0360 八9708 疤4002 巴1572 拔2149 跋6405 靶7249 把2116 耙5090 坝8218 坝1056 霸7218 霸6011 罢5007 爸3640 白4101 柏2672 百4102 摆2369 佰0184 败2408 拜2157 稗4458 斑2432 班3803 搬2289 扳2104 般5301 颁7317 板2647 版3652 扮2101 拌2142 伴0133 瓣3904 半0584 办6586 绊4810 邦6721 帮1620 梆2735 榜2831 膀5218 绑4834 棒2761 磅4319 蚌5732 镑6967 傍0266 谤6196 苞5383 胞5165 包0545 褒5988 剥0475 薄5631 雹7192 保0202 堡1027 饱7394 宝1405 抱2128 报1032 暴2552 豹6283 鲍7637 爆3915 爆3615 杯2637 碑4301 悲1896 卑0585 北0554辈6543 背5154 贝6296 倍0223 狈3709 备0271 惫1994 焙3538被5926 奔1149 苯0058 本2609 笨4570 崩1514 绷4855 甭8005泵3119 蹦6498 迸6618 逼6656 鼻7865 比3024 鄙6766 笔4581彼1764 碧4310 蓖5557 蔽5599 毕3968 毙2426 毖3025 币1578庇1642 痹4036 闭7028 敝2411 弊1705 必1801 辟6582 壁1084臂5242 避6699 陛7103 鞭7267 边6708 编4882 贬6312 扁2078便0189 变6239 卞0593 辨6587 辩6589 辫4947 遍6664 标2871彪1753 膘9136 表5903 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秦44英文字母篇：A：（短·长）B：（长·短·短·短）C：（长·短·长·短）D：（长·短·短）E：（短）F：（短·短·长·短）G：（长·长·短）H：（短·短·短·短）I：（短·短）J：（短·长·长·长）K：（长·短·长）L：（短·长·短·短）M：（长·长）N：（长·短）O：（长·长·长）P：（短·长·长·短）Q：（长·长·短·长）R：（短·长·短）S：（短·短·短）T：（长）U：（短·短·长）V：（短·短·短·长）W：（短·长·长）X：（长·短·短·长）Y：（长·短·长·长）Z：（长·长·短·短）数字篇：1：（短·长·长·长·长）2：（短·短·长·长·长）3：（短·短·短·长·长）4：（短·短·短·短·长）5：（短·短·短·短·短）6：（长·短·短·短·短）7：（长·长·短·短·短）8：（长·长·长·短·短）9：（长·长·长·长·短）0：（长·长·长·长·长）符号篇：“.”：（短·长·短·长·短·长）“，”：（长·长·短·短·长·长）“：”：（长·长·长·短·短·短）“?”：（短·短·长·长·短·短）“－”：（长·短·短·短·短·长）“/”：（长·短·短·长·短）“（）”：（长·短·长·长·短·长）特殊用语篇：引对方注意并使其回复：（长·短·长·长·短·长）对方收到并回复信号：（长·长）发出信息前的开始命令（己方，并提示叫对方接收）：（长·短·长·短·长）发信错误并更正（使对方知道你发送错误）：（短·短·短·短·短·短）发信结束：（短·短·短·长·短）间隔时间：滴，1t；答,3t；滴答间,1t；字母间,3t；字间,5t。

áçXRT7300E3/DS3/STS-1 LINE INTERFACE UNIT FEBRUARY 2002REV. 1.1.1GENERAL DESCRIPTIONThe XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 ap-plications and consists of a line transmitter and re-ceiver integrated on a single chip.XRT7300 can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates.In the transmit direction, the XRT7300 encodes input data to either B3ZS (for DS3/STS-1 applications) or HDB3 (for E3 applications) format and converts the data into the appropriate pulse shapes for transmis-sion over coaxial cable via a 1:1 transformer.In the receive direction the XRT7300 performs equal-ization on incoming signals, performs Clock Recov-ery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of line code violations.The XRT7300 also contains a 4-Wire Microprocessor Serial Interface for accessing the on-chip Command registers.FEATURES•Meets E3/DS3/STS-1 Jitter T olerance Require-ments•Full Loop-Back Capability•T ransmit and Receive Power Down Modes•Full Redundancy Support•Contains a 4-Wire Microprocessor Serial Interface •Uses Minimum External components•Requires Single +5V Power Supply•-40°C to +85°C Operating T emperature Range •Available in a 44 pin TQFP package APPLICATIONS•Interfaces to E3, DS3 or SONET STS-1 Networks •CSU/DSU Equipment•PCM T est Equipment•Fiber Optic T erminals•MultiplexersN OTE: This Device is Protected by US Patent # 6,157,270F IGURE 1. B LOCK D IAGRAM OF THE XRT7300元器件交易网Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • XRT7300áçE3/DS3/STS-1 LINE INTERFACE UNITREV. 1.1.12ORDERING INFORMATIONP ART N UMBER P ACKAGE T YPEO PERATING T EMPERATURE R ANGEXRT7300IV44 Pin TQFP (10mm x 10mm)-40°C to +85°CF IGURE 2. P IN O UT OF THE XRT7300 IN THE 44 P IN TQFPáçE3/DS3/STS-1 LINE INTERFACE UNIT XRT7300REV. 1.1.1TABLE OF CONTENTSGeneral description (1)FEATURES (1)APPLICATIONS (1)Figure 1.Block Diagram of the XRT7300 (1)Ordering Information (2)Figure 2.Pin Out of the XRT7300 in the 44 Pin TQFP (2)TABLE OF CONTENTS (I)Pin Description (3)Electrical Characteristics (10)DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECI-FIED) (10)AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECI-FIED) (10)Figure 3.Timing Diagram of the Transmit Terminal Input Interface (11)Figure 4.Timing Diagram of the Receive Terminal Output Interface (11)AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-WISE SPECIFIED) (12)AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-WISE SPECIFIED) (13)ABSOLUTE MAXIMUM RATINGS (14)Figure 5.Transmit Pulse Amplitude Test Circuit for DS3, E3 and STS-1 Rates (15)Figure 6.ITU-T G.703 Transmit Output Pulse Template for E3 Applications (15)Figure 7.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications (16)Figure 8.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications (16)MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE9) (17)Figure 9.Timing Diagram for the Microprocessor Serial Interface (17)System Description (18)THE TRANSMIT SECTION (18)THE RECEIVE SECTION (18)THE MICROPROCESSOR SERIAL INTERFACE (18)Table 1:Role of Microprocessor Serial Interface pins when the XRT7300 is operating in the Hardware Mode18 1.0 SELECTING THE DATA RATE (19)Table 2:Selecting the Data Rate for the XRT7300 via the E3 and STS-1/DS3 input pins (Hardware Mode) (19)COMMAND REGISTER CR4 (ADDRESS = 0X04) (19)Table 3:Selecting the Data Rate for the XRT7300 Via the STS-1/DS3 and the E3 Bit-fields Within Command Register CR4 (HOST Mode) (19)2.0 THE TRANSMIT SECTION (20)2.1 T HE T RANSMIT L OGIC B LOCK (20)Figure 10.The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Transmitting Ter-minal Equipment to the Transmit Section of the XRT7300 (20)Figure 11.How the XRT7300 Samples the Data on the TPDATA and TNDATA Input Pins (20)Accepting Single-Rail Data from the Terminal Equipment (21)COMMAND REGISTER CR1 (ADDRESS = 0X01) (21)Figure 12.The Behavior of the TPDATA and TCLK Input Signals While the Transmit Logic Block is Accepting Single-Rail Data From the Terminal Equipment (21)IXRT7300E3/DS3/STS-1 LINE INTERFACE UNITáçREV. 1.1.12.2 T HE T RANSMIT C LOCK D UTY C YCLE A DJUST C IRCUITRY (21)2.3 T HE HDB3/B3ZS E NCODER B LOCK (22)B3ZS Encoding (22)Figure 13.An Example of B3ZS Encoding (22)HDB3 Encoding (22)Figure 14.An Example of HDB3 Encoding (23)Enabling/Disabling the HDB3/B3ZS Encoder (23)2.4 T HE T RANSMIT P ULSE S HAPER C IRCUITRY (23)COMMAND REGISTER CR2 (ADDRESS = 0X02 (23)Enabling the Transmit Line Build-Out Circuit (23)Disabling the Transmit Line Build-Out Circuit (23)COMMAND REGISTER CR1 (ADDRESS = 0X01) (23)Design Guideline for Setting the Transmit Line Build-Out Circuit (24)COMMAND REGISTER CR1 (ADDRESS = 0X01) (24)The Transmit Line Build-Out Circuit and E3 Applications (24)2.5 I NTERFACING THE T RANSMIT S ECTION OF THE XRT7300 TO THE L INE (24)Figure 15.Recommended Schematic for Interfacing the Transmit Section of the XRT7300 to the Line (24)TRANSFORMER RECOMMENDATIONS (25)3.0 THE RECEIVE SECTION (25)3.1 I NTERFACING THE R ECEIVE S ECTION OF THE XRT7300 TO THE L INE (25)Figure 16.Recommended Schematic for Interfacing the Receive Section of the XRT7300 to the Line (Transform-er-Coupling) (26)Figure 17.Recommended Schematic for Interfacing the Receive Section of the XRT7300 to the Line (Capaci-tive-Coupling) (26)3.2 T HE R ECEIVE E QUALIZER B LOCK (26)Figure 18. The Typical Application for the System Installer (27)COMMAND REGISTER CR2 (ADDRESS = 0X02) (28)3.3 P EAK D ETECTOR AND S LICER (28)3.4 C LOCK R ECOVERY PLL (28)3.5 T HE HDB3/B3ZS D ECODER (28)B3ZS Decoding DS3/STS-1 Applications (29)Figure 19.An Example of B3ZS Decoding (29)HDB3 Decoding E3 Applications (29)Figure 20.An Example of HDB3 Decoding (29)Enabling/Disabling the HDB3/B3ZS Decoder (30)3.6 LOS D ECLARATION/C LEARANCE (30)COMMAND REGISTER CR2 (ADDRESS = 0X02) (30)The LOS Declaration/Clearance Criteria for E3 Applications (30)Figure 21.The Signal Levels that the XRT7300 Declares and Clears LOS (E3 Mode Only) (31)Figure 22.The Behavior the LOS Output Indicator In Response to the Loss of Signal and the Restoration of Sig-nal (31)The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications (32)Table 4:The ALOS Declaration and Clearance Thresholds for a Given Setting of LOSTHR (DS3 and STS-1 Ap-plications) for Equalizer Enabled or Disabled (32)COMMAND REGISTER CR0 (ADDRESS = 0X00) (32)COMMAND REGISTER CR2 (ADDRESS = 0X02) (33)COMMAND REGISTER CR0 (ADDRESS = 0X00) (33)IIáçE3/DS3/STS-1 LINE INTERFACE UNIT XRT7300REV. 1.1.1COMMAND REGISTER CR2 (ADDRESS = 0X02) (33)Muting the Recovered Data while the LOS is being Declared (33)3.7 R OUTING THE R ECOVERED T IMING AND D ATA I NFORMATION TO THE R ECEIVING T ERMINAL E QUIPMENT (33)COMMAND REGISTER CR3 (ADDRESS = 0X03) (33)Figure 23. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Receive Section of the XRT7300 to the Receiving Terminal Equipment (34)Figure 24. How the XRT7300 Outputs Data on the RPOS and RNEG Output Pins (34)Figure 25.The Behavior of the RPOS, RNEG and RCLK1 Signals When RCLK1 is Inverted (35)Routing Single-Rail Format data (Binary Data Stream) to the Receive Terminal Equipment (35)COMMAND REGISTER CR3 (ADDRESS = 0X03) (35)COMMAND REGISTER CR3 (ADDRESS = 0X03) (35)Figure 26.The Typical Interface for the Transmission of Data in a Single-Rail Format From the Receive Section of the XRT7300 to the Receiving Terminal Equipment (36)Figure 27.The Behavior of the RPOS and RCLK1 Output Signals While the XRT7300 is Transmitting Single-Rail Data to the Receiving Terminal Equipment (36)4.0 DIAGNOSTIC FEATURES OF THE XRT7300 (36)4.1 T HE A NALOG L OCAL L OOP-B ACK M ODE (36)Figure 28.The Analog Local Loop-Back in the XRT7300 (37)COMMAND REGISTER CR4 (ADDRESS = 0X04) (37)4.2 T HE D IGITAL L OCAL L OOP-B ACK M ODE (37)Figure 29.The Digital Local Loop-Back path in the XRT7300 (38)COMMAND REGISTER CR4 (ADDRESS = 0X04) (38)4.3 T HE R EMOTE L OOP-B ACK M ODE (38)Figure 30.The Remote Loop-Back Path in the XRT7300 (39)COMMAND REGISTER CR4 (ADDRESS = 0X04) (39)4.4 TXOFF F EATURES (40)COMMAND REGISTER CR1 (ADDRESS = 0X01) (40)4.5 T HE T RANSMIT D RIVE M ONITOR F EATURES (40)Figure 31.The XRT7300 Employing the Transmit Drive Monitor Features (40)Figure 32. Two LIU’s, Each Monitoring the Transmit Output Signal of the Other LIU IC (41)4.6 T HE TAOS (T RANSMIT A LL O NE S) F EATURE (41)COMMAND REGISTER CR1 (ADDRESS = 0X01) (41)5.0 THE MICROPROCESSOR SERIAL INTERFACE (42)5.1 D ESCRIPTION OF THE C OMMAND R EGISTERS (42)Table 5:Addresses and Bit Formats of XRT7300 Command Registers (42)DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER (42)Command Register - CR0 (42)Command Register - CR1 (43)Command Register - CR2 (44)Command Register - CR3 (44)Command Register - CR4 (45)5.2 O PERATING THE M ICROPROCESSOR S ERIAL I NTERFACE (45)Table 6:Loop-Back Modes (45)Figure 33.Microprocessor Serial Interface Data Structure (46)Figure 34. How to Interface the XRT7300 IC to the XRT7234/45 E3/DS3 ATM UNI IC (47)Figure 35.How to Interface the XRT7300 IC to the XRT7250 DS3/E3 Framer IC (48)ORDERING INFORMATION (49)Package Dimensions (49)IIIXRT7300E3/DS3/STS-1 LINE INTERFACE UNITáçREV. 1.1.1REVISION HISTORY (50)IVáçXRT7300E3/DS3/STS-1 LINE INTERFACE UNITREV. 1.1.13PIN DESCRIPTIONPIN DESCRIPTIONP IN#S YMBOLT YPE D ESCRIPTION1TXLEVITransmit Line Build-Out Enable/Disable Select:This input pin is used to enable or disable the T ransmit Line Build-Out circuit in the XRT7300.Setting this pin to “High” disables the Line Build-Out circuit. In this mode, the XRT7300 outputs partially shaped pulses onto the line via the TTIP and TRING output pins.Setting this pin to “Low” enables the Line Build-Out circuit. In this mode, the XRT7300 outputs partially-shaped pulses onto the line via the TTIP and TRING output pins.T o comply with the isolated DSX-3/STSX-1 Pulse T emplate Requirements per Bellcore GR-499-Core or Bellcore GR-253-Core:1. Set this input pin to a "1" if the cable length between the Cross-Connect and the transmit output of the XRT7300 is greater than 225 feet.2. Set this input pin to a "0" if the cable length between the Cross-Connect and the transmit output of the XRT7300 is less than 225 feet.This pin is active only if both of the following are true:(a) The XRT7300 is configured to operate in either the DS3 or SONET STS-1 modes and(b) The XRT7300 is configured to operate in the Hardware Mode.N OTE : This pin should be tied to GND if the XRT7300 is to be operated in the HOST mode.2T AOS ITransmit All Ones Select:A “High” on this pin causes a continuous AMI all “1’s” pattern to be transmitted onto the line. The frequency of this “1’s” pattern is determined by TCLK.N OTES :1.This input pin is ignored if the XRT7300 is operating in the HOST Mode.2.Tie this pin to GND if the XRT7300 is going to be operating in the HOST Mode.3VDD ****Transmit Digital Power Supply4DMOODrive Monitor Output:If no transmitted AMI signal is present on MTIP and MRING input pins for 128±32 TCLK periods, then the DMO pin toggles and remains “High” until the next AMI signal is detected.5GND ****Transmit Digital GND 6GND ****Analog GND (Substrate)7GND****Receive Analog GND8RTIPIReceive TIP Input:This input pin along with RRING is used to receive the line signal from the Remote DS3/E3/STS-1 T erminal.9RRING IReceive RING Input:This input pin along with RTIP is used to receive the line signal from the Remote DS3/E3/STS-1 T erminal.10VDD ****Receive Analog VDDXRT7300áçE3/DS3/STS-1 LINE INTERFACE UNITREV. 1.1.1411REGRESET/(RCLK2INV)IRegister Reset Input pin (Invert RCLK2 Output - Select):The function of this pin depends upon whether the XRT7300 is operating in the HOST Mode or in the Hardware Mode.HOST Mode - Register Reset Input pin:Setting this input pin “Low” causes the XRT7300 to reset the contents of the Command Registers to their default settings and operating configuration. This pin is internally pulled “High”.Hardware Mode - Invert RCLK2 Output Select:Setting this input pin “Low” configures the Receive Section of the XRT7300 to output the recovered data via the RPOS and RNEG output pins on the rising edge of the RCLK2 output signal.Setting this input pin “High” configures the Receive Section to output the recov-ered data on the falling edge of the RCLK2 output signal.12REQDIS IReceive Equalization Disable Input:Setting this input pin “High” disables the Internal Receive Equalizer in the XRT7300. Setting this pin “Low” enables the Internal Receive Equalizer. The guidelines for enabling and disabling the Receive Equalizer are described in Section 3.2.N OTES :1.This input pin is ignored if the XRT7300 is operating in the HOST Mode.2.Tie this pin to GND if the XRT7300 is going to be operating in the HOST Mode.13LOSTHR ILoss of Signal Threshold Control:The voltage forced on this pin controls the input loss of signal (LOS) threshold. T wo settings are provided by forcing this signal to either GND or VDD. N OTE : This pin is only applicable during DS3 or STS-1 operations.14LLB ILocal Loop-Back Select:This input pin along with RLB dictates which Loop-Back mode the XRT7300 is operating in.A “High” on this pin with RLB being set to “Low” configures the XRT7300 to oper-ate in the Analog Local Loop-Back Mode.A “High” on this pin with RLB also being set to “High” configures the XRT7300 to operate in the Digital Local Loop-Back Mode.N OTES :1.This input pin is ignored if the XRT7300 is operating in the HOST Mode.2.Tie this pin to GND if the XRT7300 is going to be operating in the HOST Mode.15RLB IRemote Loop-Back Select:This input pin along with LLB dictates which Loop-Back mode the XRT7300 is be operating in.A “High” on this pin with LLB being set to “Low” configures the XRT7300 to oper-ate in the Remote Loop-Back Mode.A “High” on this pin with LLB also being set to “High” configures the XRT7300 to operate in the Digital Local Loop-Back Mode.N OTES :1.This input pin is ignored if the XRT7300 is operating in the HOST Mode.2.Tie this pin to GND if the XRT7300 is going to be operating in the HOST Mode.PIN DESCRIPTIONP IN#S YMBOL T YPE D ESCRIPTIONáçXRT7300E3/DS3/STS-1 LINE INTERFACE UNITREV. 1.1.1516STS-1/DS3ISTS-1/DS3 Select Input:A “High” on this pin configures the Clock Recovery Phase Locked Loop to set its VCO Center frequency to around 51.84 MHz (optimal for SONET STS-1 opera-tions). A “Low” on this pin configures the Clock Recovery Phase Locked Loop to set its VCO Center frequency to around 44.736 MHz (optimal for DS3 opera-tions).N OTES :1.The XRT7300 ignores this pin if the E3 pin (pin 17) is set to “1”.2.This input pin is ignored if the XRT7300 is operating in the HOST Mode.3.Tie this pin to GND if the XRT7300 is going to be operating in the HOST Mode.17E3IE3 Select Input:A “High” on this pin configures the XRT7300 to operate in the E3 Mode.A “Low” on this pin configures the XRT7300 to check the state of the STS-1/DS3 input pin.N OTES :1.This input pin is ignored if the XRT7300 is operating in the HOST Mode.2.Tie this pin to GND if the XRT7300 is going to be operating in the HOST Mode.18HOST/HW IHOST/HW Mode Select:This input pin is used to enable or disable the Microprocessor Serial Interface (e.g., consisting of the SDI, SDO, SCLK, CS and REGRESET pins).Setting this input pin “High” enables the Microprocessor Serial Interface (e.g. configures the XRT7300 to operate in the HOST Mode). In this mode, theXRT7300 is configured by writing data into the on-chip Command Registers via the Microprocessor Serial Interface. When the XRT7300 is operating in the HOST Mode, it ignores the states of many of the discrete input pins.Setting this input pin “Low” disables the Microprocessor Serial Interface (e.g., configures the XRT7300 to operate in the Hardware Mode). In this mode, many of the external input control pins are functional.19SDI/(LOSMUTEN)ISerial Data Input for the Microprocessor Serial Interface (HOST Mode) or MUTE-upon-LOS Enable Input (Hardware Mode):The function of this input pin depends upon whether the XRT7300 is operating in the HOST or the Hardware Mode.Serial Data Input for the Microprocessor Serial Interface (HOST Mode):This pin is used to read or write data into the Command Registers of the Micro-processor Serial Interface. The Read/Write bit, the Address Values of the Com-mand Registers and Data Value to be written during Write Operations are applied to this pin.This input is sampled on the rising edge of the SCLK pin (pin 21).MUTE-upon-LOS Enable Input (Hardware Mode):When in the Hardware Mode, this input pin is used to configure the XRT7300 to MUTE the recovered data via the RPOS and RNEG output pins whenever it declares an LOS condition.Setting this input pin “High” configures the XRT7300 to automatically pull the RPOS and RNEG output pins to GND whenever it is declaring an LOS condition, thereby MUTing the data being output to the T erminal Equipment.Setting this input pin “Low” configures the XRT7300 to NOT automatically MUTE the recovered data whenever an LOS condition is declared.PIN DESCRIPTIONP IN#S YMBOL T YPE D ESCRIPTIONXRT7300áçE3/DS3/STS-1 LINE INTERFACE UNITREV. 1.1.1620SDO/(LCV)OSerial Data Output from the Controller Port/(Line Code Violation Output (LCV) Indicator.):The function of this input pin depends upon whether the XRT7300 is operating in the HOST or the Hardware Mode.HOST Mode - Microprocessor Serial Interface - Serial Data Output.This pin serially outputs the contents of the specified Command Register during Read Operations. The data on this pin is updated on the falling edge of the SCLK input signal. This pin is tri-stated upon completion of data transfer.Hardware Mode - Line Code Violation Output Indicator.This pin pulses “High” for one bit period any time the Receive Section of the XRT7300 detects a Line Code Violation in the incoming E3, DS3 or STS-1 Data Stream.21SCLK/(ENCO-DIS)IMicroprocessor Serial Interface Clock Signal/Encoder Disable:HOST Mode - Microprocessor Serial Interface Clock SignalThis signal is used to sample the data on the SDI pin on the rising edge of this signal. Additionally, during Read operations the Microprocessor Serial Interface updates the SDO output on the falling edge of this signal.Hardware Mode - B3ZS/HDB3 Encoder DisableSetting this input pin “High” disables the B3ZS/HDB3 Encoder and configures the XRT7300 to transmit the line signal in an AMI Format.Setting this input pin “Low” enables the B3ZS/HDB3 Encoder and configures the XRT7300 to transmit the line signal in the B3ZS format (for DS3/STS-1 opera-tion) or in the HDB3 format (for E3 operation).22CS/(DECODIS)IMicroprocessor Serial Interface - Chip Select/Decoder DisableThe function of this input pin depends upon whether the XRT7300 is operating in the HOST or the Hardware Mode.HOST Mode - Chip Select Input:The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to enable communication with the XRT7300 via the Microprocessor Serial Inter-face.Hardware Mode - (B3ZS/HDB3 Decoder Disable)Setting this input pin “High” disables the B3ZS/HDB3 Decoder. Setting this input pin “Low” enables the B3ZS/HDB3 Decoder.23RLOL OReceive Loss of Lock Output IndicatorThis output pin toggles “High” if the XRT7300 has detected a Loss of Lock Con-dition. The XRT7300 declares an LOL (Loss of Lock) Condition if the recovered clock frequency deviates from the Reference Clock frequency (available at the EXCLK input pin) by more than 0.5%.24RLOS OReceive Loss of Signal Output IndicatorThis output pin toggles “High” if the XRT7300 has detected a Loss of Signal Condition in the incoming line signal.The criteria the XRT7300 uses to declare an LOS Condition depends upon whether the device is operating in the E3 or DS3/STS-1 Mode.25GND ****Digital GND 26VDD****Digital VDDPIN DESCRIPTIONP IN#S YMBOL T YPE D ESCRIPTIONPIN DESCRIPTIONP IN#S YMBOL T YPE D ESCRIPTION27EXCLK I External Reference Clock Input:Apply a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signalfor DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications.28GND****Receiver Digital Ground29VDD****Receiver Digital VDD30LCV/(RCLK2)O Line Code Violation Indicator/Receive Clock Output pin 2:The function of this pin depends upon whether the XRT7300 is operating in theHOST Mode, the Hardware Mode or User selection.HOST Mode - Line Code Violation Indicator Output:If the XRT7300 is configured to operate in the HOST Mode, then this pin func-tions as the LCV output pin by default. However, by using the on-chip CommandRegisters, this pin can be configured to function as the second Receive Clocksignal output pin (RCLK2).Hardware Mode - Receive Clock Output pin 2:This output pin is the Recovered Clock signal from the incoming line signal. Thereceive section of the XRT7300 outputs data via the RPOS and RNEG outputpins on the rising edge of this clock signal.N OTE: If the XRT7300 is operating in the HOST Mode and this pin is configuredto function as the additional Receive Clock signal output pin, then the XRT7300can be configured to update the data on the RPOS and RNEG output pins on thefalling edge of this clock signal.31RCLK1O Receive Clock Output pin 1:This output pin is the Recovered Clock signal from the incoming line signal. Thereceive section of the XRT7300 outputs data via the RPOS and RNEG outputpins on the rising edge of this clock signal.N OTE: If the XRT7300 device is operating in the “Host” Mode, then the user canconfigure the device to update the data on the RPOS and RNEG output pins onthe falling edge of this clock signal.32RNEG O Receive Negative Pulse Output:This output pin pulses “High” whenever the XRT7300 has received a NegativePolarity pulse in the incoming line signal at the RTIP/RRING inputs.N OTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is notreflected at this output.33RPOS O Receive Positive Pulse Output:This output pin pulses “High” whenever the XRT7300 has received a PositivePolarity pulse in the incoming line signal at the RTIP/RRING inputs.N OTE: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is notreflected at this output.34ICT I In-Circuit Test Input:Setting this pin “Low” causes all digital and analog outputs to go into a high-impedance state to allow for in-circuit testing. This pin is internally pulled “High”.PIN DESCRIPTIONP IN#S YMBOL T YPE D ESCRIPTION35TXOFF I Transmitter OFF Input:Setting this input pin “High” configures the XRT7300 to turn off the T ransmitter inthe device.N OTES:1.This input pin is ignored if the XRT7300 is operating in the HOST Mode.2.Tie this pin to GND if the XRT7300 is going to be operating in the HOSTMode.36TCLK I Transmit Clock Input for TPDATA and TNDATA:This input pin must be driven at 34.368 MHz for E3 applications, 44.736MHz forDS3 applications, or 51.84MHz for SONET STS-1 applications. The XRT7300uses this signal to sample the TPDA T A and TNDA T A input pins. By default, theXRT7300 is configured to sample these two pins on the falling edge of this sig-nal.If the XRT7300 is operating in the HOST Mode, then the device can be config-ured to sample the TPDA T A and TNDA T A input pins on the rising edge of TCLK.37TPDA T A I Transmit Positive Data Input:The XRT73L00 samples this pin on the falling edge of TCLK. If the device sam-ples a “1” at this input pin, then it generates and transmits a positive polaritypulse to the line.N OTES:1.The data should be applied to this input pin if the T ransmit Section isconfigured to accept Single-Rail data from the T erminal Equipment.2.If the XRT73L00 is operating in the HOST Mode, then the XRT73L00can be configured to sample the TPDA T A pin on either the rising or fall-ing edge of TCLK.38TNDA T A I Transmit Negative Data Input:The XRT7300 samples this pin on the falling edge of TCLK. If the device sam-ples a “1” at this input pin, then it generates and transmits a negative polaritypulse to the line.N OTES:1.This input pin is ignored and should be tied to GND if the T ransmit Sec-tion is configured to accept Single-Rail data from the T erminal Equip-ment.2.If the XRT7300 is operating in the HOST Mode, then the XRT7300 canbe configured to sample the TNDA T A pin on either the rising or fallingedge of TCLK.39GND-Transmit Analog Ground40TRING O Transmit TIP Output:The XRT7300 uses this pin, along with TTIP, to transmit a bipolar line signal via a1:1 transformer.41TTIP O Transmit RING Output:The XRT7300 uses this pin, along with TRING, to transmit a bipolar line signalvia a 1:1 transformer.42VDD-Transmit Analog Power SupplyPIN DESCRIPTIONP IN#S YMBOL T YPE D ESCRIPTION43MRING I Monitor Ring Input:The bipolar line output signal from TRING can be connected to this pin via a 270Ω resistor in order to check for line driver failure. This pin is internally pulled“High”.44MTIP I Monitor Tip Input:The bipolar line output signal from TTIP can be connected to this pin via a 270 Ωresistor in order to check for line driver failure. This pin is internally pulled “High”.ELECTRICAL CHARACTERISTICSDC ELECTRICAL CHARACTERISTICS (T A = 25°C, V DD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED) S YMBOL P ARAMETER M IN.T YP.M AX.U NITS V DDD DC Supply Voltage 4.755 5.25V V DDA DC Supply Voltage 4.755 5.25VI CC Supply Current (Measured while T ransmitting and Receiving all “1’s”)DS-3 Mode167200mASTS-1 Mode180220mA V IL Input Low Voltage0.8V V IH Input High Voltage 2.0VDD V V OL Output Low Voltage, IOUT = -4.0mA00.4V V OH Output High Voltage, IOUT = 4.0mA 2.8VDD VI L Input Leakage Current*±10mA * Not applicable to pins with pull-up/pull-down resistors.AC ELECTRICAL CHARACTERISTICS (T A = 25°C, V DD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED)S YMBOL P ARAMETER M IN.T YP.M AX.U NITS Terminal Side Timing Parameters (See Figure3 & Figure4)TCLK Clock Duty Cycle (DS3/STS-1)305070%TCLK Clock Duty Cycle (E3)305070%TCLK Frequency (SONET STS-1)51.84MHzTCLK Frequency (DS3)44.736MHzTCLK Frequency (E3)34.368MHz t RTX TCLK Clock Rise Time (10% to 90%)4ns t FTX TCLK Clock Fall Time (90% to 10%)4ns t TSU TPDA T A/TNDA T A to TCLK Falling Set up time3ns t THO TPDA T A/TNDA T A to TCLK Falling Hold time3ns t LCVO RCLK to rising edge of LCV output delay 2.5ns t TDY TTIP/TRING to TCLK Rising Propagation Delay time0.614ns RCLK Clock Duty Cycle455055%RCLK Frequency (SONET STS-1)51.84MHzRCLK Frequency (DS3)44.736MHzRCLK Frequency (E3)34.368MHz。

PC QUICK-FIT FEMALE TERMINALSACCEPTS .110(2.8)TABVERTICAL ENTRYVERTICAL ENTRYACCEPTS .187(4.8)TABVERTICAL ENTRYACCEPTS .110(2.8)TAB HORIZONTAL ENTRYACCEPTS .187(4.8),.205(5.2),.250(6.4)TABSACCEPTS .110(2.8)×.032(.81)TABHORIZONTAL ENTRYMounting DetailMATERIAL:.012(.30)Brass,Tin-Nickel PlateMounting DetailMATERIAL:.016(.41)Brass,Tin-Nickel PlateMATERIAL:Brass,Tin-Nickel PlateMounting DetailMounting DetailMATERIAL:.016(.41)Brass,Tin-Nickel Plate CAT.NO.ACCEPTS TAB 3525.205(5.2)×.020(.51)3575.205(5.2)×.032(.81)CAT.NO.ACCEPTS TAB 3528.250(6.4)×.032(.81).400[10.1].046[1.15] DIA..076[1.9] DIA..400[10.1].067[1.70]DIA..104[2.6]DIA..146[3.7].232[5.9]W (Ref).420[10.7].150[3.8].050[1.25].200[5.1].200[5.1].052[1.30]DIA.CAT.NO.ACCEPTS TAB 3545.110(2.8)×.020(.51)3549.110(2.8)×.032(.81).212[5.4].062[1.55].100[2.5].075[1.90].400[10.2].040[1.00].070[1.80].156[4.0].280[7.1].070 [1.80].125 [3.2].281 [7.1].437[11.1].076[1.90].271 [6.9].120 [3.0].250[6.3]Tel (718)956-8900•Fax (718)956-9040(800)221-5510•kec@31-0720th Road –Astoria,NY 11105-2017RoHS COMPLIANT ~ISO 9001CERTIFIED®Mounting Detail.200[5.1].100[2.54]DIA.Mounting Detail.200[5.1].089[2.3]Mounting Detail.328[8.35].152[3.86]DIA.MATERIAL:.016(.41)Brass,Tin-Nickel PlateACCEPTS .205(5.2)TAB VERTICAL ENTRYACCEPTS .250(6.4)TABCAT.NO.ORIENTATION 3557top &side entry 3577bottom &side entryMATERIAL:.016(.41)Brass,Tin-Nickel PlateMATERIAL:.020(.51)Copper,Tin-Nickel PlateACCEPTS ALL TABS.110(2.8)TO.250(6.4)×.020(.50)TO.032.(.80)VERTICAL OR HORIZONTAL ENTRYSMT -HORIZONTAL ENTRYSMT -VERTICAL OR HORIZONTAL ENTRYACCEPTS .312(7.9)TABOVER SIZED.032[0.8].062[1.6].400[10.2].134[3.4].150[3.8].150[3.8].185[4.7]Underwriters Laboratories,Inc.Recognized Component Program —UL File Number E201546CAT.MATL NO.ACCEPTS TAB “W”“A”THICK 3571.187(4.8)×.020(.51).222(5.6).162(4.1).012(.30)3572.187(4.8)×.032(.81)3546.205(5.2)×.020(.51).240(6.1).180(4.6).012(.30)3550.205(5.2)×.032(.81)3547.250(6.4)×.032(.81).291(7.4).205(5.2).016(.41).392[10.0].180[4.6].422[10.7].375[9.5].109[2.8].106[2.7].578[14.7].180[4.6].144[3.7].065[1.30]DIA.Mounting Detail Cat.No.3557.134[3.4].067[1.7]DIA.(2)PLS.Mounting Detail Cat.No.3577.067[1.7]DIA.(2)PLS.TERMINAL CLEARENCE.040[1.0].134[3.4].062[1.6].212[5.4].062[1.55]W.100[2.5]A.098[2.5].400[10.2].062[1.55].250[6.4]MATERIAL:.012(.30)Brass,Tin-Nickel Plate.050[1.3].125[3.2].281[7.1].437[11.1].091[2.3].291[7.4].110[2.8].250[6.3].086[2.2].062[1.55]W (Ref).440[11.2].156[4.0].144[3.7].125[3.2].196[5.0]CAT.NO.ACCEPTS TAB W 3534.110(2.8)×.020(.51).070(1.80)3544.110(2.8)×.032(.81).075(1.92).312[7.9].090[2.3].250[6.4].100[2.54].075[1.9].105[2.7].156[4.0].150[3.8].242[6.2].282[7.2].062[1.6].100[2.5].185[4.7].250[6.4].176[4.5].067[1.7].252[6.4].067[1.7]TYP..105[2.7]Mounting Detail.100[2.6].105[2.7].312[7.9]Mounting DetailSPECIFICATIONSMaterial:.012(.30)Brass,Tin-Nickel Plate Current Rating:15Amps @500V ACSPECIFICATIONSMaterial:.016(.40)Brass,Tin-Nickel Plate Current Rating:15Amps @500V ACTape &Reel Spec’s:16mm wide,12mm pitch,13inch reel (750pieces per reel)*Low insertion force designTape &Reel Spec’s:24mm wide,8mm pitch,13inch reel (2000pieces per reel)CAT.NO.ACCEPTS TAB “W”3548.187(4.8)×.020(.51).093(2.36)3578*.187(4.8)×.020(.51).093(2.36)3551.187(4.8)×.032(.81).102(2.59)CAT.NO.3569(Bulk)CAT.NO.3569TR (Tape &Reel)CAT.NO.3586TR (Tape &Reel)CAT.NO.3586(Bulk)FEMALE PC QUICK-FIT TERMINALS55ACCEPTS ALL TABS.110(2.8)TO.250(6.4)×.020(.50)TO.032.(.80)CAT.NO.ACCEPTS TAB3555.312(7.9)×.032(.81)35573577/分销商库存信息: KEYSTONE-ELECTRONICS 3577。

66579-7 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer SupportHome > Products > By Type > > 5 amps < 10 amps Circuit Max. > Product Feature Selector > Product Details66579-7Active MultimateAlways EU RoHS/ELV Compliant (Statement of Compliance)Product Highlights:?Pin?Gold (30) Contact Mating Area PlatingMaterial?Wire Range = 0.80-1.40²[18-16] mm[AWG]?Insulation Diameter = 2.03 - 2.54 mm?Brass Contact MaterialView all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:?CONTACT, PIN, STRIP, TYPE VI, MULTIMATE(PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?None AvailableApplication Specifications:?Type VI Insulation Grip Contacts(PDF, English)Instruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Additional Information:?Product Line InformationRelated Products:?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Pin/Socket = Pin?Insulation Diameter (mm [in]) = 2.03 – 2.54[0.080 –0.100]?Product Type = Type VI?Insulation Support = Yes?Wire Termination Type = Crimp?Wire/Cable Type = Discrete Wire?Grade = Commercial?Comment = Wire strip length-- 3.96 [.156] forall wire sizes.Electrical Characteristics:?High Current = NoTermination Related Features:?Termination End Plating = Tin?Pin Diameter (mm [in]) = 1.57 [0.062]Body Related Features:?Wire Range (mm [AWG]) = 0.80-1.40²[18-16] ?Spring Material = Stainless Steel?Used With = G Series Connectors Contact Related Features:?Contact Mating Area Plating Material = Gold(30)?Contact Material = Brass?Contact Size = 16?Contact Type = SignalIndustry Standards:?RoHS/ELV Compliance = RoHS compliant, ELVcompliant?Lead Free Solder Processes = Not relevant forlead free process?RoHS/ELV Compliance History = Always wasRoHS compliantConditions for Usage:?Terminate To = Wire?Test Current (Amps.) = 13.0Packaging Related Features:?Packaging Method = StripOther:?Brand = AMPProvide Website Feedback | Contact Customer Support。

引用标准
DIN 3870 无焊接的和焊接的管接头；锁紧螺母
DIN 73 378 车辆用聚酰胺（尼龙）管
DIN 74 324 第1部分压缩空气制动设备（气刹）；聚酰胺（尼龙）管和管道；
要求，试验
早期的版本
DIN 73 377：08.78, 07.87
修改
本标准和1987年7月版相比有下列修改：
） a) 30°角的公差由30′增加到1°
口径DN3S的圆角半径r2减小到0,3毫米。

b)
补充了DN3, DN3S和DN12S的外形尺寸。

c)
说明
按照DIN 73 377标准生产的这种连接芯管经受了多年实际应用的考验，适用于车辆燃料输送管道和压缩空气制动设备（气刹），
使用DIN74 324 第1部分的管子和按照DIN 73 378 PA11和PA12的管子，以及在允许工作压力和温度下使用的所有管子。

此乃一种可靠、经济和易于控制的连接元件。

为了能确保达到要求的连接强度，这种芯管根据口径大小的不同带有2到4个固定肋槽。

上面的表中按照DIN 2402给出了各种常用口径芯管的外形尺寸。

表面保护
必须注意保护好完工零件的表面，从而确保外形尺寸和公差。

材料
这种连接芯管主要采用金属材料制造而成。

具体采用何种材料可依合同要求来决定。

如果是采用塑料来制造这种芯管，必须经过适用性试验。

不允许采用锁紧套管，软管夹头等紧固元件的原因在于这些元件在和芯管连接的部位和导致塑料管产生冷挤压，从而会降低其强度。

国际专利分类号
F16L 47/00。