S4OP1511_BP_supported_fields

34 .80 7IRELESS IMPORTANT NOTICEDear customer,As from August 2nd2008, the wireless operations of NXP have moved to a new company,ST-NXP Wireless.As a result, the following changes are applicable to the attached document.●Company name - NXP B.V. is replaced with ST-NXP Wireless.●Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. Allrights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.●Web site - is replaced with ●Contact information- the list of sales offices previously obtained by sendingan email to salesaddresses@ , is now found at under Contacts.If you have any questions related to the document, please contact our nearest sales office.Thank you for your cooperation and understanding.ST-NXP Wireless34 .80 7IRELESS1.General descriptionThe ISP1504 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev.2.0,On-The-Go Supplement to the USB 2.0 Specification Rev.1.3 and UTMI+ Low Pin Interface (ULPI) Specification Rev.1.1.The ISP1504 can transmit and receive USB data at high-speed (480Mbit/s), full-speed (12Mbit/s) and low-speed (1.5Mbit/s), and provides a pin-optimized, physical layer front-end attachment to USB host, peripheral and OTG devices.It is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) and any system chip set to interface with the physical layer of the USB through a 12-pin interface.The ISP1504 can interface to the link with digital I/O voltages in the range of 1.65V to 3.6V .The ISP1504 is available in HVQFN32 package.2.FeaturesI Fully complies with:N Universal Serial Bus Specification Rev.2.0N On-The-Go Supplement to the USB 2.0 Specification Rev.1.3N UTMI+ Low Pin Interface (ULPI) Specification Rev.1.1I Interfaces to host,peripheral and OTG device cores;optimized for portable devices or system ASICs with built-in USB OTG device coreI Complete Hi-Speed USB physical front-end solution that supports high-speed (480Mbit/s), full-speed (12Mbit/s) and low-speed (1.5Mbit/s)N Integrated 45Ω±10% high-speed termination resistors, 1.5k Ω±5% full-speed device pull-up resistor, and 15k Ω±5% host termination resistorsN Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive N USB clock and data recovery to receive USB data up to ±500ppmN Insertion of stuff bits during transmit and discarding of stuff bits during receive N Non-Return-to-Zero Inverted (NRZI) encoding and decodingN Supports bus reset, suspend, resume and high-speed detection handshake (chirp)I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)and Session Request Protocol (SRP)ISP1504A; ISP1504CULPI Hi-Speed Universal Serial Bus On-The-Go transceiverRev. 03 — 7 April 2008Product data sheetN Integrated 5V charge pump; also supports external charge pump or 5V V BUSswitchN Complete control over bus resistorsN Data line and V BUS pulsing session request methodsN Integrated V BUS voltage comparatorsN Integrated cable (ID) detectorI Highly optimized ULPI-compliantN60MHz, 8-bit interface between the core and the transceiverN Supports 60MHz output clock configurationN Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:19.2MHz (ISP1504ABS) and 26MHz (ISP1504CBS)N Fully programmable ULPI-compliant register setN Internal Power-On Reset (POR) circuitI Flexible system integration and very low current consumption, optimized for portabledevicesN Power-supply input range is 3.0V to 3.6VN Internal voltage regulator supplies 3.3V and 1.8VN Charge pump regulator outputs 4.75V to 5.25V at a current of up to 50mA,tunable using an external capacitorN Supports external V BUS charge pump or 5V V BUS switch:External V BUS source is controlled using the PSW_N pin; open-drain PSW_Nallows per-port or ganged power controlDigital FAULT input to monitor the external V BUS supply statusN Pin CHIP_SELECT_N 3-states the ULPI interface, allowing bus reuse for otherapplicationsN Supports wide range interfacing I/O voltage of1.65V to3.6V;separate I/O voltagepins minimize crosstalkN Typical operating current of 10mA to 48mA, depending on the USB speed andbus utilization; not including the charge pumpN Typical suspend current of 35µAI Full industrial grade operating temperature range from−40°C to +85°CI4kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, V BUS and GNDI Available in a small HVQFN32 (5mm×5mm) Restriction of Hazardous Substances(RoHS) compliant, halogen-free and lead-free package3.ApplicationsI Digital still cameraI Digital TVI Digital Video Disc (DVD) recorderI External storage device, for example:N Magneto-Optical (MO) driveN Optical drive: CD-ROM, CD-RW, DVDN Zip driveI Mobile phoneI MP3 playerI PDA I Printer I ScannerI Set-T op Box (STB)I Video camera4.Ordering information[1]The package marking is the first line of text on the IC package and can be used for IC identification.Table 1.Ordering informationPartPackageType numberMarkingCrystal or clockfrequency Name DescriptionVersionISP1504ABS 504A [1]19.2MHz HVQFN32plastic thermal enhanced very thin quad flat package;no leads; 32terminals; body 5×5×0.85mm SOT617-1ISP1504CBS504C [1]26MHzHVQFN32plastic thermal enhanced very thin quad flat package;no leads; 32terminals; body 5×5×0.85mmSOT617-15.Block diagramFig 1.Block diagramREGISTER MAPULPI INTERFACE CONTROLLERUSB DATA SERIALIZERUSB DATA DESERIALIZER HI-SPEED USB ATXDMDPSTP DIR NXTDATA [7:0]8452120191, 23 to 26,28, 31, 32004aaa478CLOCK27TERMINATION RESISTORSIDDETECTORV BUSCOMPARATORSON-THE-GO MODULESRP CHARGE AND DISCHARGE RESISTORS5 V CHARGE PUMP SUPPLYPOWER-ON RESETPLLCRYSTAL OSCILLATORVOLTAGE REGULATORBAND GAP REFERENCE VOLTAGERREF3internal powerV CC11REG3V3REG1V81418RESET_NGLOBAL RESETGLOBAL CLOCKSXTAL2XTAL11516V CC(I/O)2, 22, 30interface voltagePSW_NDRV V BUS EXTERNALDRV V BUS ID7V BUS13FAULT 612CPGND810C_A C_B 9ISP150417ULPIINTERFACEUSB CABLEV REFCHIP_SELECT_N29V BUS VALID EXTERNAL6.Pinning information6.1Pinning6.2Pin descriptionFig 2.Pin configuration HVQFN32; top view004aaa479ISP1504T ransparent top viewRESET_N ID CPGNDREG1V8FAULTDIR DP STP DM NXT RREF V CC(I/O)V CC(I/O)DATA7DATA0DATA6C _B C _A V C C P S W _N V B U S R E G 3V 3X T A L 1X T A L 2D A T A 1D A T A 2V C C (I /O )C H I P _S E L E C T _ND A T A 3C L O C KD A T A 4D A T A 58177186195204213222231249101112131415163231302928272625terminal 1index areaTable 2.Pin descriptionSymbol [1][2]Pin Type [3]Description [4]DA T A01I/O pin 0 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down V CC(I/O)2P I/O supply rail RREF 3AI/O resistor referenceDM 4AI/O data minus (D −) pin of the USB cable DP 5AI/O data plus (D+) pin of the USB cableFAULT 6I input pin for the external V BUS digital overcurrent or fault detector signal plain input; 5V tolerantID7Iidentification (ID) pin of the micro-USB cableIf this pin is not used, it is recommended to connect to REG3V3.plain input; TTL levelCPGND 8P charge pump groundC_B 9AI/O flying capacitor pin connection for the charge pump C_A 10AI/O flying capacitor pin connection for the charge pump V CC 11P input supply voltage or battery sourcePSW_N12ODactive LOW external V BUS power switch or external charge pump enable open-drain; 5V tolerant[1]Symbol names ending with an underscore N, for example, NAME_N, indicate active LOW signals.[2]For details on external components required on each pin, see bill of materials and application diagrams in Section 16.[3]I = input; O = output; I/O = digital input/output; OD = open-drain output; AI = analog input; AO = analog output; AI/O = analog input/output; P = power or ground pin.[4]A detailed description of these pins can be found in Section 7.9.V BUS 13AI/O V BUS pin of the USB cable 5V tolerantREG3V314P 3.3V regulator output XTAL115AI crystal oscillator or clock input XTAL216AO crystal oscillator outputRESET_N 17I active LOW, asynchronous reset input plain inputREG1V818P 1.8V regulator output DIR 19O ULPI direction signalslew-rate controlled output (1ns)STP 20I ULPI stop signalplain input; programmable pull up NXT 21O ULPI next signalslew-rate controlled output (1ns)V CC(I/O)22P I/O supply railDAT A723I/O pin 7 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down DAT A624I/O pin 6 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down DAT A525I/O pin 5 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down DAT A426I/O pin 4 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down CLOCK 27O 60MHz clock outputslew-rate controlled output (1ns)DAT A328I/O pin 3 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down CHIP_SELECT_N 29I active LOW chip select plain input V CC(I/O)30P I/O supply railDAT A231I/O pin 2 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull down DAT A132I/O pin 1 of the bidirectional ULPI data busslew-rate controlled output (1ns); plain input; programmable pull downGNDdie padPground supply;down bonded to the exposed die pad (heat sink);to be connected to the PCB groundTable 2.Pin description …continuedSymbol [1][2]Pin Type [3]Description [4]7.Functional description7.1ULPI interface controllerThe ISP1504 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface(ULPI) Specification Rev.1.1. This interface must be connected to the USB link.The ULPI interface controller provides the following functions:•ULPI-compliant interface and register set•Allows full control over the USB peripheral, host and OTG functionality•Parses the USB transmit and receive data•Prioritizes the USB receive data,USB transmit data,interrupts and register operations•Low-power mode•Control of the V BUS charge pump or external source•V BUS monitoring, charging and discharging•6-pin serial mode and 3-pin serial mode•Generates RXCMDs; status updates•Maskable interrupts•Control over the ULPI bus state, allowing pins to 3-state or attach active weakpull-down resistorsFor more information on the ULPI protocol, see Section9.7.2USB data serializer and deserializerThe USB data serializer prepares data to transmit on the USB bus. To transmit data, theUSB link sends a transmit command and data on the ULPI bus. The serializer performsparallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, theserializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the endof the packet. When the serializer is busy and cannot accept any more data, the ULPIinterface controller deasserts NXT.The USB data deserializer decodes data received from the USB bus. When data isreceived, the deserializer strips the SYNC and EOP patterns, and then performsserial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the datapayload. The ULPI interface controller sends data to the USB link by asserting DIR, andthen asserting NXT whenever a byte is ready. The deserializer also detects variousreceive errors, including bit stuff errors, elasticity buffer underrun or overrun, andbyte-alignment errors.7.3Hi-Speed USB (USB2.0) ATXThe Hi-Speed USB ATX block is an analog front-end containing the circuitry needed totransmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, forUSB peripheral, host and OTG implementations. The following circuitry is included:•Differential drivers to transmit data at high-speed, full-speed and low-speed•Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed•Squelch circuit to detect high-speed bus activity•High-speed disconnect detector•45Ω high-speed bus terminations on DP and DM for peripheral and host modes• 1.5kΩ pull-up resistor on DP for full-speed peripheral mode•15kΩ bus terminations on DP and DM for host and OTG modesFor details on controlling resistor settings, see Table8.7.4Voltage regulatorThe ISP1504 contains a built-in voltage regulator that conditions the V CC supply for use inside the ISP1504. The voltage regulator:•Supports input supply range of 3.0V<V CC<3.6V•Supplies internal circuitry with 1.8V and 3.3VRemark:The REG1V8 and REG3V3 pins require external decoupling capacitors. Fordetails, see Section16.7.5Crystal oscillator and PLLThe ISP1504 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock generation.The crystal oscillator takes a sine-wave input from an external crystal, on the XTAL1 pin, and converts it to a square wave clock for internal use. Alternatively, a square wave clock of the same frequency can also be directly driven into the XTAL1 pin. Using an existing square wave clock can save the cost of the crystal and also reduce the board size.The PLL takes the square wave clock from the crystal oscillator,and multiplies or divides it into various frequencies for internal use.The PLL produces the following frequencies, irrespective of the clock source:•60MHz clock for the ULPI interface controller• 1.5MHz for the low-speed USB data•12MHz for the full-speed USB data•480MHz for the high-speed USB data•Other internal frequencies for data conversion and data recovery7.6OTG moduleThis module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits:•The ID detector to sense the ID pin of the micro-USB cable.The ID pin dictates which device is initially configured as the host and which as the peripheral.•V BUS comparators to determine the V BUS voltage level. This is required for the V BUS detection, SRP and HNP.•Resistors to temporarily charge and discharge V BUS. This is required for SRP.•Charge pump to provide5V power on V BUS.The downstream peripheral can draw its power from the ISP1504 V BUS.7.6.1ID detectorThe ID detector detects which end of the micro-USB cable is plugged in. The detectormust first be enabled by setting the ID_PULLUP register bit to logic1. If the ISP1504senses a value on ID that is different from the previously reported value, an RXCMDstatus update will be sent to the USB link, or an interrupt will be asserted.•If the micro-B end of the cable is plugged in, the ISP1504 will report that ID_GND is logic1. The USB link must change to peripheral mode.•If the micro-A end of the cable is plugged in, the ISP1504 will report that ID_GND is logic0. The USB link must change to host mode.7.6.2V BUS comparatorsThe ISP1504 provides three comparators, V BUS valid comparator, session validcomparator and session end comparator, to detect the V BUS voltage level.7.6.2.1V BUS valid comparatorThis comparator is used by hosts and A-devices to determine whether the voltage onV BUS is at a valid level for operation. The ISP1504 minimum threshold for the V BUS validcomparator is V A_VBUS_VLD.Any voltage on V BUS below V A_VBUS_VLD is considered invalid.During power-up, it is expected that the comparator output will be ignored.7.6.2.2Session valid comparatorThe session valid comparator is a TTL-level input that determines when V BUS is highenough for a session to start.Peripherals,A-devices and B-devices use this comparator to detect when a session is started. The A-device also uses this comparator to determinewhen a session is completed.The session valid threshold of the ISP1504is V B_SESS_VLD, with a hysteresis of V hys(B_SESS_VLD).7.6.2.3Session end comparatorThe ISP1504 session end comparator determines when V BUS is below the B-devicesession end threshold.The B-device uses this threshold to determine when a session has ended. The session end threshold of the ISP1504 is V B_SESS_END.7.6.3SRP charge and discharge resistorsThe ISP1504 provides on-chip resistors for short-term charging and discharging of V BUS.These are used by the B-device to request a session, prompting the A-device to restorethe V BUS power. First, the B-device makes sure that V BUS is fully discharged from theprevious session by setting the DISCHRG_VBUS register bit to logic1 and waiting forSESS_END to be logic1. Then the B-device charges V BUS by setting the CHRG_VBUSregister bit to logic1. The A-device sees that V BUS is charged above the session validthreshold and starts a session by turning on the V BUS power.7.6.4Charge pumpThe ISP1504 uses a built-in charge pump to supply current to V BUS at a nominal voltage of 5V . The charge pump works as a capacitive DC-DC converter. An external holding capacitor,C cp(C_A)-(C_B),is required between the C_A and C_B pins as shown in Figure 3,which also shows a typical OTG V BUS load. The value of C cp(C_A)-(C_B) depends on the amount of current drive required.If the internal charge pump is not used,the C cp(C_A)-(C_B)capacitor is not required.For details on the C_A and C_B pins, see Section 7.9.8.7.7Band gap reference voltageThe band gap circuit provides a stable internal voltage reference to bias the analogcircuitry.The band gap requires an accurate external reference resistor R RREF connected between the RREF and GND pins. For details, see Section 16.7.8Power-On Reset (POR)The ISP1504 has an internal power-on reset circuit that resets all internal logic on power-up. The ULPI interface is also reset on power-up.Remark:When CLOCK starts toggling after power-up, the USB link must issue a reset command over the ULPI bus to ensure correct operation of the ISP1504.7.9Detailed description of pins7.9.1DATA[7:0]The ISP1504 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is the bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is idle. When the link has data to transmit to the PHY , it drives a nonzero value.The data bus can be reconfigured to carry various data types, as given in Section 8 and Section 9.The DA TA[7:0] pins can be 3-stated by driving pin CHIP_SELECT_N to HIGH. Weakpull-down resistors are incorporated into the DATA[7:0]pins as part of the interface protect feature. For details, see Section 9.3.1.Fig 3.External capacitors connection004aaa515ISP1504V BUSC_BC_AC cp(C_A)-(C_B)OTG V BUS4.7 µF0.1 µF7.9.2V CC(I/O)The input power pin that sets the I/O voltage level.For details,see Section12,Section13 and Section16. V CC(I/O) provides power to on-chip pads of the following pins:•CHIP_SELECT_N•CLOCK•DAT A[7:0]•DIR•NXT•RESET_N•STP7.9.3RREFResistor reference analog I/O pin. A resistor, R RREF, must be connected between RREF and GND, as shown in Section16. This provides an accurate voltage reference thatbiases internal analog circuitry.Less accurate resistors cannot be used and will render the ISP1504 unusable.7.9.4DP and DMThe DP (data plus) and DM (data minus) are USB differential data pins. These must beconnected to the D+ and D− pins of the USB receptacle.7.9.5FAULTIf an external V BUS overcurrent or fault circuit is used, the output fault indicator of thatcircuit can be connected to the ISP1504FAULT input pin.The ISP1504will inform the link of V BUS fault events by sending RXCMDs on the ULPI bus.To use the FAULT pin,the link must:•Set the USE_EXT_VBUS_IND register bit to logic1.•Set the polarity of the external fault signal using the IND_COMPL register bit.•Set the IND_P ASSTHRU register bit to logic1.If the FAULT pin is not used, it is recommended to connect to GND.7.9.6IDFor OTG implementations, the ID (identification) pin is connected to the ID pin of themicro-USB receptacle.As defined in On-The-Go Supplement to the USB2.0Specification Rev.1.3, the ID pin dictates the initial role of the link. If ID is detected as HIGH, the linkmust assume the role of a peripheral. If ID is detected as LOW, the link must assume ahost role. Roles can be swapped at a later time by using HNP.If the ISP1504is not used as an OTG PHY,but as a standard USB host or peripheral PHY, the ID pin must be connected to REG3V3.7.9.7CPGNDCPGND indicates the analog ground for the on-board charge pump.CPGND must always be connected to ground, even when the charge pump is not used.7.9.8C_A and C_BThe C_A and C_B pins are to connect the flying capacitor of the charge pump.The output current capability of the charge pump depends on the value of the capacitor used, as shown in T able 3. For maximum efficiency, place capacitors as close as possible to pins.For details, see Section 16.If the charge pump is not used, C_A and C_B must be left floating (not connected).7.9.9V CCV CC is the main input supply voltage for the ISP1504. Decoupling capacitors are recommended. For details, see Section 16.7.9.10PSW_NPSW_N is an active LOW, open-drain output pin. This pin can be connected to an active LOW, external V BUS switch or charge pump enable circuit to control the external V BUSpower source.An external pull-up resistor,R pullup ,is required when PSW_N is used.This pin is open-drain, allowing ganged-mode power control for multiple USB ports. For application details, see Section 16.If the link is in host mode, it can enable the external V BUS power source by setting the DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1504 will drive PSW_N to LOW to enable the external V BUS power source. If the link detects anovercurrent condition (the V BUS state in RXCMD is not 11b), it must disable the external V BUS power source by setting DRV_VBUS_EXT to logic 0.7.9.11V BUSThis pin acts as an input to V BUS comparators, and also as a power pin for the charge pump, and SRP charge and discharge resistors.When the DRV_VBUS bit of the OTG Control register is set to logic 1,the ISP1504drives V BUS to a voltage of 4.4V to 5.25V , with a minimum output current capability of 8mA.The V BUS pin requires a capacitive load as shown in Section 16.Fig 4.Charge pump capacitorTable 3.Recommended charge pump capacitor valueC cp(C_A)-(C_B)I L (max)22nF 8mA 270nF50mA004aaa516I LISP1504V BUSC_A C_BC cp(C_A)-(C_B)To prevent electrical overstress, it is strongly recommended that you attach a seriesresistor on the V BUS pin (R VBUS). R VBUS must not be attached when using the ISP1504internal charge pump. For details, see Section16.7.9.12REG3V3 and REG1V8Regulator output voltage. These supplies are used to power the ISP1504 internal digitaland analog circuits, and must not be used to power external circuits.For correct operation of the regulator, it is recommended that you connect REG3V3 andREG1V8 to decoupling capacitors. For examples, see Section16.7.9.13XTAL1 and XTAL2XT AL1is the crystal input,and XT AL2is the crystal output.The allowed frequency on the XT AL1 pin depends on the ISP1504 product version.If the link requires a 60MHz clock from the ISP1504, then either a crystal must beattached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 leftfloating.If a crystal is attached,it requires external load capacitors to GND on each terminal of the crystal. For details, see Section16.If at any time the system wants to stop the clock on XTAL1, the link must first put theISP1504 into low-power mode. The clock on XTAL1 must be restarted before low-powermode is exited.7.9.14RESET_NAn active LOW asynchronous reset pin that resets all circuits in the ISP1504. TheISP1504 contains an internal power-on reset circuit, and therefore using the RESET_Npin is optional. If RESET_N is not used, it must be connected to V CC(I/O).For details on using RESET_N, see Section9.3.2.7.9.15DIRULPI direction output pin. Controls the direction of the data bus. By default, the ISP1504holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1504listens for data from the link. The ISP1504 pulls DIR to HIGH only when it has data tosend to the link, which is for one of two reasons:•To send the USB receive data,RXCMD status updates and register reads data to the link.•To block the link from driving the data bus during power-up, reset and low-power (suspend) mode.The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev.1.1.7.9.16STPULPI stop input pin. The link must assert STP to signal the end of a USB transmit packetor a register write operation. When DIR is asserted, the link can optionally assert STP toabort the ISP1504, causing it to deassert DIR in the next clock cycle. A weak pull-upresistor is incorporated into the STP pin as part of the interface protect feature.For details, see Section9.3.1.The STP input will be ignored when CHIP_SELECT_N is driven to HIGH.For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev.1.1.7.9.17NXTULPI next data output pin.The ISP1504holds NXT at LOW,by default.When DIR is LOW and the link is sending data to the ISP1504, NXT will be asserted to notify the link toprovide the next data byte. When DIR is at HIGH and the ISP1504 is sending data to thelink,NXT will be asserted to notify the link that another valid byte is on the bus.NXT is not used for register read data or the RXCMD status update.The NXT pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.For details on NXT usage,refer to UTMI+Low Pin Interface(ULPI)Specification Rev.1.1.7.9.18CLOCKA 60MHz interface clock to synchronize the ULPI bus. The ISP1504 provides twoclocking options:• A crystal is attached between the XT AL1 and XTAL2 pins.• A clock is driven into the XT AL1 pin, with the XTAL2 pin left floating.For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) SpecificationRev.1.1.7.9.19CHIP_SELECT_NActive LOW chip select pin. If CHIP_SELECT_N is not used, it must be connected toGND. For more information on using CHIP_SELECT_N, see Section9.3.3.7.9.20GND (die pad)Global ground signal, except for the charge pump that uses CPGND. The die pad isexposed on the underside of the package as a ground plate. This acts as a ground to allcircuits in the ISP1504, except the charge pump. To ensure correct operation of theISP1504, GND must be soldered to the cleanest ground available.。

f in eo nIn fio nI n fTechnical Committee SD Card Associationf in eo nIn fi ne o n I nf in eo nIRevision HistoryDate Version Changes compared to previous issueApril 3, 2006 1.10 Simplified Version Initial ReleaseFebruary 8, 20072.00(1) Added method to change bus speed (Normal Speed up to 25MHzand High Speed up to 50 MHz)(2) Operational Voltage Requirement is extended to 2.7-3.6V(3) Combine sections 12 (Physical Properties) and 13 (MechanicalExtensions) and add miniSDIO to the new section 13 (Physical Properties)(4) Add Embedded SDIO ATA Standard Function Interface Code (5) Reference of Physical Ver2.00 supports SDHC combo card. (6) Some typos in Ver1.10 are fixed.f in eo nIn fi ne o n I nf in eo nI Release of SD Simplified SpecificationThe following conditions apply to the release of the SD simplified specification ("Simplified Specification") by the SD Card Association. The Simplified Specification is a subset of the complete SD Specification which is owned by the SD Card Association.Publisher:SD Association2400 Camino Ramon, Suite 375 San Ramon, CA 94583 USA Telephone: +1 (925) 275-6615 Fax: +1 (925) 886-4870 E-mail: office@Copyright Holder: The SD Card AssociationNotes:This Simplified Specification is provided on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified Specification may require a license from the SD Card Association or other third parties.Disclaimers:The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any representations or warranties of any kind. No responsibility is assumed by the SD Card Association for any damages, any infringements of patents or other right of the SD Card Association or any third parties, which may result from its use. No license is granted by implication, estoppel or otherwise under any patent or other rights of the SD Card Association or any third party. Nothing herein shall be construed as an obligation by the SD Card Association to disclose or distribute any technical information, know-how or other confidential information to any third party.f in eo nIn fi ne o n I nf in eo nConventions Used in This DocumentNaming ConventionsSome terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Numbers and Number BasesHexadecimal numbers are written with a lower case “h” suffix, e.g., FFFFh and 80h. Binary numbers are written with a lower case “b” suffix (e.g., 10b).Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.All other numbers are decimal.Key WordsMay: Indicates flexibility of choice with no implied recommendation or requirement.Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation.Application NotesSome sections of this document provide guidance to the host implementers as follows: Application Note:This is an example of an application note.f in eo nIn fi ne o n I nf in eo nTable of Contents1. General Description.................................................................................................................................1 1.1 SDIO Features....................................................................................................................................1 1.2 Primary Reference Document.............................................................................................................1 1.3 Standard SDIO Functions....................................................................................................................1 2. SDIO Signaling Definition........................................................................................................................2 2.1 SDIO Card Types................................................................................................................................2 2.2 SDIO Card modes...............................................................................................................................2 2.2.1 SPI (Card mandatory support).....................................................................................................2 2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support).............................................................2 2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed).........2 2.3 SDIO Host Modes...............................................................................................................................2 2.4 Signal Pins..........................................................................................................................................3 3. SDIO Card Initialization............................................................................................................................4 3.1 Differences in I/O card Initialization.....................................................................................................4 3.2 The IO_SEND_OP_COND Command (CMD5).................................................................................10 3.3 The IO_SEND_OP_COND Response (R4)........................................................................................11 3.4 Special Initialization considerations for Combo Cards.......................................................................12 3.4.1 Re-initialize both I/O and Memory..............................................................................................12 3.4.2 Using a Combo Card as SDIO only or SD Memory only after Combo Initialization....................12 3.4.3 Acceptable Commands after Initialization..................................................................................12 3.4.4 Recommendations for RCA after Reset.....................................................................................12 3.4.5 Enabling CRC in SPI Combo Card.............................................................................................14 4. Differences with SD Memory Specification..........................................................................................15 4.1 SDIO Command List.........................................................................................................................15 4.2 Unsupported SD Memory Commands...............................................................................................15 4.3 Modified R6 Response......................................................................................................................16 4.4 Reset for SDIO..................................................................................................................................16 4.5 Bus Width..........................................................................................................................................16 4.6 Card Detect Resistor.........................................................................................................................17 4.7 Timings..............................................................................................................................................17 4.8 Data Transfer Block Sizes.................................................................................................................18 4.9 Data Transfer Abort...........................................................................................................................18 4.9.1 Read Abort.................................................................................................................................18 4.9.2 Write Abort.................................................................................................................................18 4.10 Changes to SD Memory Fixed Registers..........................................................................................18 4.10.1 OCR Register.............................................................................................................................19 4.10.2 CID Register...............................................................................................................................19 4.10.3 CSD Register.............................................................................................................................19 4.10.4 RCA Register.............................................................................................................................19 4.10.5 DSR Register.............................................................................................................................19 4.10.6 SCR Register.............................................................................................................................19 4.10.7 SD Status...................................................................................................................................19 4.10.8 Card Status Register..................................................................................................................19 5. New I/O Read/Write Commands............................................................................................................21 5.1 IO_RW_DIRECT Command (CMD52)..............................................................................................21 5.2 IO_RW_DIRECT Response (R5)......................................................................................................22 5.2.1 CMD52 Response (SD modes)..................................................................................................22 5.2.2 R5, IO_RW_DIRECT Response (SPI mode).............................................................................23 5.3 IO_RW_EXTENDED Command (CMD53). (24)f in eo nIn fi ne o n I nf in eo nI 5.3.2 Special Timing for CMD53 Multi-Block Read..............................................................................25 6. SDIO Card Internal Operation................................................................................................................26 6.1 Overview...........................................................................................................................................26 6.2 Register Access Time........................................................................................................................26 6.3 Interrupts...........................................................................................................................................26 6.4 Suspend/Resume..............................................................................................................................27 6.5 Read Wait..........................................................................................................................................27 6.6 CMD52 During Data Transfer............................................................................................................27 6.7 SDIO Fixed Internal Map...................................................................................................................27 6.8 Common I/O Area (CIA)....................................................................................................................28 6.9 Card Common Control Registers (CCCR).........................................................................................28 6.10 Function Basic Registers (FBR)........................................................................................................35 6.11 Card Information Structure (CIS).......................................................................................................37 6.12 Multiple Function SDIO Cards...........................................................................................................37 6.13 Setting Block Size with CMD53.........................................................................................................37 6.14 Bus State Diagram............................................................................................................................38 7. Embedded I/O Code Storage Area (CSA).............................................................................................39 7.1 CSA Access.......................................................................................................................................39 7.2 CSA Data Format..............................................................................................................................39 8. SDIO Interrupts.......................................................................................................................................40 8.1 Interrupt Timing.................................................................................................................................40 8.1.1 SPI and SD 1-bit Mode Interrupts ..............................................................................................40 8.1.2 SD 4-bit Mode............................................................................................................................40 8.1.3 Interrupt Period Definition ..........................................................................................................40 8.1.4 Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional)..........................................40 8.1.5 Inhibited Interrupts (Removed Section)......................................................................................40 8.1.6 End of Interrupt Cycles...............................................................................................................40 8.1.7 Terminated Data Transfer Interrupt Cycle ..................................................................................41 8.1.8 Interrupt Clear Timing.................................................................................................................41 9. SDIO Suspend/Resume Operation........................................................................................................42 10. SDIO Read Wait Operation.....................................................................................................................43 11. Power Control.........................................................................................................................................44 11.1 Power Control Overview....................................................................................................................44 11.2 Power Control support for SDIO Cards.............................................................................................44 11.2.1 Master Power Control ................................................................................................................44 11.2.2 Power Selection.........................................................................................................................45 11.2.3 High-Power Tuples.....................................................................................................................45 11.3 Power Control Support for the SDIO Host.........................................................................................45 11.3.1 Version 1.10 Host.......................................................................................................................45 11.3.2 Power Control Operation............................................................................................................46 12. High-Speed Mode...................................................................................................................................47 12.1 SDIO High-Speed Mode....................................................................................................................47 12.2 Switching Bus Speed Mode in a Combo Card...................................................................................47 13. SDIO Physical Properties......................................................................................................................48 13.1 SDIO Form Factors...........................................................................................................................48 13.2 Full-Size SDIO ..................................................................................................................................48 13.3 miniSDIO...........................................................................................................................................48 14. SDIO Power.............................................................................................................................................48 14.1 SDIO Card Initialization Voltages......................................................................................................48 14.2 SDIO Power Consumption................................................................................................................48 15. Inrush Current Limiting..........................................................................................................................50 16. CIS Formats.. (51)f in eo nIn fi ne o n I nf in eo nI 16.2 Basic Tuple Format and Tuple Chain Structure.................................................................................51 16.3 Byte Order Within Tuples ..................................................................................................................51 16.4 Tuple Version ....................................................................................................................................52 16.5 SDIO Card Metaformat......................................................................................................................52 16.6 CISTPL_MANFID: Manufacturer Identification String Tuple..............................................................53 16.7 SDIO Specific Extensions..................................................................................................................53 16.7.1 CISTPL_FUNCID: Function Identification Tuple.........................................................................53 16.7.2 CISTPL_FUNCE: Function Extension Tuple..............................................................................54 16.7.3 CISTPL_FUNCE Tuple for Function 0 (common).......................................................................54 16.7.4 CISTPL_FUNCE Tuple for Function 1-7....................................................................................55 16.7.5 CISTPL_SDIO_STD: Function is a Standard SDIO Function.....................................................58 16.7.6 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards...............................................................58 Appendix A.....................................................................................................................................................59 A.1 SD and SPI Command List....................................................................................................................59 Appendix B.....................................................................................................................................................61 B.1 Normative References...........................................................................................................................61 Appendix C.....................................................................................................................................................62 C.1 Abbreviations and Terms...................................................................................................................62 Appendix D.. (64)f in eo nIn fi ne o n I nf in eo nI Table of TablesTable 3-1 OCR Values for CMD5.....................................................................................................................10 Table 4-1 Unsupported SD Memory Commands.............................................................................................16 Table 4-2 R6 response to CMD3.....................................................................................................................16 Table 4-3 SDIO R6 Status Bits.........................................................................................................................16 Table 4-4 Combo Card 4-bit Control................................................................................................................17 Table 4-5 Card Detect Resistor States.............................................................................................................17 Table 4-6 is blanked.........................................................................................................................................17 Table 4-7 SDIO Status Register Structure .......................................................................................................20 Table 5-1 Flag data for IO_RW_DIRECT SD Response..................................................................................23 Table 5-2 IO_RW_ EXTENDED command Op Code Definition.......................................................................24 Table 5-3 Byte Count Values ...........................................................................................................................25 Table 6-1 Card Common Control Registers (CCCR).......................................................................................29 Table 6-2 CCCR bit Definitions........................................................................................................................34 Table 6-3 Function Basic Information Registers (FBR)....................................................................................35 Table 6-4 FBR bit and field definitions.............................................................................................................36 Table 6-5 Card Information Structure (CIS) and reserved area of CIA.............................................................37 Table 11-1 Reference Tuples by Master Power Control and Power Select......................................................45 Table 16-1 Basic Tuple Format........................................................................................................................51 Table 16-2 Tuples Supported by SDIO Cards..................................................................................................52 Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple.....................................................................53 Table 16-4 CISTPL_FUNCID Tuple.................................................................................................................53 Table 16-5 CISTPL_FUNCE Tuple General Structure.....................................................................................54 Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (common)....................................................................54 Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (common).................................................54 Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7..................................................................................55 Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7.............................................................57 Table 16-10 TPLFE_FUNCTION_INFO Definition...........................................................................................57 Table 16-11 TPLFE_CSA_PROPERTY Definition...........................................................................................57 Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards................................................................58 Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards.................................................................58 Table A-14 SD Mode Command List................................................................................................................59 Table A-15 SPI Mode Command List (60)f in eo nIn fi ne o n I nf in eo nI Table of FiguresFigure 2-1 Signal connection to two 4-bit SDIO cards.......................................................................................3 Figure 3-1 SDIO response to non-I/O aware initialization..................................................................................4 Figure 3-2 Card initialization flow in SD mode (SDIO aware host)....................................................................7 Figure 3-3 Card initialization flow in SPI mode (SDIO aware host)....................................................................9 Figure 3-4 IO_SEND_OP_COND Command (CMD5).....................................................................................10 Figure 3-5 Response R4 in SD mode...............................................................................................................11 Figure 3-6 Response R4 in SPI mode..............................................................................................................11 Figure 3-7 Modified R1 Response....................................................................................................................11 Figure 3-8 Re-Initialization Flow for I/O Controller...........................................................................................13 Figure 3-9 Re-Initialization Flow for Memory controller ...................................................................................13 Figure 5-1 IO_RW_DIRECT Command...........................................................................................................21 Figure 5-2 R5 IO_RW_DIRECT Response (SD modes)..................................................................................22 Figure 5-3 IO_RW_DIRECT Response in SPI Mode.......................................................................................23 Figure 5-4 IO_RW_EXTENDED Command.....................................................................................................24 Figure 6-1 SDIO Internal Map..........................................................................................................................28 Figure 6-2 State Diagram for Bus State Machine (38)f in eo nIn fi ne o n I nf in eo nI 1. General DescriptionThe SDIO (SD Input/Output) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host shall cause no physical damage or disruption of that host or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card proceeds via the normal means described in this specification with some extensions. In this state, the SDIO card is idle and draws a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO card. The host software then obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. This decision is based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into it.1.1 SDIO Features• Targeted for portable and stationary applications• Minimal or no modification to SD Physical bus is required • Minimal change to memory driver software• Extended physical form factor available for specialized applications • Plug and play (PnP) support• Multi-function support including multiple I/O and combined I/O and memory • Up to 7 I/O functions plus one memory supported on one card. • Allows card to interrupt host• Operational Voltage range: 2.7-3.6V (Operational Voltage is used for Initialization) • Application Specifications for Standard SDIO Functions. • Multiple Form Factors:• Full-Size SDIO • miniSDIO1.2 Primary Reference DocumentThis specification is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1 PHYSICAL LAYER SPECIFICATION Version 2.00 May 9, 2006The reader is directed to this document for more information on the basic operation of SD cards. In addition, other documents are referenced in this specification. A complete list can be found in appendix B.1.This specification can apply to any released versions of Physical Layer Specification after Version 2.00.1.3 Standard SDIO FunctionsAssociated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. These common functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. Implementation of the standard interfaces are optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications which will increase the appeal of these cards to the consumer. Full information on these standard interfaces can be found in the Application Specifications for Standard SDIO Functions maintained by the SDA.。

CODE ENGLISH CONTENT CHINA CONTENTO2Verify Real Mode校验实模式O3Disable Non-Maskable Internupt(NMI)放弃非屏蔽中断O4Get CPU type获得CPU类型O6Initialize system hardware 初始化系统硬件O7Disable shadow and execute code from the ROM放弃映射和从只读存储器执行代码 O8Initalize chipset with initial POST valucs用初始自检值初始化芯片组O9Set IN POST flag置入自检标示OA Initilize CPU registers初始化CPU 寄存器OB Enable CPU Cache激活CPU缓存OC Initialize caches to initial POST values用初始自检值初始化缓存OE Initialize I/O component初始化输入,输出组件OF Initialize the local bus IDE初始化局部总线IDE 10Initialize Power Management初始化电源管理11Load alternate registers with initial POST values用自检初始值加载替换寄存器12Restore CPU control word during warm boot恢复CPU控制字在热启动时13Initialize PCI BUS Mastering devices初始化PCI总线主设备14Initialize Keyboard controller初始化键盘控制器16BIOS ROM checksum BIOS ROM求校验和17Iinitalize cache before memory Auto size在内存自动排序初始化缓存188254 timer initialization8254时钟计数器初始化1A8237 DMA controller initilzation8237DMA控制器初始化1C Reset Programmable Intemupt conntpller重置可编程中断请求控制器20Test DRAM refresh测试DRAM刷新22Test 8742 Keyboard Conntroller测试8742键盘控制器24Set ES segment register to 4 GB设置ES段寄存器达４ＧＢ28Auto size DRAM自动测试DRAM容量29Initialize POST Memory Manager初始化自检内存管理器2A Clear 512 KB base RAM512KB基本内存清零2C RAM failure on address line RAM失败在某地址线2E RAM failure on data bits of low byte of memory bus RAM失败在存储总线低位某数据位 2F Enable cache before system BIOS shadow激活缓存在系统BIOS映射前32Test CPUbus-clock freguency测试CPU 总线时钟频率33Initialize Phoenix Dispatch Manager初始化凤凰分派管理器36Warm start shut down热启动关机38Shadow system BIOS ROM映射系统BIOS ROM3A Auto size cache自动测试缓存容量3C Advanced configuration of chipset registers芯片组寄存器高级配置3D Load altrnate registers with CMOS values用CMOS值加载交换寄存器41Initialize extended memory for RomPilot为ROM引导初始化扩展存储器42Initialize interrupt vectors初始化中断向量45POST device initialization自检设备初始化46Check ROMcopyright notice检查ROM版权提示47Initialize 120 support初始化120支援48Check video configuration against CMOS检查区别于CMOS的显存配置49Initialize PCI bus and devices初始化PCI总线及设备4A Initialize all video adapters in system初始化所有系统内的显示适配器 4B QuietBoot start (optional)冷启动开始4C Shadow video BIOS ROM映射ROM内显示BIOS4E Display BIOS copyright notice显示BIOS 版权提示4F Initialize MultiBoot初始化多启动52Test Keyboard测试键盘54Set key click if enabled激活后设置键控响声55Enable USB devices激活USB设备58Test for unexpected interrupts测试意外中断59Initialize POST display service初始化自检显示服务5A Display prompt press F2 to enter SETUP显示DOS提示按F2进入设置5B Disable CPU cache放弃CPU缓存5C Test RAM between 512 and 640 KB测试RAM从512至640KB 60Test extended memory测试扩展存储器62Test ectended memory address lines测试扩展内存地址线64Jump to UserPatch1跳至用户补丁区166Configure advanced cache registers配置高级缓存寄存器67Initialize Multi Processor APIC初始化多处理器APIC68Enable external and CPU caches激活外接和CPU缓存69Display system Management Mode (SMM)area显示系统管理模式区6A Display external L2 cache size 显示外接L2缓存容量6B Load custom defaults(optional)加载用户默认值6C Dislay shadow-area message显示映射区信息6E Display possible high address for UMB recover显示可能的高端地址为UMB恢复使用70Display error messages显示错误信息72Check for configuation errors检测配置偏差76Check for keyboard errors检测键盘错误7C Set up tard ware interrupt vectors设置硬件中断向量7D Initialize Intelligent System Monitoring初始化智能系统跟踪7E Initialize coprocessor if present如果存在,初始化协处理器80Disable onboard Super I/O ports and IRQS放弃板上的超级输入输出端口及IRQS 81Late POST device initialization最后自检设备的初始化82Detect and install extemal RS232 ports侦测安装外接RS232端口83Configure non-MCD IDE controllers配置NON-MCD IDE控制器84Detect and installextermal parallel ports侦测安装外接并行端口85Initialize PC-compatible PnP ISA devices初始化兼容PC即插即用ISA设备86Re-initialize onblard I/O Ports重初始化板上的输入输出端口87Configure Motherboard Configurable Devices(optional)配置M/B可配置设备88Initializ BIOS Data area BOIS数据区初始化89Enable mon-maskable inteerupts[NMIS]激活非屏蔽中断请求8A Initializ Extended Bios Data Area扩展BIOS数据区初始化8b Test and initialize PS/2 mouse测试和初始化PS/2端口8C Initialize floppy controller初始化软驱控制器8F Determine number of ATA drives (optional)测试ATA驱动器数量90Initialize hard-disk controllers初始化硬盘驱控制器91Initialize local-bus bard-disk countrollers初始化局部总线上的硬盘控制器92Jump to Userpatch2跳至用户补丁区93Build MPTABLE for multi-processor boards为多处理器板建立多处理器列表95Install CD-ROM for boot为启动安装CD-ROM96Clear hUge ES segment register清空大量ES段寄存器97Fix up Multi Procssor table设置多处理器列表98Scarch for option ROMs,One long,授索可选只读存储器，一长，二two short beeps on checksum failure短嗡鸣声，在校验失败时99Check for SMART Drive(optional)检查SMART驱动器9A Shadow option ROMs映射选定的只读存储器9C Set up power Management设置电源管理9D Initialize security engine(oprional)初始化安防措施9E Enable bardware interrupts激活硬件中断9F Determine number of ATA and SCDI drives 检测A/A和SCDI设备数量A0Set time or day设置时间和日期A2Check key lock检查锁定键A4Initialize typebatic rateA8Erase F2 prompt清除F2提示AA Scan for F2 key stroke扫描有无F2键按下AC Enter SETUP进入设置AE clear boot flag清除启动标志B0Check for errors检查错误B1Inform Rom pilot about the end of POST通知只读存储器在自检结束后引导系统 B2POST done-prepare to boot operating system自检结束准备起动系统B4One short beep before boot起动前一个短嗡鸣声B5Terminate QuietBoot(optional)结束冷启动B6Check passwont(potional)检验密码B7Initialize ACPIBIOS初始化ACPIBIOSB9Prepare Boot准备启动BA Initialize SMBIOS初始化SMBIOSBB Initialize PuP Option ROMs初 始化即插即用只读存储器BC Clear parity checkers清零奇偶校验检测BD Display MultiBoot menu显示多启动菜单BE Clear screen (Optional)清空显示屏BF Check virus and backup reminders检查病毒备份提示C0Try to boot with INT 19试用INT 19启动C1Initialize POST Error Manager初始化自检管理C2Initialize error logging初始化错误日志C3Initialize error display function初始化错误显示功能C4Initialize system error bandler初始化系统错误处理C5PnPnd dual CMOS(optional)C6Initialize note disk (optional)C7Initialize note dock lateC8Force check(optional)强行检查CC Redirect Int 10h to ENable remote serial video重指示INT 10去激活远程窜行显示 CD Re_map I/O and memory for PCMCIA重定位I/O和内存为PCMCIA卡CE Initialize digitize and display message初始化数字的显示信息D2Unknowm interrupt不明中断The followIng are for boot block in Flash ROME0Initialize the chipset初始化芯片组E1Initialize the bridge初始化桥E2Iinitalize the CPU初始化CPUE3Initialize system timer初始化系统时钟E4Initialize system I/0初始化系统输入输出口E5Check force reCovery boot检查强行恢复启动E6Checksum BIOSROM BIOS ROM求校验和E7Go to BIOS转向BIOSE8Set Hune Segment设置大量段寄存器E9Initialize Multi procssor初始化多处理器EA Initialize OEMspectal code初始化OEM专用代码EB Initialize PIC and DMA初始化PIC 和DMAEC Initialize Memory type初始化存储类型ED Initialize Memory size初始化存储容量EE Shadow Boot Block映射启动模块EF System memory test系统存储器测试F0Initilize intemupt vectors初始化中断向量F1Initilize Run Time Clock初始化运行时钟F2Initilize video初始化显示F3Initilize System Management Manager初始化系统管理的管理器F4Output one beep输出一个嗡鸣声F5Clear Huge Seginent清空大量段寄存器F6Boot to Mini DOS最小化DOS启动F7Boot to Full DOS完整DOS启动。

REVISION HISTORYDECLARATIONTABLE OF CONTENTS5.3. DC Electrical Characteristics2.6.Memory Subsystem&Touch G-SENSORSPI1_CLK UART3_RX42 DDR3_D743 VCC3_DRAM79 AGND80 VRPSDC0_CMD 111PF3PE9 CSI_D6LCD_D10 141PD10PC19 163 VCC4function 0);3)Type: signal directionPC7 Input PC8 InputPE4 Input PE5 InputSignal Name DescriptionOthersVRP Reference voltageV IH High-Level Input Voltage V IL Low-Level Input VoltageFigure 5-1. Power Up Sequence5.5.2.Power Up Reset Sequence RequirementsThe device has a system reset signal to reset the board. When asserted, the following steps give an example of power up reset sequence supported by the R8 device.•AVCC ,VDD_CPU and VCC_DRAM can be powered up simultaneously.•VDD_INT can be powered up after VDD_CPU is powered up, the time difference is T1ms.•VCC can be powered up after VDD_INT is powered up, the time difference is T2ms.Figure 5-2. Power Up Reset Sequence5.5.3.Resume Power Up Sequence from Super Standby ModeTo resume a power up sequence when the device is in Super Standby mode:•VCC_DRAM and AVCC remains powered up always.•VDD_CPU can be powered up firstly.•VDD_INT can be powered up after VDD_CPU is powered up, the time difference is T1ms.•VCC can be powered up after VDD_INT is powered up, the time difference is T2ms.Figure 5-3. Exit Super Standby and Resume Power Up Sequence5.5.4.Power Down Sequence RequirementsTo reduce power consumption,the R8 can be partially powered down.The section lists the power down requirements in each mode.In Super Standby mode,•VCC_DRAM and AVCC must be kept powered up.•VDD_CPU,VDD_INT and VCC are powered down simultaneously.•VCC voltage fall time is more longer than VDD_INT.VDD_CPUVDD_CPU6.PIN ASSIGNMENT6.2.PACKAGE DIMENSIONThe following diagram shows the package dimension of R8.。

MIPS32™ Architecture For Programmers Volume I: Introduction to the MIPS32™ArchitectureDocument Number: MD00082Revision 2.00June 8, 2003MIPS Technologies, Inc.1225 Charleston RoadMountain View, CA 94043-1353Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Copyright ©2001-2003 MIPS Technologies, Inc. All rights reserved.Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries.This document contains information that is proprietary to MIPS Technologies, Inc. ("MIPS Technologies"). Any copying,reproducing,modifying or use of this information(in whole or in part)that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. 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The information contained in this document constitutes one or more of the following: commercial computer software, commercial computer software documentation or other commercial items.If the user of this information,or any related documentation of any kind,including related technical data or manuals,is an agency,department,or other entity of the United States government ("Government"), the use, duplication, reproduction, release, modification, disclosure, or transfer of this information, or any related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation12.212for civilian agencies and Defense Federal Acquisition Regulation Supplement227.7202 for military agencies.The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party.MIPS,R3000,R4000,R5000and R10000are among the registered trademarks of MIPS Technologies,Inc.in the United States and other countries,and MIPS16,MIPS16e,MIPS32,MIPS64,MIPS-3D,MIPS-based,MIPS I,MIPS II,MIPS III,MIPS IV,MIPS V,MIPSsim,SmartMIPS,MIPS Technologies logo,4K,4Kc,4Km,4Kp,4KE,4KEc,4KEm,4KEp, 4KS, 4KSc, 4KSd, M4K, 5K, 5Kc, 5Kf, 20Kc, 25Kf, ASMACRO, ATLAS, At the Core of the User Experience., BusBridge, CoreFPGA, CoreLV, EC, JALGO, MALTA, MDMX, MGB, PDtrace, Pipeline, Pro, Pro Series, SEAD, SEAD-2, SOC-it and YAMON are among the trademarks of MIPS Technologies, Inc.All other trademarks referred to herein are the property of their respective owners.Template: B1.08, Built with tags: 2B ARCH MIPS32MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table of ContentsChapter 1 About This Book (1)1.1 Typographical Conventions (1)1.1.1 Italic Text (1)1.1.2 Bold Text (1)1.1.3 Courier Text (1)1.2 UNPREDICTABLE and UNDEFINED (2)1.2.1 UNPREDICTABLE (2)1.2.2 UNDEFINED (2)1.3 Special Symbols in Pseudocode Notation (2)1.4 For More Information (4)Chapter 2 The MIPS Architecture: An Introduction (7)2.1 MIPS32 and MIPS64 Overview (7)2.1.1 Historical Perspective (7)2.1.2 Architectural Evolution (7)2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures (9)2.2 Compliance and Subsetting (9)2.3 Components of the MIPS Architecture (10)2.3.1 MIPS Instruction Set Architecture (ISA) (10)2.3.2 MIPS Privileged Resource Architecture (PRA) (10)2.3.3 MIPS Application Specific Extensions (ASEs) (10)2.3.4 MIPS User Defined Instructions (UDIs) (11)2.4 Architecture Versus Implementation (11)2.5 Relationship between the MIPS32 and MIPS64 Architectures (11)2.6 Instructions, Sorted by ISA (12)2.6.1 List of MIPS32 Instructions (12)2.6.2 List of MIPS64 Instructions (13)2.7 Pipeline Architecture (13)2.7.1 Pipeline Stages and Execution Rates (13)2.7.2 Parallel Pipeline (14)2.7.3 Superpipeline (14)2.7.4 Superscalar Pipeline (14)2.8 Load/Store Architecture (15)2.9 Programming Model (15)2.9.1 CPU Data Formats (16)2.9.2 FPU Data Formats (16)2.9.3 Coprocessors (CP0-CP3) (16)2.9.4 CPU Registers (16)2.9.5 FPU Registers (18)2.9.6 Byte Ordering and Endianness (21)2.9.7 Memory Access Types (25)2.9.8 Implementation-Specific Access Types (26)2.9.9 Cache Coherence Algorithms and Access Types (26)2.9.10 Mixing Access Types (26)Chapter 3 Application Specific Extensions (27)3.1 Description of ASEs (27)3.2 List of Application Specific Instructions (28)3.2.1 The MIPS16e Application Specific Extension to the MIPS32Architecture (28)3.2.2 The MDMX Application Specific Extension to the MIPS64 Architecture (28)3.2.3 The MIPS-3D Application Specific Extension to the MIPS64 Architecture (28)MIPS32™ Architecture For Programmers Volume I, Revision 2.00i Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.3.2.4 The SmartMIPS Application Specific Extension to the MIPS32 Architecture (28)Chapter 4 Overview of the CPU Instruction Set (29)4.1 CPU Instructions, Grouped By Function (29)4.1.1 CPU Load and Store Instructions (29)4.1.2 Computational Instructions (32)4.1.3 Jump and Branch Instructions (35)4.1.4 Miscellaneous Instructions (37)4.1.5 Coprocessor Instructions (40)4.2 CPU Instruction Formats (41)Chapter 5 Overview of the FPU Instruction Set (43)5.1 Binary Compatibility (43)5.2 Enabling the Floating Point Coprocessor (44)5.3 IEEE Standard 754 (44)5.4 FPU Data Types (44)5.4.1 Floating Point Formats (44)5.4.2 Fixed Point Formats (48)5.5 Floating Point Register Types (48)5.5.1 FPU Register Models (49)5.5.2 Binary Data Transfers (32-Bit and 64-Bit) (49)5.5.3 FPRs and Formatted Operand Layout (50)5.6 Floating Point Control Registers (FCRs) (50)5.6.1 Floating Point Implementation Register (FIR, CP1 Control Register 0) (51)5.6.2 Floating Point Control and Status Register (FCSR, CP1 Control Register 31) (53)5.6.3 Floating Point Condition Codes Register (FCCR, CP1 Control Register 25) (55)5.6.4 Floating Point Exceptions Register (FEXR, CP1 Control Register 26) (56)5.6.5 Floating Point Enables Register (FENR, CP1 Control Register 28) (56)5.7 Formats of Values Used in FP Registers (57)5.8 FPU Exceptions (58)5.8.1 Exception Conditions (59)5.9 FPU Instructions (62)5.9.1 Data Transfer Instructions (62)5.9.2 Arithmetic Instructions (63)5.9.3 Conversion Instructions (65)5.9.4 Formatted Operand-Value Move Instructions (66)5.9.5 Conditional Branch Instructions (67)5.9.6 Miscellaneous Instructions (68)5.10 Valid Operands for FPU Instructions (68)5.11 FPU Instruction Formats (70)5.11.1 Implementation Note (71)Appendix A Instruction Bit Encodings (75)A.1 Instruction Encodings and Instruction Classes (75)A.2 Instruction Bit Encoding Tables (75)A.3 Floating Point Unit Instruction Format Encodings (82)Appendix B Revision History (85)ii MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Figure 2-1: Relationship between the MIPS32 and MIPS64 Architectures (11)Figure 2-2: One-Deep Single-Completion Instruction Pipeline (13)Figure 2-3: Four-Deep Single-Completion Pipeline (14)Figure 2-4: Four-Deep Superpipeline (14)Figure 2-5: Four-Way Superscalar Pipeline (15)Figure 2-6: CPU Registers (18)Figure 2-7: FPU Registers for a 32-bit FPU (20)Figure 2-8: FPU Registers for a 64-bit FPU if Status FR is 1 (21)Figure 2-9: FPU Registers for a 64-bit FPU if Status FR is 0 (22)Figure 2-10: Big-Endian Byte Ordering (23)Figure 2-11: Little-Endian Byte Ordering (23)Figure 2-12: Big-Endian Data in Doubleword Format (24)Figure 2-13: Little-Endian Data in Doubleword Format (24)Figure 2-14: Big-Endian Misaligned Word Addressing (25)Figure 2-15: Little-Endian Misaligned Word Addressing (25)Figure 3-1: MIPS ISAs and ASEs (27)Figure 3-2: User-Mode MIPS ISAs and Optional ASEs (27)Figure 4-1: Immediate (I-Type) CPU Instruction Format (42)Figure 4-2: Jump (J-Type) CPU Instruction Format (42)Figure 4-3: Register (R-Type) CPU Instruction Format (42)Figure 5-1: Single-Precisions Floating Point Format (S) (45)Figure 5-2: Double-Precisions Floating Point Format (D) (45)Figure 5-3: Paired Single Floating Point Format (PS) (46)Figure 5-4: Word Fixed Point Format (W) (48)Figure 5-5: Longword Fixed Point Format (L) (48)Figure 5-6: FPU Word Load and Move-to Operations (49)Figure 5-7: FPU Doubleword Load and Move-to Operations (50)Figure 5-8: Single Floating Point or Word Fixed Point Operand in an FPR (50)Figure 5-9: Double Floating Point or Longword Fixed Point Operand in an FPR (50)Figure 5-10: Paired-Single Floating Point Operand in an FPR (50)Figure 5-11: FIR Register Format (51)Figure 5-12: FCSR Register Format (53)Figure 5-13: FCCR Register Format (55)Figure 5-14: FEXR Register Format (56)Figure 5-15: FENR Register Format (56)Figure 5-16: Effect of FPU Operations on the Format of Values Held in FPRs (58)Figure 5-17: I-Type (Immediate) FPU Instruction Format (71)Figure 5-18: R-Type (Register) FPU Instruction Format (71)Figure 5-19: Register-Immediate FPU Instruction Format (71)Figure 5-20: Condition Code, Immediate FPU Instruction Format (71)Figure 5-21: Formatted FPU Compare Instruction Format (71)Figure 5-22: FP RegisterMove, Conditional Instruction Format (71)Figure 5-23: Four-Register Formatted Arithmetic FPU Instruction Format (72)Figure 5-24: Register Index FPU Instruction Format (72)Figure 5-25: Register Index Hint FPU Instruction Format (72)Figure 5-26: Condition Code, Register Integer FPU Instruction Format (72)Figure A-1: Sample Bit Encoding Table (76)MIPS32™ Architecture For Programmers Volume I, Revision 2.00iii Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table 1-1: Symbols Used in Instruction Operation Statements (2)Table 2-1: MIPS32 Instructions (12)Table 2-2: MIPS64 Instructions (13)Table 2-3: Unaligned Load and Store Instructions (24)Table 4-1: Load and Store Operations Using Register + Offset Addressing Mode (30)Table 4-2: Aligned CPU Load/Store Instructions (30)Table 4-3: Unaligned CPU Load and Store Instructions (31)Table 4-4: Atomic Update CPU Load and Store Instructions (31)Table 4-5: Coprocessor Load and Store Instructions (31)Table 4-6: FPU Load and Store Instructions Using Register+Register Addressing (32)Table 4-7: ALU Instructions With an Immediate Operand (33)Table 4-8: Three-Operand ALU Instructions (33)Table 4-9: Two-Operand ALU Instructions (34)Table 4-10: Shift Instructions (34)Table 4-11: Multiply/Divide Instructions (35)Table 4-12: Unconditional Jump Within a 256 Megabyte Region (36)Table 4-13: PC-Relative Conditional Branch Instructions Comparing Two Registers (36)Table 4-14: PC-Relative Conditional Branch Instructions Comparing With Zero (37)Table 4-15: Deprecated Branch Likely Instructions (37)Table 4-16: Serialization Instruction (38)Table 4-17: System Call and Breakpoint Instructions (38)Table 4-18: Trap-on-Condition Instructions Comparing Two Registers (38)Table 4-19: Trap-on-Condition Instructions Comparing an Immediate Value (38)Table 4-20: CPU Conditional Move Instructions (39)Table 4-21: Prefetch Instructions (39)Table 4-22: NOP Instructions (40)Table 4-23: Coprocessor Definition and Use in the MIPS Architecture (40)Table 4-24: CPU Instruction Format Fields (42)Table 5-1: Parameters of Floating Point Data Types (45)Table 5-2: Value of Single or Double Floating Point DataType Encoding (46)Table 5-3: Value Supplied When a New Quiet NaN Is Created (47)Table 5-4: FIR Register Field Descriptions (51)Table 5-5: FCSR Register Field Descriptions (53)Table 5-6: Cause, Enable, and Flag Bit Definitions (55)Table 5-7: Rounding Mode Definitions (55)Table 5-8: FCCR Register Field Descriptions (56)Table 5-9: FEXR Register Field Descriptions (56)Table 5-10: FENR Register Field Descriptions (57)Table 5-11: Default Result for IEEE Exceptions Not Trapped Precisely (60)Table 5-12: FPU Data Transfer Instructions (62)Table 5-13: FPU Loads and Stores Using Register+Offset Address Mode (63)Table 5-14: FPU Loads and Using Register+Register Address Mode (63)Table 5-15: FPU Move To and From Instructions (63)Table 5-16: FPU IEEE Arithmetic Operations (64)Table 5-17: FPU-Approximate Arithmetic Operations (64)Table 5-18: FPU Multiply-Accumulate Arithmetic Operations (65)Table 5-19: FPU Conversion Operations Using the FCSR Rounding Mode (65)Table 5-20: FPU Conversion Operations Using a Directed Rounding Mode (65)Table 5-21: FPU Formatted Operand Move Instructions (66)Table 5-22: FPU Conditional Move on True/False Instructions (66)iv MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table 5-23: FPU Conditional Move on Zero/Nonzero Instructions (67)Table 5-24: FPU Conditional Branch Instructions (67)Table 5-25: Deprecated FPU Conditional Branch Likely Instructions (67)Table 5-26: CPU Conditional Move on FPU True/False Instructions (68)Table 5-27: FPU Operand Format Field (fmt, fmt3) Encoding (68)Table 5-28: Valid Formats for FPU Operations (69)Table 5-29: FPU Instruction Format Fields (72)Table A-1: Symbols Used in the Instruction Encoding Tables (76)Table A-2: MIPS32 Encoding of the Opcode Field (77)Table A-3: MIPS32 SPECIAL Opcode Encoding of Function Field (78)Table A-4: MIPS32 REGIMM Encoding of rt Field (78)Table A-5: MIPS32 SPECIAL2 Encoding of Function Field (78)Table A-6: MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture (78)Table A-7: MIPS32 MOVCI Encoding of tf Bit (79)Table A-8: MIPS32 SRL Encoding of Shift/Rotate (79)Table A-9: MIPS32 SRLV Encoding of Shift/Rotate (79)Table A-10: MIPS32 BSHFL Encoding of sa Field (79)Table A-11: MIPS32 COP0 Encoding of rs Field (79)Table A-12: MIPS32 COP0 Encoding of Function Field When rs=CO (80)Table A-13: MIPS32 COP1 Encoding of rs Field (80)Table A-14: MIPS32 COP1 Encoding of Function Field When rs=S (80)Table A-15: MIPS32 COP1 Encoding of Function Field When rs=D (81)Table A-16: MIPS32 COP1 Encoding of Function Field When rs=W or L (81)Table A-17: MIPS64 COP1 Encoding of Function Field When rs=PS (81)Table A-18: MIPS32 COP1 Encoding of tf Bit When rs=S, D, or PS, Function=MOVCF (81)Table A-19: MIPS32 COP2 Encoding of rs Field (82)Table A-20: MIPS64 COP1X Encoding of Function Field (82)Table A-21: Floating Point Unit Instruction Format Encodings (82)MIPS32™ Architecture For Programmers Volume I, Revision 2.00v Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.vi MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Chapter 1About This BookThe MIPS32™ Architecture For Programmers V olume I comes as a multi-volume set.•V olume I describes conventions used throughout the document set, and provides an introduction to the MIPS32™Architecture•V olume II provides detailed descriptions of each instruction in the MIPS32™ instruction set•V olume III describes the MIPS32™Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS32™ processor implementation•V olume IV-a describes the MIPS16e™ Application-Specific Extension to the MIPS32™ Architecture•V olume IV-b describes the MDMX™ Application-Specific Extension to the MIPS32™ Architecture and is notapplicable to the MIPS32™ document set•V olume IV-c describes the MIPS-3D™ Application-Specific Extension to the MIPS64™ Architecture and is notapplicable to the MIPS32™ document set•V olume IV-d describes the SmartMIPS™Application-Specific Extension to the MIPS32™ Architecture1.1Typographical ConventionsThis section describes the use of italic,bold and courier fonts in this book.1.1.1Italic Text•is used for emphasis•is used for bits,fields,registers, that are important from a software perspective (for instance, address bits used bysoftware,and programmablefields and registers),and variousfloating point instruction formats,such as S,D,and PS •is used for the memory access types, such as cached and uncached1.1.2Bold Text•represents a term that is being defined•is used for bits andfields that are important from a hardware perspective (for instance,register bits, which are not programmable but accessible only to hardware)•is used for ranges of numbers; the range is indicated by an ellipsis. For instance,5..1indicates numbers 5 through 1•is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below.1.1.3Courier TextCourier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.MIPS32™ Architecture For Programmers Volume I, Revision 2.001 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Chapter 1 About This Book1.2UNPREDICTABLE and UNDEFINEDThe terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of theprocessor in certain cases.UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register).Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged andunprivileged software can cause UNPREDICTABLE results or operations.1.2.1UNPREDICTABLEUNPREDICTABLE results may vary from processor implementation to implementation,instruction to instruction,or as a function of time on the same implementation or instruction. Software can never depend on results that areUNPREDICTABLE.UNPREDICTABLE operations may cause a result to be generated or not.If a result is generated, it is UNPREDICTABLE.UNPREDICTABLE operations may cause arbitrary exceptions.UNPREDICTABLE results or operations have several implementation restrictions:•Implementations of operations generating UNPREDICTABLE results must not depend on any data source(memory or internal state) which is inaccessible in the current processor mode•UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example,UNPREDICTABLE operations executed in user modemust not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process •UNPREDICTABLE operations must not halt or hang the processor1.2.2UNDEFINEDUNDEFINED operations or behavior may vary from processor implementation to implementation, instruction toinstruction, or as a function of time on the same implementation or instruction.UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue.UNDEFINED operations or behavior may cause data loss.UNDEFINED operations or behavior has one implementation restriction:•UNDEFINED operations or behavior must not cause the processor to hang(that is,enter a state from which there is no exit other than powering down the processor).The assertion of any of the reset signals must restore the processor to an operational state1.3Special Symbols in Pseudocode NotationIn this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1-1.Table 1-1 Symbols Used in Instruction Operation StatementsSymbol Meaning←Assignment=, ≠Tests for equality and inequality||Bit string concatenationx y A y-bit string formed by y copies of the single-bit value x2MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.1.3Special Symbols in Pseudocode Notationb#n A constant value n in base b.For instance10#100represents the decimal value100,2#100represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#" prefix is omitted, the default base is 10.x y..z Selection of bits y through z of bit string x.Little-endian bit notation(rightmost bit is0)is used.If y is less than z, this expression is an empty (zero length) bit string.+, −2’s complement or floating point arithmetic: addition, subtraction∗, ×2’s complement or floating point multiplication (both used for either)div2’s complement integer divisionmod2’s complement modulo/Floating point division<2’s complement less-than comparison>2’s complement greater-than comparison≤2’s complement less-than or equal comparison≥2’s complement greater-than or equal comparisonnor Bitwise logical NORxor Bitwise logical XORand Bitwise logical ANDor Bitwise logical ORGPRLEN The length in bits (32 or 64) of the CPU general-purpose registersGPR[x]CPU general-purpose register x. The content of GPR[0] is always zero.SGPR[s,x]In Release 2 of the Architecture, multiple copies of the CPU general-purpose registers may be implemented.SGPR[s,x] refers to GPR set s, register x. GPR[x] is a short-hand notation for SGPR[ SRSCtl CSS, x].FPR[x]Floating Point operand register xFCC[CC]Floating Point condition code CC.FCC[0] has the same value as COC[1].FPR[x]Floating Point (Coprocessor unit 1), general register xCPR[z,x,s]Coprocessor unit z, general register x,select sCP2CPR[x]Coprocessor unit 2, general register xCCR[z,x]Coprocessor unit z, control register xCP2CCR[x]Coprocessor unit 2, control register xCOC[z]Coprocessor unit z condition signalXlat[x]Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR numberBigEndianMem Endian mode as configured at chip reset (0→Little-Endian, 1→ Big-Endian). Specifies the endianness of the memory interface(see LoadMemory and StoreMemory pseudocode function descriptions),and the endianness of Kernel and Supervisor mode execution.BigEndianCPU The endianness for load and store instructions (0→ Little-Endian, 1→ Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register.Thus,BigEndianCPU may be computed as (BigEndianMem XOR ReverseEndian).Table 1-1 Symbols Used in Instruction Operation StatementsSymbol MeaningChapter 1 About This Book1.4For More InformationVarious MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS URL:ReverseEndianSignal to reverse the endianness of load and store instructions.This feature is available in User mode only,and is implemented by setting the RE bit of the Status register.Thus,ReverseEndian may be computed as (SR RE and User mode).LLbitBit of virtual state used to specify operation for instructions that provide atomic read-modify-write.LLbit is set when a linked load occurs; it is tested and cleared by the conditional store. It is cleared, during other CPU operation,when a store to the location would no longer be atomic.In particular,it is cleared by exception return instructions.I :,I+n :,I-n :This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the currentinstruction appear to occur during the instruction time of the current instruction.No label is equivalent to a time label of I . Sometimes effects of an instruction appear to occur either earlier or later — that is, during theinstruction time of another instruction.When this happens,the instruction operation is written in sections labeled with the instruction time,relative to the current instruction I ,in which the effect of that pseudocode appears to occur.For example,an instruction may have a result that is not available until after the next instruction.Such an instruction has the portion of the instruction operation description that writes the result register in a section labeled I +1.The effect of pseudocode statements for the current instruction labelled I +1appears to occur “at the same time”as the effect of pseudocode statements labeled I for the following instruction.Within one pseudocode sequence,the effects of the statements take place in order. However, between sequences of statements for differentinstructions that occur “at the same time,” there is no defined order. Programs must not depend on a particular order of evaluation between such sections.PCThe Program Counter value.During the instruction time of an instruction,this is the address of the instruction word. The address of the instruction that occurs during the next instruction time is determined by assigning a value to PC during an instruction time. If no value is assigned to PC during an instruction time by anypseudocode statement,it is automatically incremented by either 2(in the case of a 16-bit MIPS16e instruction)or 4before the next instruction time.A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.PABITSThe number of physical address bits implemented is represented by the symbol PABITS.As such,if 36physical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.FP32RegistersModeIndicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs).In MIPS32,the FPU has 3232-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs.In MIPS64,the FPU has 3264-bit FPRs in which 64-bit data types are stored in any FPR.In MIPS32implementations,FP32RegistersMode is always a 0.MIPS64implementations have a compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In such a caseFP32RegisterMode is computed from the FR bit in the Status register.If this bit is a 0,the processor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.The value of FP32RegistersMode is computed from the FR bit in the Status register.InstructionInBranchDelaySlotIndicates whether the instruction at the Program Counter address was executed in the delay slot of a branch or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which is not executed in the delay slot of a branch or jump.SignalException(exce ption, argument)Causes an exception to be signaled, using the exception parameter as the type of exception and the argument parameter as an exception-specific argument). Control does not return from this pseudocode function - the exception is signaled at the point of the call.Table 1-1 Symbols Used in Instruction Operation StatementsSymbolMeaning。

Installation InstructionsArmorBlock LP24 Sinking Input / 4 Output Module(Cat. No. 1792D-4BT4LP)This ArmorBlock LP2™ I/O module (Cat. No. 1792D-4BT4LP) is a stand-alone 24V dc I/O product which communicates via a DeviceNet network. The sealed housing of this module requires no enclosure.This module has 4 sinking inputs and 4 sourcing outputs accessed through Y splitter cables. Four self-protected 24V dc outputs can provide up to 300mA each.Package ContentsYour package contains:• 1 ArmorBlock LP2 Module •Installation Instructions416222 4 Sinking Input / 4 Output ModuleEuropean Union Directive ComplianceIf this product has the CE mark it is approved for installation within the European Union and EEA regions. It has been designed and tested to meet the following directives.EMC DirectiveThis product is tested to meet Council Directive 89/336/EEC Electromagnetic Compatibility (EMC) and the following standards, in whole or in part, documented in a technical construction file:•EN 50081-2 EMC - Generic Emission Standard, Part 2 - Industrial Environment•EN 50082-2 EMC - Generic Immunity Standard, Part 2 - Industrial EnvironmentThis product is intended for use in an industrial environment.Low Voltage DirectiveThis product is tested to meet Council Directive 73/23/EEC Low V oltage, by applying the safety requirements of EN 61131-2 Programmable Controllers, Part 2 - Equipment Requirements and Tests.For specific information required by EN 61131-2, see the appropriate sections in this publication, as well as the following Allen-Bradley publications:•Industrial Automation Wiring and Grounding Guidelines For Noise Immunity, publication 1770-4.1•Automation Systems Catalog, publication B111Install Your ArmorBlock LP2 I/O ModuleTo install the module:•Set the node address and baud rate.•Mount the module.•Connect the unit to the DeviceNet trunk and the auxilary power source.•Connect the cord sets.Set the Node AddressSet the node address using RSNetworx for DeviceNet software, DeviceNetManager™ software, or another software configuration tool. The module is equipped with AutoBaud detect. AutoBaud lets the module read the settings already in use on your DeviceNet network and automatically adjusts to follow those settings.4 Sinking Input / 4 Output Module3Install the Module1.Attach the module using the dimensions shown below.2.Connect the grey DeviceNet cable to the DeviceNet trunk. Use the1485P-P1R5-MN5R1 T-Part tap to connect to round media. Use the 1485P-P1E4-R5 to connect to the Kwik Link flat media system. Connect the Input / Output Cord Sets to the LP2 ModuleThis module uses 5 pin micro (12mm) style PCB mounted connectors. Four micro caps cover the connectors on your module. Remove the caps and connect your cord sets to the appropriate ports. This product has two inputs or outputs per I/O connector. Use a “Y” splitter cable for access to all I/O connections. For more information on these cables, see the Product Data guide publication 1792-2.1.Use the micro caps to cover and seal unused ports. Pinout diagrams for the connectors are shown next.Input Micro-Connector(View into Sockets)Pin 1 Sensor Source VoltagePin 2 Input BPin 3 Return Logic Ground1Pin 4 Input APin 5 Not UsedOutput Micro-Connector(View into Sockets)Pin 1 Not UsedPin 2 Output BPin 3 Auxilary Power GroundPin 4 Output APin 5 Not UsedLogic Ground is approximately 0.4V above DeviceNet V-measured at the module.414524 4 Sinking Input / 4 Output ModuleOutput Power and DeviceNet CablesRefer to the DeviceNet Cable Planning and Installation Manual for more information on output power and DeviceNet cables for your application.!ATTENTION:•Make sure to connect the proper color coded cables together. DeviceNet cable should connect to DeviceNet cables and auxillary outputs should match auxillary outputs.•Make sure all connectors and caps are securely tightened to properly seal the connections against leaks and maintain IP67 requirements•For maximum noise immunity, input and output cable return wires must be properly terminated. When inputs and outputs are connected in loopback, return wires should be connected together.•I/O cable length should be less than 30 meters.Input 030706-MInput 1Input 2Input 34 Sinking Input / 4 Output Module 5Communicate With Your ArmorBlock LP2 I/O ModuleThis ArmorBlock module’s I/O is exchanged with the master through a polled, change of state, or cyclic connection.The module consumes and produces I/O data as follows:Cyclic - allows configuration of the block as an I/O client. The block will produce and consume its I/O cyclically at the rate configured.Polled - a master initiates communication by sending its polled I/O message to the module. The 4 input / 4 output module consumes themessage, updates outputs, and produces a response. The response has input data, and the status of the Auxiliary power.Change of state - productions occur when an input changes. If no input change occurs within the expected packet rate, a heartbeat production occurs. This heartbeat production tells the scanner module that the I/O module is alive and ready to communicate. Consumption occurs when data changes and the master produces new output data to the I/O module. Refer to the table below for the word/bit definitions.Type of I/O Connections Consumes Produces Cyclic 1 Byte 1 Byte Polled 1 Byte 1 Byte Change of State1 Byte1 ByteBit 0706050403020100Produces 0RSVD OPWR RSVD RSVD I3I2I1I0Consumes 0RSVDRSVDRSVDRSVDO3O2O1O0Where:RSVD= Reserved I = InputO = OutputOPWR= Output Power (Auxiliary Power)6 4 Sinking Input / 4 Output ModuleThe DeviceNet Network uses advanced network technology, producer/consumer communication, to increase network functionality andthroughput. Visit our web site at /networks for producer/consumer technology information and updates.Byte Bit DescriptionProduces 000-0304050607Input status bits: When the bit is set (1), the input is on. Bit 00 corresponds to input 0, bit 01 corresponds to input 1, bit 02 corresponds to input 2, bit 03 corresponds to input 3.Reserved ReservedOutput Powr Fault (OPWR): When the bit is set (1) auxilary power is not present.ReservedConsumes 000-0304-07Output bits: When the bit is set (1), the output will be turned on. Bit 00 corresponds to output 0, bit 01 corresponds to output 1, bit 02 to output 2, bit 03 to output 3.Reserved4 Sinking Input / 4 Output Module7Troubleshoot with the IndicatorsThis module has the following indicators:•Network status indicator•Module status indicator•Auxiliary Power indicator•Individual point status indicators for inputs 0, 1, 2, and 3 and outputs 0,Module Status IndicatorIndication StatusNone No PowerGreenBlinking Solid Needs Commissioning Operating NormalRedBlinking Solid Recoverable Fault Unrecoverable Faultand 130706-M 38 4 Sinking Input / 4 Output ModuleFor more information on indications see the Product Data publication 1792-2.1.Network Status Indicator Indication Status None Not On-lineGreen Blinking Solid On-line/No Connections On-line/ConnectedRed Blink SolidConnection Timed OutFailed Communication: A duplicate node address exists or module is at the wrong baud rate.Auxiliary Power Indication StatusNone No Auxiliary Power Green SolidAuxiliary Power PresentI/O Status Indicators Function Module Status Indicator Point Indicator Condition Outputs Green Green None Yellow Output not energized Output energized InputsGreen GreenNone YellowNo valid input Valid input4 Sinking Input / 4 Output Module9 Specifications4 Input / 4 Output Module - Cat. No. 1792D-4BT4LPSinking Input Specifications Max MinInputs per block 4 - 3 wire or dry contact PNP devices or 2 - 4 wirePNP devicesSensor Source Current (per input)50mA-On-state Voltage 25V dc10V dcOn-state Current10mA2mAOff-state Voltage5V dcOff-state Current 1.5mA Sourcing Output Specifications Max MinOutputs per block 4 sourcing outputs labeled O0, O1, O2, and O3 Output Auxiliary Voltage30V10VOn-state Voltage Drop1V-On-state Current0.3A-Off-state Leakage 1.5mA-Module Current (all outputs) 1.2A-Surge Current - for 10ms,repeatable every 2s0.6A-No Load Sense Current (On-state)0.18A-General SpecificationsIndicators Network Status - red/greenModule Status - red/greenAuxiliary Power - greenPoint LED - yellowCommunication Rate•125Kbps @ 500 meters(1600 feet) for thickcable, flat media length 375 meters•250Kbps @ 200 meters(600 feet) for thick cable,flat media length 150 meters• 500Kbps @ 100 meters (330 feet) for thickcable, flat media length 75 metersDeviceNet Power Voltage Current25V dc125mA (no sensors)300mA (full load)11V dcAuxiliary Power Voltage Current30V dc1.2A max10V dc1.2A maxDimensions (assembled to base) inches - (Millimeters)1.023H x 2.7w x 4.72D (26)H x (68.5)W x (120)D10 4 Sinking Input / 4 Output ModuleThis product has been tested at an Open DeviceNet V endor Association, Inc. (ODV A) authorized independent test laboratory and found to comply with ODV A Conformance Test Software Composite Test Version 11.ArmorBlock, ArmorBlock LP2 and DeviceNetManager are trademarks of Rockwell Automation.4 Input / 4 Output Module - Cat. No. 1792D-4BT4LP General Specifications Cont.MaxMinEnvironmental Conditions Operational Temperature Storage Temperature Relative Humidity Shock Operating Non-operating Vibration -25 to 60o (-13 to 140o F)-25 to 80o C (-13 to 176O F)Up to 100%30g peak acceleration, 11 (+1) ms pulse width 50g peak acceleration, 11(+1)ms pulse width Tested 10g @ 10-500Hz per IEC 68-2-6Conductors Publication DN-6.7.2EnclosureMeets or exceeds IP67Agency Certification(when product is marked)•CE marked for all applicable directives4 Sinking Input / 4 Output Module11Publication 1792D-5.26 - January 199912 4 Sinking Input / 4 Output ModulePublication 1792D-5.26 - January 1999PN 955134-80© 1999 Rockwell International. All Rights Reserved. Printed in USA。

Driver for NPort 5600-DTL Series (NPort Administration Suite forWindows 7, Server 2008 R2 or later) Release Notes Supported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Fixed driver signature failure on Windows 7.• For IP Serial library, unable to reopen a Grouped-COM port.• Fixed BSOD when a Grouped-COM port is opened.• Encrypted configuration file can't be imported via web console.EnhancementsWindows 10, Windows 7, Windows 8, Windows 8.1, Windows Server 2008 R2, Windows Server 2012,Windows Server 2012 R2, Windows Server 2016, Windows Server 2019NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series,NPort 5600 Series, NPort 5600-8-DT Series, NPort 5600-8-DTL Series, NPort IA5000 Series, NPort P5150A• Supports Windows Server 2019.• Supports Moxa Security Guideline.New Features• Separate driver versions are now used to support different Windows versions; driver v2.0 supports Windows 95/98/ME/NT/XP/Visa and Windows Server 2003/2008, driver v3.0 supports Windows 7/8/8.1/10 and Windows Server 2008 R2/2012/2012 R2/2016/2019.N/ASupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/AN/AEnhancementsWindows 10, Windows 2000, Windows 7, Windows 8, Windows 8.1, Windows 95, Windows 98,Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2,Windows Server 2012, Windows Server 2012 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports encrypted configuration.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Device search failure when the host has more than 16 IP addresses.• NPort Administration Suite could not be run on Windows 2000.EnhancementsWindows 10, Windows 2000, Windows 7, Windows 8, Windows 8.1, Windows 95, Windows 98,Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2,Windows Server 2012, Windows Server 2012 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports Windows 10.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Updated IPSerial.dll to fix thread handle always existing.• Utility could not monitor devices with "auto save device" setting when restarting the utility.• Utility could not monitor devices with "manual" setting before executing search function.• Ports mapped by the NPort Administration Suite v1.18 or earlier would disappear when using a version of Administration Suite later than v1.18.• Searching by 802.11 WLAN would fail on Windows 7 or later.• The timeout of IPSerial nsio_checkalive function would not work on Windows 7 Ultimate.• Popup error message "The network component is not ready" when searching for an NPort on Windows 8.• Ports could not be sorted by COM number order when clicking the COM number field in the monitor page.• The ports mapped by NPort Administration Suite v1.19 or earlier could not be opened by using a version of Administration Suite later than v1.19.17.EnhancementsWindows 2000, Windows 7, Windows 8, Windows 8.1, Windows 95, Windows 98, Windows ME,Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2, Windows Server 2012, Windows Server 2012 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • IPSerial.dll upgraded to version 1.7.3.• IPSerial added example code for VB2010.• Updated NPort.dll to support NPort P5150A.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/AN/AEnhancementsWindows 2000, Windows 7, Windows 8, Windows 95, Windows 98, Windows ME, Windows NT,Windows Server 2003, Windows Server 2008, Windows Server 2008 R2, Windows Server 2012,Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports Windows 8 and Windows Server 2012.• Supports "Always Accept Open Request" for Windows 2000 and newer.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Driver caused a BSOD when opening and closing repeatedly in Windows 2008 R2.• Driver caused a BSOD when applications open grouped COM ports which contain one or more disabled ports.• In the COM Grouping function, sometimes HyperTerminal may not read the received data immediately.EnhancementsWindows 2000, Windows 7, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports NPort 5150AI-M12, 5250AI-M12, 5450AI-M12.• Supports LLDP configuration.• Supports Windows publish.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Application will not work properly when logging as a standard user in Windows Vista/7environments. This version will prompt the user change to an account with administrative rights.• Windows 2008 64-bit driver would cause a BSOD when accessing an invalid memory path.• Modified the Georgetown time zone to GMT-04:00, Caracas to GMT-04:30, and Sofia to GMT +02:00.• The "nsio_RTS" function was not able to control RTS signals.EnhancementsWindows 2000, Windows 7, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports NPort P5150A.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• System BSOD when setting and enabling COM grouping functions in Windows 2008 R2.EnhancementsWindows 2000, Windows 7, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports NPort 5600-8-DTL Series.• Supports NPort A Series products in NPort.dll library.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Reduced handle counts when application called nsio_init() from IPSerial library.• When closing COM port and applying change to other COM numbers simultaneously, the NPort administrator utility will cause a hang up.• If the nsio_close() function is called several times and then the nsio_open() function is called, it will fail and return an undefined error code.EnhancementsWindows 2000, Windows 7, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Server 2008 R2, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports Multi-connection by IPSerial library.• Supports Windows 7.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Shortened opening time for COM Grouping.• Shortened setting time for COM Grouping.• Write operation would stop transmitting.• Monitor and port monitor would stop after removing target.EnhancementsWindows 2000, Windows 7, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003, Windows Server 2008, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports COM Grouping function for Windows NT.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• Set IP filter netmask error on Windows x64 platforms.EnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows Server 2008, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports NPort 5110A, 5130A, 5150A, IA5450A, IA5450AI, IA5150A, IA5150AI, IA5250A, IA5250AI,5210A, 5230A, 5250A.• Supports COM Grouping function (does not support Windows 95/98/ME/NT).New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• "Import COM Mapping" function would throw an "invalid pointer opertion" message.• Monitor function would cause a memory leak.• Adjusted the IRP completion order for multi-processor environments.• Fixed the buffer protection mechanism for issues while inserting special characters in the serial RX buffer.EnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows Server 2008, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports NPort IA-5250I.New FeaturesN/A• This version also applies to models NPort IA-5250ISupported Operating SystemsNotesChangesApplicable ProductsBugs Fixed• Upgraded package: IPSerial Library.• Application crash problem with IP serial library when binding more than 8 IPs(alias) for PC.• Loading driver failed in Windows Vista x64.EnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows Server 2008, Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series N/ANew FeaturesN/AN/ASupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• SERIAL_PURGE_TXABORT did not reset the WriteCharsQueued counter.• SIO outqueue count was inaccurate under classic mode.• The port number was incorrect in the "UDP Mode Settings: Destination" list.• Startup of Monitor and Port Monitor may fail.• Removal of Monitor and Port Monitor may fail.• The search function would have issues on a Windows 2003 host with dual LAN cards.• Adding COM port would fail if "SERIALCOMM" registry key was absent.• Invalid argument for time encode.• Access violation problem in "IP Address Report List".• Search function supports 16 IP addresses for local host.• "Alive" status in Monitor and Port Monitor may be incorrect.EnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series N/ANew FeaturesN/AN/ASupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/AN/AEnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows Vista, Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports Windows Vista.• Supports 5610-8-DT, 5610-8-DT-J, 5650-8-DT, 5650-8-DT-J and 5650I-8-DT.New FeaturesN/AN/ASupported Operating SystemsNotesChangesApplicable ProductsBugs Fixed• Improved IoctlGetCommstatus() to report live out queue count.• Improved utility user interface.• Improved COM setting functions. If the selected ports are in use, no change can be made to them.These settings include: COM number, Tx mode, FIFO, and Fast Flush.• Improved COM setting functions. If the users do not have administrative privileges, they cannot add or delete COM ports. However, they can still view the COM settings and open the COM ports.• Improved utility user interface.• Modem dial out caused system halt on multi-processor platforms.• Driver read operations caused double completion (BSOD) on multi-processor platforms.• GetCommStatus caused a BSOD on multi-processor platforms.• ioctl of setting Xon/Xoff character failed.• Fixed bugs detected by Static Driver Verifier, which include a double completion problem and completion of IRP without releasing the cancel spinlock.• FastFlush setting error when COM port number exceeds 127.• COM Mapping problem when a disabled port is opened.EnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Added "Network Timeout" function for COM settings.• Added auto message log function.New FeaturesN/AN/ASupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/A• IOCTL_SERIAL_IMMEDIATE_CHAR bug causing a BSOD.• IOCTL_SERIAL_XOFF_COUNTER bug causing system halt.• Accessible IPs export and import configurations did not match.• IOCTL_SERIAL_IMMEDIATE_CHAR bug causing a BSOD.• IPSerial nsio_write and mutli-port connection problems.• Administrator could not remove serial port settings when uninstalling the NPort Administration Suite.• COM Mapping could not import files exported by Administrator v1.2.• Disconnecting an NPort will crash the application while calling nsio_close.EnhancementsWindows 2000, Windows 95, Windows 98, Windows ME, Windows NT, Windows Server 2003,Windows XPIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports PPP Mode and Real COM Mode (RFC2217) operating mode for NPort 56xx.• Supports 64-bit Windows.• Moved nprcmisic.dll to nport.dll to cover all NPort models.• Supports NPort 5130, 5150, 5650, 5650-S-SC, 5650-M-SC.• Supports SERIAL_LSRMST_ESCAPE and SERIAL_LSRMST_MST event types of IOCTL_SERIAL_LSRMST_INSERT requests. SERIAL_LSRMST_LSR_NODATA and SERIAL_LSRMST_LSR_DATA event types are not supported due to driver limitations.New FeaturesN/AN/ASupported Operating SystemsNotesChangesApplicable ProductsBugs Fixed• Improved Windows 2000/XP/2003 driver "Fast Flush" performance.• Improved disconnection process to prevent application blocking.• Improved NT/2000/XP/2003 driver Ioctl performance (parity, baud, modem...).• High CPU loading with Hyper Threading systems.• COM Mapping rescan prevents some models from being able to be configured.• Port Monitor: When NPort is reconnecting, Administrator increases CPU load to 100%.• Event log lost problem.• IOCTL_SERIAL_SET_WAIT_MASK (npser+114c) BSOD RQL_NOT_LESS_OR_EQUAL problem.• (npser+5c13) BSOD KERNEL_MODE_EXCEPTION_NOT_HANDLED problem.• Verifier testing problem.• Classic mode oqueue length was not correct.• Tx does not stop on network disconnection.• Write blocked after reconnecting.EnhancementsN/AIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • Supports new functions of firmware 2.0.• Added new NPort IA model.• Added Web console toolbar.• Supports IOCTL_SERIAL_XOFF_COUNTER command (Windows 2000/XP/2003), which is used by some 16-bit programs.New Features• Registered COM number usage (Windows 2000/XP/2003). This will avoid other COM device from using the same COM number occupied by this driver.N/ASupported Operating SystemsNotesChangesApplicable ProductsBugs FixedN/AN/AEnhancementsN/AIndustrial Device Servers, NPort 5100 Series, NPort 5100A Series, NPort 5200 Series, NPort 5200A Series, NPort 5400 Series, NPort 5600 Series, NPort 5600-DT Series, NPort 5600-DTL Series • First release.New FeaturesN/AN/A。

主题：HWPoeportpdclass 返回值分析1. 概述HWPoeportpdclass 返回值的含义和作用HWPoeportpdclass 返回值是指通过命令获取交换机端口的PoE设备类别信息。

这个返回值可以帮助网络管理员了解每个端口上连接的具体PoE设备类别，从而进行合理的网络管理和维护。

2. HWPoeportpdclass 返回值的具体格式和解读HWPoeportpdclass 返回值的格式通常是一个16进制数，表示相应端口连接的PoE设备类别。

不同的16进制数对应不同的设备类别，比如0x00代表未检测到设备、0x02代表IEEE 802.3af设备、0x03代表IEEE 802.3at设备等。

网络管理员可以根据这些返回值，快速判断端口连接的设备类别。

3. HWPoeportpdclass 返回值在网络管理中的应用通过分析HWPoeportpdclass 返回值，网络管理员可以进行以下相关工作：a. 设备识别和管理：通过返回值快速了解端口连接设备的种类，有利于对网络设备进行准确识别和管理。

b. 故障诊断和排查：当有端口出现故障时，通过返回值可以迅速判断是端口问题还是设备问题，有利于快速排查故障。

c. 安全防护：可以根据返回值对接入设备进行合理的权限控制，确保网络安全。

4. HWPoeportpdclass 返回值的获取方法和注意事项在获取HWPoeportpdclass 返回值时，需要使用相应的命令，比如“display poe interface interface-type interface-number”. 需要注意端口的权限和操作规范，确保获取到正确的返回值。

5. 结论HWPoeportpdclass 返回值在网络管理中具有重要作用，能够帮助网络管理员快速了解端口连接设备的种类，从而进行合理的管理和维护。

对于系统管理人员来说，掌握HWPoeportpdclass 返回值的分析和应用是十分重要的。

/****************************************************************************** * * * ********** * * ************ * * *** *** * * *** ++ *** * * *** + + *** CHIPCON * * *** + * * *** + + *** * * *** ++ *** * * *** *** * * ************ * * ********** * * * *******************************************************************************Filename: hal.hTarget: cc2430Author: EFU/ KJARevised: 1/3-2007Revision: 1.1Description:Hardware Abstraction Layer, Utility Library.******************************************************************************/#ifndef HAL_H#define HAL_H#include "ioCC2430.h"/****************************************************************************** ******************* Chip revisions *************************************************************************************************/ #define REV_A 0x00#define REV_B 0x01#define REV_C 0x02#define REV_D 0x03#define REV_E 0x04/****************************************************************************** ******************* Commonly used types ******************* ******************************************************************************/ typedef unsigned char BOOL;// Datatypedef unsigned char BYTE;typedef unsigned short WORD;typedef unsigned long DWORD;// Unsigned numberstypedef unsigned char UINT8;typedef unsigned short UINT16;typedef unsigned long UINT32;// Signed numberstypedef signed char INT8;typedef signed short INT16;typedef signed long INT32;// Common values#ifndef FALSE#define FALSE 0#endif#ifndef TRUE#define TRUE 1#endif#ifndef NULL#define NULL 0#endif#ifndef HIGH#define HIGH 1#endif#ifndef LOW#define LOW 0#endif/****************************************************************************** ******************* Bit, byte and word macros *************************************************************************************************/// bit mask#define BM( b ) ( 0x01 << ( b ))#define HIBYTE(a) (BYTE) ((WORD)(a) >> 8 )#define LOBYTE(a) (BYTE) (WORD)(a)#define SET_WORD(regH, regL, word) \do{ \(regH) = HIBYTE( word ); \(regL) = LOBYTE( word ); \}while(0)#define GET_WORD(regH, regL, word) \do{ \word = (WORD)regH << 8; \word |= regL; \}while(0)/****************************************************************************** ******************* Port functions/macros ************************************************************************************************** Macros for simplifying access to I/O pin setup and usage.MCU pin configuration:---------------------------------------------| Peripheral I/O signal | Alt1 | Alt2 |---------------------------------------------| Timer1 channel0 | P0.2 | P1.2 || Timer1 channel1 | P0.3 | P1.1 || Timer1 channel2 | P0.4 | P1.0 || Timer3 channel0 | P1.3 | P1.6 || Timer3 channel1 | P1.4 | P1.7 || Timer4 channel0 | P1.0 | P2.0 || Timer4 channel1 | P1.1 | P2.3 || USART0 TXD/MOSI | P0.3 | P1.5 || USART0 RXD/MISO | P0.2 | P1.4 || USART0 RTS/SCK | P0.5 | P1.3 || USART0 CTS/SS_N | P0.4 | P1.2 || USART1 TXD/MOSI | P0.4 | P1.6 || USART1 RXD/MISO | P0.5 | P1.7 || USART1 RTS/SCK | P0.3 | P1.5 || USART1 CTS/SS_N | P0.2 | P1.4 |---------------------------------------------******************************************************************************/// Macros for configuring IO peripheral location:// Example usage:// IO_PER_LOC_TIMER1_AT_PORT0_PIN234();// IO_PER_LOC_TIMER4_AT_PORT2_PIN03();// IO_PER_LOC_USART1_AT_PORT0_PIN2345();#define IO_PER_LOC_TIMER1_AT_PORT0_PIN234() do { PERCFG = (PERCFG&~0x40)|0x00; } while (0)#define IO_PER_LOC_TIMER1_AT_PORT1_PIN012() do { PERCFG = (PERCFG&~0x40)|0x40; } while (0)#define IO_PER_LOC_TIMER3_AT_PORT1_PIN34() do { PERCFG = (PERCFG&~0x20)|0x00; } while (0)#define IO_PER_LOC_TIMER3_AT_PORT1_PIN67() do { PERCFG = (PERCFG&~0x20)|0x20; } while (0)#define IO_PER_LOC_TIMER4_AT_PORT1_PIN01() do { PERCFG = (PERCFG&~0x10)|0x00; } while (0)#define IO_PER_LOC_TIMER4_AT_PORT2_PIN03() do { PERCFG = (PERCFG&~0x10)|0x10; } while (0)#define IO_PER_LOC_USART1_AT_PORT0_PIN2345() do { PERCFG = (PERCFG&~0x02)|0x00; } while (0)#define IO_PER_LOC_USART1_AT_PORT1_PIN4567() do { PERCFG = (PERCFG&~0x02)|0x02; } while (0)#define IO_PER_LOC_USART0_AT_PORT0_PIN2345() do { PERCFG = (PERCFG&~0x01)|0x00; } while (0)#define IO_PER_LOC_USART0_AT_PORT1_PIN2345() do { PERCFG = (PERCFG&~0x01)|0x01; } while (0)// Macros for configuring IO direction:// Example usage:// IO_DIR_PORT_PIN(0, 3, IO_IN); // Set P0_3 to input// IO_DIR_PORT_PIN(2, 1, IO_OUT); // Set P2_1 to output#define IO_DIR_PORT_PIN(port, pin, dir) \do { \if (dir == IO_OUT) \P##port##DIR |= BM( pin ); \else \P##port##DIR &= ~BM( pin ); \}while(0)// Where port={0,1,2}, pin={0,..,7} and dir is one of:#define IO_IN 0#define IO_OUT 1// Macros for configuring IO input mode:// Example usage:// IO_IMODE_PORT_PIN(0, 0, IO_IMODE_PUD);// IO_IMODE_PORT_PIN(2, 0, IO_IMODE_TRI);// IO_IMODE_PORT_PIN(1, 3, IO_IMODE_PUD);#define IO_IMODE_PORT_PIN(port, pin, imode) \do { \if (imode == IO_IMODE_TRI) \P##port##INP |= BM( pin ); \else \P##port##INP &= ~BM( pin ); \} while (0)// where imode is one of:#define IO_IMODE_PUD 0 // Pull-up/pull-down#define IO_IMODE_TRI 1 // Tristate// Macro for configuring IO drive mode:// Example usage:// IIO_PUD_PORT(0, IO_PULLUP);// IIO_PUD_PORT(1, IO_PULLDOWN);// IIO_PUD_PORT(2, IO_PULLUP);// IO口输入驱动模式#define IO_PUD_PORT(port, pud) \do { \if (pud == IO_PULLDOWN) \P2INP |= BM( port + 5 ); \else \P2INP &= ~BM( port + 5 ); \} while (0)#define IO_PULLUP 0#define IO_PULLDOWN 1// Macros for function select (General purpose I/O / Peripheral function): // Example usage:// IO_FUNC_PORT0_PIN0(0, 0, IO_FUNC_PERIPH);// IO_FUNC_PORT0_PIN1(0, 1, IO_FUNC_GIO);// IO_FUNC_PORT2_PIN3(2, 3, IO_FUNC_PERIPH);// IO口的外围功能配置#define IO_FUNC_PORT_PIN(port, pin, func) \do { \if((port == 2) && (pin == 3)){ \if (func) { \P2SEL |= 0x02; \} else { \P2SEL &= ~0x02; \} \} \else if((port == 2) && (pin == 4)){ \if (func) { \P2SEL |= 0x04; \} else { \P2SEL &= ~0x04; \} \} \else{ \if (func) { \P##port##SEL |= BM( pin ); \} else { \P##port##SEL &= ~BM( pin ); \} \} \} while (0)// where func is one of:#define IO_FUNC_GIO 0 // General purpose I/O#define IO_FUNC_PERIPH 1 // Peripheral function// Macros for configuring the ADC input:// Example usage:// IO_ADC_PORT0_PIN(0, IO_ADC_EN);// IO_ADC_PORT0_PIN(4, IO_ADC_DIS);// IO_ADC_PORT0_PIN(6, IO_ADC_EN);// ADC输入设置#define IO_ADC_PORT0_PIN(pin, adcEn) \do { \if (adcEn) \ADCCFG |= BM( pin ); \else \ADCCFG &= ~BM( pin ); \}while (0)// where adcEn is one of:#define IO_ADC_EN 1 // ADC input enabled#define IO_ADC_DIS 0 // ADC input disab/****************************************************************************** ******************* Interrupt functions/macros **************************************************************************************************Macros which simplify access to interrupt enables, interrupt flags andinterrupt priorities. Increases code legibility.******************************************************************************/#define INT_ON 1#define INT_OFF 0#define INT_SET 1#define INT_CLR 0// Global interrupt enables#define INT_GLOBAL_ENABLE(on) EA = (!!on)#define DISABLE_ALL_INTERRUPTS() (IEN0 = IEN1 = IEN2 = 0x00)#define INUM_RFERR 0#define INUM_ADC 1#define INUM_URX0 2#define INUM_URX1 3#define INUM_ENC 4#define INUM_ST 5#define INUM_P2INT 6#define INUM_UTX0 7#define INUM_DMA 8#define INUM_T1 9#define INUM_T2 10#define INUM_T3 11#define INUM_T4 12#define INUM_P0INT 13#define INUM_UTX1 14#define INUM_P1INT 15#define INUM_RF 16#define INUM_WDT 17#define NBR_OF_INTERRUPTS 18// Macro used together with the INUM_* constants// to enable or disable certain interrupts.// Example usage:// INT_ENABLE(INUM_RFERR, INT_ON);// INT_ENABLE(INUM_URX0, INT_OFF);// INT_ENABLE(INUM_T1, INT_ON);// INT_ENABLE(INUM_T2, INT_OFF);#define INT_ENABLE(inum, on) \ do{ \ if (inum==INUM_RFERR) { RFERRIE = on; } \else if (inum==INUM_ADC) { ADCIE = on; } \else if (inum==INUM_URX0) { URX0IE = on; } \else if (inum==INUM_URX1) { URX1IE = on; } \else if (inum==INUM_ENC) { ENCIE = on; } \else if (inum==INUM_ST) { STIE = on; } \else if (inum==INUM_P2INT) { (on) ? (IEN2 |= 0x02) : (IEN2 &= ~0x02); } \else if (inum==INUM_UTX0) { (on) ? (IEN2 |= 0x04) : (IEN2 &= ~0x04); } \else if (inum==INUM_DMA) { DMAIE = on; } \ else if (inum==INUM_T1) { T1IE = on; } \else if (inum==INUM_T2) { T2IE = on; } \else if (inum==INUM_T3) { T3IE = on; } \else if (inum==INUM_T4) { T4IE = on; } \else if (inum==INUM_P0INT) { P0IE = on; } \else if (inum==INUM_UTX1) { (on) ? (IEN2 |= 0x08) : (IEN2 &= ~0x08); } \else if (inum==INUM_P1INT) { (on) ? (IEN2 |= 0x10) : (IEN2 &= ~0x10); } \else if (inum==INUM_RF) { (on) ? (IEN2 |= 0x01) : (IEN2 &= ~0x01); } \else if (inum==INUM_WDT) { (on) ? (IEN2 |= 0x20) : (IEN2 &= ~0x20); } \ } while (0)// Macro for setting interrupt group priority// Example usage:// INT_PRIORITY(RFERR_RF_DMA, 3);// 中断优先级设置#define INT_PRIORITY(group, pri) \ do { \ if (pri == 0) { IP0 &= ~group; IP1 &= ~group; } \if (pri == 1) { IP0 |= group; IP1 &= ~group; } \if (pri == 2) { IP0 &= ~group; IP1 |= group; } \if (pri == 3) { IP0 |= group; IP1 |= group; } \ } while (0)// Where pri is one of:// 0 = Level 0 (lowest priority)// 1 = Level 1// 2 = Level 2// 3 = Level 3 (highest priority)// Where group is one of#define RFERR_RF_DMA 0x01 // Group IP0#define ADC_P2INT_T1 0x02 // Group IP1#define URX0_UTX0_T2 0x04 // Group IP2#define URX1_UTX1_T3 0x08 // Group IP3#define ENC_P1INT_T4 0x10 // Group IP4#define ST_WDT_P0INT 0x20 // Group IP5// Macro used together with the INUM_* constants// to read the interrupt flags.// Example usage:// if (INT_GETFLAG(INUM_URX0))// ...// while (!INT_GETFLAG(INUM_URX0));#define INT_GETFLAG(inum) ( \ (inum==INUM_RFERR) ? RFERRIF : \(inum==INUM_ADC) ? ADCIF : \(inum==INUM_URX0) ? URX0IF : \(inum==INUM_URX1) ? URX1IF : \(inum==INUM_ENC) ? ENCIF_0 : \(inum==INUM_ST) ? STIF : \(inum==INUM_P2INT) ? P2IF : \(inum==INUM_UTX0) ? UTX0IF : \(inum==INUM_DMA) ? DMAIF : \(inum==INUM_T1) ? T1IF : \(inum==INUM_T2) ? T2IF : \(inum==INUM_T3) ? T3IF : \(inum==INUM_T4) ? T4IF : \(inum==INUM_P0INT) ? P0IF : \(inum==INUM_UTX1) ? UTX1IF : \(inum==INUM_P1INT) ? P1IF : \(inum==INUM_RF) ? S1CON &= ~0x03 : \(inum==INUM_WDT) ? WDTIF : \0 \)// Macro used to set or clear certain interrupt flags.// Example usage:// INT_SETFLAG(INUM_URX0, INT_SET);// INT_SETFLAG(INUM_T3, INT_CLR);// 清除中断标志#define INT_SETFLAG(inum, f) \ do{ \ if (inum==INUM_RFERR) { RFERRIF= f; } \ else if (inum==INUM_ADC) { ADCIF = f; } \else if (inum==INUM_URX0) { URX0IF = f; } \else if (inum==INUM_URX1) { URX1IF = f; } \else if (inum==INUM_ENC) { (f) ? (S0CON |= 0x03) : (S0CON &= ~0x03); } \else if (inum==INUM_ST) { STIF = f; } \else if (inum==INUM_P2INT) { P2IF = f; } \else if (inum==INUM_UTX0) { UTX0IF= f; } \ else if (inum==INUM_DMA) { DMAIF = f; } \ else if (inum==INUM_T1) { T1IF = f; } \else if (inum==INUM_T2) { T2IF = f; } \else if (inum==INUM_T3) { T3IF = f; } \else if (inum==INUM_T4) { T4IF = f; } \else if (inum==INUM_P0INT) { P0IF = f; } \else if (inum==INUM_UTX1) { UTX1IF= f; } \ else if (inum==INUM_P1INT) { P1IF = f; } \else if (inum==INUM_RF) { (f) ? (S1CON |= 0x03) : (S1CON &= ~0x03); } \else if (inum==INUM_WDT) { WDTIF = f; } \ } while (0)/****************************************************************************** ************************** DMA structures / macros ********************************************************************************************************The macros and structs in this section simplify setup and usage of DMA.******************************************************************************/#define DMA_CHANNEL_0 0x01#define DMA_CHANNEL_1 0x02#define DMA_CHANNEL_2 0x04#define DMA_CHANNEL_3 0x08#define DMA_CHANNEL_4 0x10#define VLEN_USE_LEN 0x00 // Use LEN for transfer count#define VLEN_FIXED 0x00 // Use LEN for transfer count#define VLEN_1_P_VALOFFIRST 0x01 // Transfer the first byte + the number of bytes indicated by the first byte#define VLEN_VALOFFIRST 0x02 // Transfer the number of bytes indicated by the first byte (starting with the first byte)#define VLEN_1_P_VALOFFIRST_P_1 0x03 // Transfer the first byte + the number of bytes indicated by the first byte + 1 more byte#define VLEN_1_P_VALOFFIRST_P_2 0x04 // Transfer the first byte + the number of bytes indicated by the first byte + 2 more bytes#define WORDSIZE_BYTE 0x00 // Transfer a byte at a time#define WORDSIZE_WORD 0x01 // Transfer a 16-bit word at a time#define TMODE_SINGLE 0x00 // Transfer a single byte/word after each DMA trigger #define TMODE_BLOCK 0x01 // Transfer block of data (length len) after each DMA trigger#define TMODE_SINGLE_REPEATED 0x02 // Transfer single byte/word (after len transfers, rearm DMA)#define TMODE_BLOCK_REPEATED 0x03 // Transfer block of data (after len transfers, rearm DMA)#define DMATRIG_NONE 0 // No trigger, setting DMAREQ.DMAREQx bit starts transfer#define DMATRIG_PREV 1 // DMA channel is triggered by completion of previous channel#define DMATRIG_T1_CH0 2 // Timer 1, compare, channel 0#define DMATRIG_T1_CH1 3 // Timer 1, compare, channel 1#define DMATRIG_T1_CH2 4 // Timer 1, compare, channel 2#define DMATRIG_T2_COMP 5 // Timer 2, compare#define DMATRIG_T2_OVFL 6 // Timer 2, overflow#define DMATRIG_T3_CH0 7 // Timer 3, compare, channel 0#define DMATRIG_T3_CH1 8 // Timer 3, compare, channel 1#define DMATRIG_T4_CH0 9 // Timer 4, compare, channel 0#define DMATRIG_T4_CH1 10 // Timer 4, compare, channel 1#define DMATRIG_ST 11 // Sleep Timer compare#define DMATRIG_IOC_0 12 // Port 0 I/O pin input transition#define DMATRIG_IOC_1 13 // Port 1 I/O pin input transition#define DMATRIG_URX0 14 // USART0 RX complete#define DMATRIG_UTX0 15 // USART0 TX complete#define DMATRIG_URX1 16 // USART1 RX complete#define DMATRIG_UTX1 17 // USART1 TX complete#define DMATRIG_FLASH 18 // Flash data write complete#define DMATRIG_RADIO 19 // RF packet byte received/transmit#define DMATRIG_ADC_CHALL 20 // ADC end of a conversion in a sequence, sample ready#define DMATRIG_ADC_CH0 21 // ADC end of conversion channel 0 in sequence, sample ready#define DMATRIG_ADC_CH1 22 // ADC end of conversion channel 1 in sequence, sample ready#define DMATRIG_ADC_CH2 23 // ADC end of conversion channel 2 in sequence, sample ready#define DMATRIG_ADC_CH3 24 // ADC end of conversion channel 3 in sequence, sample ready#define DMATRIG_ADC_CH4 25 // ADC end of conversion channel 4 in sequence, sample ready#define DMATRIG_ADC_CH5 26 // ADC end of conversion channel 5 in sequence, sample ready#define DMATRIG_ADC_CH6 27 // ADC end of conversion channel 6 in sequence, sample ready#define DMATRIG_ADC_CH7 28 // ADC end of conversion channel 7 in sequence, sample ready#define DMATRIG_ENC_DW 29 // AES encryption processor requests download input data#define DMATRIG_ENC_UP 30 // AES encryption processor requests upload output data#define SRCINC_0 0x00 // Increment source pointer by 0 bytes/words after each transfer#define SRCINC_1 0x01 // Increment source pointer by 1 bytes/words after each transfer#define SRCINC_2 0x02 // Increment source pointer by 2 bytes/words after each transfer#define SRCINC_M1 0x03 // Decrement source pointer by 1 bytes/words aftereach transfer#define DESTINC_0 0x00 // Increment destination pointer by 0 bytes/words after each transfer#define DESTINC_1 0x01 // Increment destination pointer by 1 bytes/words after each transfer#define DESTINC_2 0x02 // Increment destination pointer by 2 bytes/words after each transfer#define DESTINC_M1 0x03 // Decrement destination pointer by 1 bytes/words after each transfer#define IRQMASK_DISABLE 0x00 // Disable interrupt generation#define IRQMASK_ENABLE 0x01 // Enable interrupt generation upon DMA channel done#define M8_USE_8_BITS 0x00 // Use all 8 bits for transfer count#define M8_USE_7_BITS 0x01 // Use 7 LSB for transfer count#define PRI_LOW 0x00 // Low, CPU has priority#define PRI_GUARANTEED 0x01 // Guaranteed, DMA at least every second try#define PRI_HIGH 0x02 // High, DMA has priority#define PRI_ABSOLUTE 0x03 // Highest, DMA has priority. Reserved for DMA port access.#pragma bitfields=reversedtypedef struct {BYTE SRCADDRH;BYTE SRCADDRL;BYTE DESTADDRH;BYTE DESTADDRL;BYTE VLEN : 3;BYTE LENH : 5;BYTE LENL : 8;BYTE WORDSIZE : 1;BYTE TMODE : 2;BYTE TRIG : 5;BYTE SRCINC : 2;BYTE DESTINC : 2;BYTE IRQMASK : 1;BYTE M8 : 1;BYTE PRIORITY : 2;} DMA_DESC;#pragma bitfields=default#define DMA_SET_ADDR_DESC0(a) \do{ \DMA0CFGH = HIBYTE( a ); \DMA0CFGL = LOBYTE( a ); \} while(0)#define DMA_SET_ADDR_DESC1234(a) \do{ \DMA1CFGH = HIBYTE( a ); \DMA1CFGL = LOBYTE( a ); \} while(0)#define DMA_ARM_CHANNEL(ch) \DMAARM = ((0x01 << ch) & 0x1F);#define DMA_ABORT_CHANNEL(ch) DMAARM = (0x80 | ( BM( ch ) & 0x1F) ) #define DMA_MAN_TRIGGER(ch) DMAREQ = BM( ch )#define DMA_START_CHANNEL(ch) DMA_MAN_TRIGGER( ch )// Macro for quickly setting the destination address of a DMA structure#define SET_DMA_DEST(pDmaDesc, dest) \ do{ \pDmaDesc->DESTADDRH = HIBYTE( dest ); \pDmaDesc->DESTADDRL = LOBYTE( dest ); \} while (0);// Macro for quickly setting the source address of a DMA structure#define SET_DMA_SOURCE(pDmaDesc, source) \ do{ \pDmaDesc->SRCADDRH = HIBYTE( source ); \pDmaDesc->SRCADDRL = LOBYTE( source ); \ } while (0)// Macro for quickly setting the number of bytes to be transferred by the DMA. // Max lenght is 0x1FFF#define SET_DMA_LENGTH(pDmaDesc, length) \ do{ \pDmaDesc->LENH = HIBYTE( length ); \pDmaDesc->LENL = LOBYTE( length ); \} while (0)// Macro for getting the destination address of a DMA channel#define GET_DMA_DEST(pDmaDesc) \( (WORD)pDmaDesc->DESTADDRL | ( (WORD)pDmaDesc->DESTADDRH << 8 ))// Macro for getting the source address of a DMA channel#define GET_DMA_SOURCE(pDmaDesc) \( (WORD)pDmaDesc->SRCADDRL | ( (WORD)pDmaDesc->SRCADDRH << 8 ))/****************************************************************************** ******************* Common USART functions/macros ******************* *******************************************************************************The macros in this section are available for both SPI and UART operation.******************************************************************************/// Example usage:// USART0_FLUSH();#define USART_FLUSH(num) (U##num##UCR |= 0x80)#define USART0_FLUSH() USART_FLUSH(0)#define USART1_FLUSH() USART_FLUSH(1)// Example usage:// if (USART0_BUSY())// ...#define USART_BUSY(num) (U##num##CSR & 0x01)#define USART0_BUSY() USART_BUSY(0)#define USART1_BUSY() USART_BUSY(1)// Example usage:// while(!USART1_BYTE_RECEIVED())// ...#define USART_BYTE_RECEIVED(num) (U##num##CSR & 0x04)#define USART0_BYTE_RECEIVED() USART_BYTE_RECEIVED(0)#define USART1_BYTE_RECEIVED() USART_BYTE_RECEIVED(1)// Example usage:// if(USART1_BYTE_TRANSMITTED())// ...#define USART_BYTE_TRANSMITTED(num) (U##num##CSR & 0x02)#define USART0_BYTE_TRANSMITTED() USART_BYTE_TRANSMITTED(0)#define USART1_BYTE_TRANSMITTED() USART_BYTE_TRANSMITTED(1)/****************************************************************************** ******************* USART-UART specific functions/macros *************************************************************************************************/ // The macros in this section simplify UART operation.#define BAUD_E(baud, clkDivPow) ( \(baud==2400) ? 6 +clkDivPow : \(baud==4800) ? 7 +clkDivPow : \(baud==9600) ? 8 +clkDivPow : \(baud==14400) ? 8 +clkDivPow : \(baud==19200) ? 9 +clkDivPow : \(baud==28800) ? 9 +clkDivPow : \(baud==38400) ? 10 +clkDivPow : \(baud==57600) ? 10 +clkDivPow : \(baud==76800) ? 11 +clkDivPow : \(baud==115200) ? 11 +clkDivPow : \(baud==153600) ? 12 +clkDivPow : \(baud==230400) ? 12 +clkDivPow : \(baud==307200) ? 13 +clkDivPow : \0 )#define BAUD_M(baud) ( \(baud==2400) ? 59 : \(baud==4800) ? 59 : \(baud==9600) ? 59 : \(baud==14400) ? 216 : \(baud==19200) ? 59 : \(baud==28800) ? 216 : \(baud==38400) ? 59 : \(baud==57600) ? 216 : \(baud==76800) ? 59 : \(baud==115200) ? 216 : \(baud==153600) ? 59 : \(baud==230400) ? 216 : \(baud==307200) ? 59 : \0)// Macro for setting up a UART transfer channel. The macro sets the appropriate// pins for peripheral operation, sets the baudrate, and the desired options of// the selected uart. _uart_ indicates which uart to configure and must be// either 0 or 1. _baudRate_ must be one of 2400, 4800, 9600, 14400, 19200, // 28800, 38400, 57600, 76800, 115200, 153600, 230400 or 307200. Possible // options are defined below.//// Example usage://// UART_SETUP(0,115200,HIGH_STOP);//// This configures uart 0 for contact with "hyperTerminal", setting:// Baudrate: 115200// Data bits: 8// Parity: None// Stop bits: 1// Flow control: None//#define UART_SETUP(uart, baudRate, options) \do { \if ((options) & FLOW_CONTROL_ENABLE){ \if((uart) == 0){ /* USART0 */\if(PERCFG & 0x01){ /* Alt 2 */\P1SEL |= 0x3C; \} else { /* Alt 1 */\P0SEL |= 0x3C; \} \} \else { /* USART1 */\if(PERCFG & 0x02){ /* Alt 2 */\P1SEL |= 0xF0; \} else { /* Alt 1 */\P0SEL |= 0x3C; \} \} \} \else{ /* Flow Ctrl Dis*/\if((uart) == 0){ /* USART0 */\if(PERCFG & 0x01){ /* Alt 2 */\P1SEL |= 0x30; \} else { /* Alt 1 */\P0SEL |= 0x0C; \} \} \else { /* USART1 */\if(PERCFG & 0x02){ /* Alt 2 */\P1SEL |= 0xC0; \} else { /* Alt 1 */\P0SEL |= 0x30; \} \ } \ } \\ U##uart##GCR = BAUD_E((baudRate), CLKSPD); \U##uart##BAUD = BAUD_M(baudRate); \\ U##uart##CSR |= 0x80; \\ U##uart##UCR |= ((options) | 0x80); \\ if((options) & TRANSFER_MSB_FIRST){ \U##uart##GCR |= 0x20; \ } \ } while(0)// Options for UART_SETUP macro#define FLOW_CONTROL_ENABLE 0x40#define FLOW_CONTROL_DISABLE 0x00#define EVEN_PARITY 0x20#define ODD_PARITY 0x00#define NINE_BIT_TRANSFER 0x10#define EIGHT_BIT_TRANSFER 0x00#define PARITY_ENABLE 0x08#define PARITY_DISABLE 0x00#define TWO_STOP_BITS 0x04#define ONE_STOP_BITS 0x00#define HIGH_STOP 0x02#define LOW_STOP 0x00#define HIGH_START 0x01#define TRANSFER_MSB_FIRST 0x80#define TRANSFER_MSB_LAST 0x00// Example usage:// if(UART0_PARERR())// ...#define UART_PARERR(num) (U##num##CSR & 0x08) #define UART0_PARERR() UART_PARERR(0)#define UART1_PARERR() UART_PARERR(1)// Example usage:// if(UART1_FRAMEERR())// ...#define UART_FRAMEERR(num) (U ##num## CSR & 0x10)#define UART0_FRAMEERR() UART_FRAMEERR(0)#define UART1_FRAMEERR() UART_FRAMEERR(1)// Example usage:// char ch = 'A';// UART1_SEND(ch);// ...// UART1_RECEIVE(ch);#define UART_SEND(num, x) U##num##DBUF = x#define UART0_SEND(x) UART_SEND(0, x)#define UART1_SEND(x) UART_SEND(1, x)#define UART_RECEIVE(num, x) x = U##num##DBUF#define UART0_RECEIVE(x) UART_RECEIVE(0, x)#define UART1_RECEIVE(x) UART_RECEIVE(1, x)/****************************************************************************** ******************* USART-SPI specific functions/macros ************************************************************************************************** The macros in this section simplify SPI operation.******************************************************************************/// Macro for setting up an SPI connection. The macro configures the appropriate// pins for peripheral operation, sets the baudrate if the chip is configured// to be SPI master, and sets the desired clock polarity and phase. Whether to// transfer MSB or LSB first is also determined. _spi_ indicates whether// to use spi 0 or 1. _baudRate_ must be one of 2400, 4800, 9600, 14400, 19200,// 28800, 38400, 57600, 76800, 115200, 153600, 230400 or 307200.// Possible options are defined below.#define SPI_SETUP(spi, baudRate, options) \do { \U##spi##UCR = 0x80; \U##spi##CSR = 0x00; \\ if((options) & SPI_SLAVE){ /* Slave */\if(spi == 0){ /* USART0 */\if(PERCFG & 0x01){ /* Alt 2 */\P1SEL |= 0x3C; \} else { /* Alt 1 */\P0SEL |= 0x3C; \} \ } else { /* USART1 */\if(PERCFG & 0x02){ /* Alt 2 */\P1SEL |= 0xF0; \} else { \P0SEL |= 0x3C; /* Alt 1 */\} \ } \U##spi##CSR = 0x20; \ } \else { /* Master */\ if(spi == 0){ /* USART0 */\if(PERCFG & 0x01){ /* Alt 2 */\P1SEL |= 0x38; \P1SEL &= ~0x04; \} else { /* Alt 1 */\P0SEL |= 0x2C; \P0SEL &= ~0x10; \} \ } else { /* USART 1 */\if(PERCFG & 0x02){ /* Alt 2 */\P1SEL |= 0xE0; \P1SEL &= ~0x10; \} else { /* Alt 1 */\P0SEL |= 0x38; \P0SEL &= ~0x04; \} \ } \U##spi##GCR = BAUD_E(baudRate, CLKSPD); \U##spi##BAUD = BAUD_M(baudRate); \ } \U##spi##GCR |= ((options) & 0xE0); \ } while(0)// Options for the SPI_SETUP macro.#define SPI_SLAVE 0x01#define SPI_MASTER 0x00#define SPI_CLOCK_POL_LO 0x00#define SPI_CLOCK_POL_HI 0x80#define SPI_CLOCK_PHA_0 0x00#define SPI_CLOCK_PHA_1 0x40#define SPI_TRANSFER_MSB_FIRST 0x20#define SPI_TRANSFER_MSB_LAST 0x00/****************************************************************************** ******************* FLASH programming functions ******************* *******************************************************************************_halFlashWritePage(...)_ writes a whole flash page. Because code memory cannotbe read during flash write, the writing routines are copied to XDATA RAM. Thefunction is implemented in assembly code with file extensions .s51 rather than .cThe Direct Memory Access (DMA) may also be used for flash write.******************************************************************************///Macro for erasing a given flash page#define FLASH_ERASE_PAGE(page) \do{ \FADDRH = (page) << 1; \FCTL = 0x01; \asm("NOP"); \while(FCTL == 0x80); \}while (0)#define SET_FLASH_WRITE_TIME() \FWT = 0x2A >> CLKSPD;/****************************************************************************** * @fn halFlashDmaTrigger** @brief* This function gives the first FLASH DMA trigger.** Parameters:。