K9W8G08U1M-YCB0中文资料

K9XXG08UXMINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.10.20.31.0RemarkAdvance Advance Preliminary Preliminary FinalHistory1. Initial issue1. Technical note is changed 1. Icc value is changedDraft DateMar. 1st. 2005Apr. 1st. 2005May 3rd. 2005Sep. 26th. 2005Nov. 4th 2005GENERAL DESCRIPTIONFEATURES• Voltage Supply - 2.70V ~ 3.60V • Organization- Memory Cell Array : (1G + 32M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 20µs(Max.) - Serial Access : 25ns(Min.) * K9NBG08U5M : 50ns(Min.) • Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC) - Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9K8G08U0M-YCB0/YIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- K9K8G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1M-YCB0/YIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- K9WAG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1M-ICB0/IIB052 - Pin TLGA (12 x 17 / 1.0 mm pitch)- K9NBG08U5M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)Offered in 1G x 8bit, the K9K8G08U0M is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns(K9NBG08U5M:50ns) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as com-mand input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0M ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K8G08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.An ultra high density solution having two 8Gb stacked with two chip selects is also available in standard TSOPI package and another ultra high density solution having two 16Gb TSOPI package stacked with four chip selects is also available in TSOPI-DSP .PRODUCT LISTPart Number Vcc RangeOrganizationPKG Type K9K8G08U0M-Y ,P 2.70 ~ 3.60VX8TSOP1K9WA G08U1M-Y ,P K9WA G08U1M-I 52TLGA K9NBG08U5M-PTSOP1-DSP1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View1.0(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321K9WAG08U1M - ICB0 / IIB052-TLGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NCNCNCNCNCNC NCVccVcc VssVssVss /RE1/RE2/CE1/CE2CLE1CLE2ALE1ALE2/WE1/WE2/WP1/WP2R/B1R/B2VssIO0-1IO0-2IO1-1IO1-2IO2-1IO3-1IO2-2IO3-2IO4-1IO4-2IO5-1IO5-2IO6-1IO6-2IO7-1IO7-2∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.There are two CE pins (CE 1 & CE 2) in the K9WAG08U1M and four CE pins (CE 1 & CE 2 & CE 3 & CE 4) in the K9NBG08U5M.There are two R/B pins (R/B1 & R/B2) in the K9WAG08U1M and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the K9NBG08U5M.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation.Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation. CE2CHIP ENABLEThe CE2 input enables the second K9K8G08U0MREREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K8G08U0M is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0M. The K9K8G08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0M.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.The K9WAG08U1M is composed of two K9K8G08U0M chips which are selected separately by each CE1 and CE2 and the K9NBG08U5M is composed of four K9K8G08U0M chips which are selected seperately by each CE1, CE2, CE3 and CE4. Therefore, in terms of each CE, the basic operations of K9WAG08U0M and K9NBG08U5M are same with K9K8G08U0M except some AC/DC charateristics.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hTwo-Plane Page Program(4)80h---11h81h---10hCopy-Back Program85h10hTwo-Plane Copy-Back Program(4)85h---11h81h---10hBlock Erase60h D0hTwo-Plane Block Erase60h---60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh OChip1 Status(3)F1h OChip2 Status(3)F2h ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.3. Interleave-operation between two chips is allowed.It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.4.Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.3. The typical value of the K9WAG08U1M’s I SB 2 is 40µA and the maximum value is 200µA.4. The typical value of the K9NBG08U5M’s I SB 2 is 80µA and the maximum value is 400µA.5. The maximum value of K9WAG08U1M-Y ,P’s I LI and I LO is ±40µA , the maximum value of K9WAG08U1M-I’s I LI and I LO is ±20µA .6. The maximum value of K9NBG08U5M’s I LI and I LO is ±80µA.ParameterSymbol Test ConditionsMinTypMaxUnitOperating CurrentPage Read withSerial Access I CC 1tRC=25ns (K9NBG08U5M: 50ns)CE=V IL, I OUT =0mA-2535mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -20100µAInput Leakage Current I LI V IN =0 to Vcc(max)--±20Output Leakage Current I LO V OUT =0 to Vcc(max)--±20Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH I OH =-400µA 2.4--Output Low Voltage Level V OL I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXG08UXM-XCB0 :T A =0 to 70°C, K9XXG08UXM-XIB0:T A =-40 to 85°C)ParameterSymbol Min Typ.Max Unit Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc+0.3 (<4.6V)Temperature Under Bias K9XXG08UXM-XCB0T BIAS -10 to +125°C K9XXG08UXM-XIB0-40 to +125Storage Temperature K9XXG08UXM-XCB0T STG-65 to +150°CK9XXG08UXM-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1M-IXB0’s capacitance(I/O, Input) is 20pF.ItemSymbol Test Condition Min MaxUnit K9K8G08U0MK9WAG08U1M*K9NBG08U5MInput/Output Capacitance C I/O V IL =0V -204080pF Input CapacitanceC INV IN =0V-204080pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.* : Each K9K8G08U0M chip in the K9WAG08U1M and K9NBG08U5M has Maximun 160 invalid blocks.Parameter Symbol Min Typ.Max Unit K9K8G08U0M N VB 8,032-8,192Blocks K9WAG08U1M N VB 16,064*-16,384*BlocksK9NBG08U5MN VB32,128*32,768*AC TEST CONDITION(K9XXG08UXM-XCB0: T A =0 to 70°C, K9XXG08UXM-XIB0:T A =-40 to 85°C ,K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9XXG08UXM Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF (K9K8G08U0M-Y ,P/K9WAG08U1M-I) 1 TTL GATE and CL=30pF (K9WAG08U1M-Y ,P) 1 TTL GATE and CL=30pF (K9NBG08U5M-P)MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byAC Timing Characteristics for Command / Address / Data InputNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleParameterSymbol MinMaxUnitK9NBG08U5MK9K8G08U0M K9NBG08U5MK9K8G08U0M K9WAG08U1MK9WAG08U1MCLE Setup Time t CLS (1)2512--ns CLE Hold Time t CLH 105--ns CE Setup Time t CS (1)3520--ns CE Hold Time t CH 105--ns WE Pulse Width t WP 2512--ns ALE Setup Time t ALS (1)2512--ns ALE Hold Time t ALH 105--ns Data Setup Time t DS (1)2012--ns Data Hold Time t DH 105--ns Write Cycle Time t WC 4525--ns WE High Hold Timet WH 1510--ns Address to Data Loading Timet ADL (2)7070--ns Program / Erase CharacteristicsNOTE1. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C temperature .ParameterSymbol Min Typ Max Unit Program Time t PROG -200700µs Dummy Busy Time for Two-Plane Page Program t DBSY -0.51µs Number of Partial Program Cycles Nop --4cycles Block Erase Timet BERS- 1.52msAC Characteristics for OperationNOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.ParameterSymbol MinMaxUnitK9NBG08U5MK9K8G08U0M K9NBG08U5MK9K8G08U0M K9WAG08U1K9WAG08U1Data Transfer from Cell to Register t R -2020µs ALE to RE Delay t AR 1010-ns CLE to RE Delay t CLR 1010-ns Ready to RE Low t RR 2020-ns RE Pulse Width t RP 2512-ns WE High to Busy t WB --100100ns Read Cycle Time t RC 5025--ns RE Access Time t REA --3020ns CE Access Time t CEA --4525ns RE High to Output Hi-Z t RHZ --100100ns CE High to Output Hi-Z t CHZ --3030ns RE High to Output hold t RHOH 1515--ns RE Low to Output hold t RLOH -5--ns CE High to Output hold t COH 1515--ns RE High Hold Time t REH 1510--ns Output Hi-Z to RE Low t IR 00--ns RE High to WE Low t RHW 100100--ns WE High to RE Lowt WHR 6060--ns Device Resetting Time(Read/Program/Erase)t RST--5/10/500(1)5/10/500(1)µsNAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block table.StartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9K8G08U0M supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-nificant bit) pages of the block. Random page address programming is prohibited.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Interleave Page ProgramK9K8G08U0M is composed of two K9F4G08U0Ms. K9K8G08U0M provides interleaving operation between two K9F4G08U0Ms. This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.At first, the host issues page program command to one of the K9F4G08U0M chips, say K9F4G08U0M(chip #1). Due to this K9K8G08U0M goes into busy state. During this time, K9F4G08U0M(chip #2) is in ready state. So it can execute the page program command issued by the host.After the execution of page program by K9F4G08U0M(chip #1), it can execute another page program regardless of the K9F4G08U0M(chip #2). Before that the host needs to check the status of K9F4G08U0M(chip #1) by issuing F1h command. Only when the status of K9F4G08U0M(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0M(chip #1) is in busy state, the host has to wait for the K9F4G08U0M(chip #1) to get into ready state.Similarly, K9F4G08U0M chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0M(chip #2) by issuing F2h command. When the K9F4G08U0M(chip #2) shows ready state, host can issue another page program command to K9F4G08U0M(chip #2).This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation.NOTES : During interleave operations, 70h command is prohibited.R / B (#1)b u s y o f C h i p #1I /O X80h10h C o m m a n d A 30 : L o w A d d & D a t a80h 10h A 30 : H i g h A d d & D a t ab u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e P a g e P r o g r a m≈≈≈F 1h o r F 2h A B CDa n o t h e r p a g e p r o g r a m o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a p a g e p r o g r a m o p e r a t i o n a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a p a g e p r o g r a m c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g p a g e p r o g r a m o p e r a t i o n .S t a t e C : P a g e p r o g r a m o n c h i p #1 i s t e r m i n a t e d , b u t p a g e p r o g r a m o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r p a g e p r o g r a m c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e p a g e p r o g r a m o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x h。

Product IntroductionThe K9F1G08U0B is a 1,056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2,112x8 columns. Spare 64x8 col-umns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodat-ing data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B.The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 132M byte physical space requires 28 addresses, thereby requiring four cycles for addressing : 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-mand register. Table 1 defines the specific commands of the K9F1G08U0B.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.Table 1. Command SetsNOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.Function1st Cycle 2nd CycleAcceptable Command during BusyRead00h 30h Read for Copy Back 00h 35h Read ID 90h -Reset FFh -OPage Program 80h 10h Copy-Back Program 85h 10h Block Erase60h D0h Random Data Input (1)85h -Random Data Output (1)05h E0hRead Status 70h O Read EDC Status (2)7BhODC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less.2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.ParameterSymbol Test ConditionsK9F1G08U0B(3.3V)UnitMinTypMaxOperating CurrentPage Read with Serial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-1530mAProgram I CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -1050µAInput Leakage Current I LI V IN =0 to Vcc(max)--±10Output Leakage Current I LO V OUT =0 to Vcc(max)--±10Input High VoltageV IH (1)-0.8xVcc -V CC +0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH K9F1G08U0A :I OH =-400µA 2.4--Output Low Voltage Level V OLK9F1G08U0A :I OL =2.1mA--0.4Output Low Current(R/B)I OL (R/B)K9F1G08U0A :V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F1G08U0B-XCB0 :T A =0 to 70°C, K9F1G0808B-XIB0:T A =-40 to 85°C)ParameterSymbol K9F1G08U0B(3.3V)UnitMin Typ.Max Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSV ABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit3.3V Device Voltage on any pin relative to VSSV CC-0.6 to + 4.6VV IN -0.6 to + 4.6V I/O-0.6 to Vcc + 0.3 (< 4.6V)Temperature Under BiasK9XXG08XXB-XCB0T BIAS -10 to +125°C K9XXG08XXB-XIB0-40 to +125Storage Tempera-tureK9XXG08XXB-XCB0T STG-65 to +150°CK9XXG08XXB-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.ItemSymbol Test ConditionMin Max Unit Input/Output Capacitance C I/O V IL =0V -10pF Input CapacitanceC INV IN =0V-10pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.ParameterSymbol Min Typ.Max Unit K9F1G08U0BN VB1,004-1,024BlocksMODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(4clock)H L L H H Write ModeCommand Input L H L H H Address Input(4clock)L L L HH Data Input L L L H XData Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byAC TEST CONDITION(K9F1G08U0B-XCB0 :TA=0 to 70°C, K9F1G08U0B-XIB0:TA=-40 to 85°C, K9F1G08U0B : Vcc=2.7V~3.6V unless otherwise noted)ParameterK9F1G08U0B Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF。

关于现在MP3有用MLC和SLC两种芯片的已经不是什么新闻了，但是很多人都害怕自己买到的是MLC芯片的MP3，认为MLC芯片的MP3就一定不好，其实这里面有很多需要说明的地方，存在很多误解。

在说明MLC MP3之前我们先了解一下什么是MLC和SLC闪存芯片，以及它们的特点和应用。

什么是SLC和MLC？SLC全称为Single-Level Cell，MLC全称为Multi-Level Cell。

数码播放器中一般采用两种不同类型的NAND闪存。

其中一种叫做SLC（Single Level Cell），单层单元闪存；第二种叫做MLC（Multi Level Cell），多层单元闪存。

两者的主要区别是SLC每一个单元储存一位数据，而MLC通过使用大量的电压等级，每一个单元储存两位数据，数据密度比较大。

SLC芯片和MLC技术特点一般而言，SLC虽然生产成本较高，但在效能上大幅胜于MLC。

SLC晶片可重复写入次数约10万次，而MLC晶片的写入次数至少要达到1万次才算标准，而目前三星MLC芯片采用的MLC芯片写入寿命则在5000次左右。

A.读写速度较慢。

相对主流SLC芯片，MLC芯片目前技术条件下，理论速度只能达到2MB左右，因此对于速度要求较高的应用会有一些问题。

B.MLC能耗比SLC高，在相同使用条件下比SLC要多15%左右的电流消耗。

C.MLC理论写入次数上限相对较少，因此在相同使用情况下，使用寿命比较SLC短。

MP3主控芯片对MLC支持的现状随着三星、现代、东芝的MLC闪存芯片开始量产，但是，由于全新的MLC芯片在存储密度等方面加大，对主控芯片的要求也越来越高。

特别是对于读写频繁的数码播放器来说，由于MLC闪存的出错几率很高，对于视频和音频这样的应用来说，必需具备ECC校验机制，目前有的主控芯片通过纯软件校验，这样，无形当中加重了主控芯片的负担。

也有部分主控通过硬件的4bit ECC校验和软件校验相结合，从而减轻了主控负担，但是这只是在一定程度上减少出错的几率，MLC的芯片写入次数限制和传输速度等缺点是无法克服的。

K9F1G08U0B中文资料部分K9F1G08U0B中文资料（部分）128*8Bit NAND Flash存储器工作电压范围：2.7~3.6V 存储单元：8位特征描述组织：存储单元为（128M+4M）*8位，数据寄存器为（2K+64）字节自动页编程（写操作）和擦除：自动页编程（写操作）为（2K+64）字节，块擦除为（128K+4K）字节页读操作：页大小为（2K+64）字节，任意读最大时间为25us，串行存取时间最小为：25ns最快写操作周期：页编程（写操作）时间为200us，块擦除时间为1.5ms命令/地址/数据I/O端口概述K9F1G08U0B的容量为1056Mbit （128M×8bits+64byte×64K×8bits）。

K9F1G08U0B的页编程操作（写操作）在（2K+64）字节的也上执行，时间为200us，块擦除操作是在（128K+4K)字节的块上执行，时间为1.5ms。

数据寄存器里的数据每字节被读出是用25ns是时间周期。

I/O引脚为地址、命令和数据复用引脚。

引脚描述发送地址说明注释：1、第一和第二周期为列地址，第三和第四周期为行地址2、L表示为低电平产品描述K9F1G08U0B的存储容量为1056MBit。

由65536页（行）和2112列组成。

又分为1024块，1块大小为64页（行）。

每页大小为2112列（2K+64bytes（字节）），即2048bytes（字节）和附加的64bytes（字节）。

附加的64bytes（即为OOB，out of band的缩写）的地址为2048~2111。

读页操作和页编程操作（写操作）都是基于页的，而擦除操作是基于块的。

K9F1G08U0B的8位I/O口为地址、命令和数据复用。

这样方便以后升级到大容量。

命令、地址和数据在WE和CE位低电平时写入I/O口，在WE下降沿被锁存。

命令靠使能CLE来锁存，地址靠使能ALE来锁存。

Intel ，SST，AMD，MXIC系列FLASH芯片比较目前常见的FLASH芯片的生产厂家主要有Intel，SST，AMD，MXIC等，现以使用比较广泛的16M BYTE的FLASH芯片为例，比较它们在性能、设计上的一些异同。

Intel的16M BYTE FLASH芯片的型号为28F160C3，SST的为39VF1601/1602，AMD的为29LV160D，MXIC的为29LV160BT/BB。

工作电压：这几种FLASH芯片的正常读、写、擦除电压都为2.7V-3.6V，但较特殊的是Intel 的28F160C3，有一条专用的快速写、擦除电源腿，可接＋12V电源进行快速写、擦除操作，若无＋12V电源，仍可接正常电源进行正常读写。

执行速度：这几种FLASH芯片都可提供最快70ns的数据读取速度。

可靠性：这几种FLASH芯片都支持最少100,000次的写、擦除操作。

并且都提供符合商业级、工业级标准的芯片。

芯片制作工艺：Intel 的28F160C3有0.13μm、0.18μm、0.25μm三种工艺的版本SST的39VF1601/1602为0.18μmAMD的29LV160D为0.23μmMXIC的29LV160BT/BB为0.23μm封装：Intel提供的封装有：48-Lead TSOP，48-Ball Easy BGA，48-Ball μBGA/VFBGA SST提供的封装有：48-Lead TSOP，48-Ball TFBGAAMD提供的封装有：44-Lead SOP，48-Lead TSOP，48-Ball FBGAMXIC提供的封装有：44-Lead SOP，48-Lead TSOP，48-Ball CSP功耗：这几种FLASH芯片在Typical Read时的电流相同，都为9mABOOT方式：这几种FLASH芯片都提供TOP BOOT和BOTTOM BOOT方式的型号。

数据存取线宽：Intel 的28F160C3和SST的39VF1601/1602都为1M×16bits的存取线宽，2M ×8bits存取线宽的FLASH芯片为另外型号。

SLC闪存芯片型号容量表品牌类型容量型号Samsung SLC16M K9F2808U0M/A/B/C Samsung SLC16M K9F2816Q0C(x16) Samsung SLC32M K9F5608U0M/A/B/C Samsung SLC32M K9F5616U0C(x16) Samsung SLC32M K9F5616U0B(x16) Samsung SLC64M K9F1208U0M/A/B/C Samsung SLC64M K9F1208Q0CSamsung SLC64M K9K1216U0C(x16) Samsung SLC64M K9k1216Q0C(x16) Samsung SLC128M K9K1G08Q0ASamsung SLC128M K9K1G08U0M/A/B Samsung SLC128M K9K1G16U0A(x16) Samsung SLC128M K9F1G16U0M(x16) Samsung SLC128M K9F1G08U0ASamsung SLC128M K9F1G08R0ASamsung SLC128M K9F1G08U0M/A Samsung SLC128M K9F1G08R0M/A Samsung SLC128M K9F1G08U0BSamsung SLC128M K9F1G16Q0B(x16) Samsung SLC128M K9F1G16Q0M(x16) Samsung SLC256M K9E2G08U0MSamsung SLC256M K9E2G08U1MSamsung SLC256M K9K2G08U1ASamsung SLC256M K9K2G08Q0M/A Samsung SLC256M K9K2G08U0M/A Samsung SLC256M K9K2G16Q0M/A(x16) Samsung SLC256M K9K2G16U0M/A(x16) Samsung SLC256M K9F2G08U0MSamsung SLC256M K9F2G16U0M(x16) Samsung SLC256M K9F2G08U0ASamsung SLC256M K9F2G08R0ASamsung SLC512M K9W4G08U1MSamsung SLC512M K9W4G16U1M(x16) Samsung SLC512M K9K4G08U0M Samsung SLC512M K9F4G08U0M Samsung SLC1G K9W8G08U1M Samsung SLC1G K9K8G08U1M Samsung SLC1G K9K8G08U0M/A Samsung SLC1G K9F8G08U0M Samsung SLC2G K9WAG08U1M/A Samsung SLC2G K9KAG08U0M Samsung SLC4G K9NBG08U5M/A Samsung SLC4G K9WBG08U1M Samsung SLC8G K9NCG08U5MMicron SLC128M MT29F1G08ABBMicron SLC128M MT29F1G16ABB(x16) Micron SLC128M MT29F1G08ABCMicron SLC128M MT29F1G16ABC(x16) Micron SLC128M MT29F1G08AACMicron SLC128M MT29F1G16AAC(x16) Micron SLC128M MT29F1G08AACMicron SLC256M MT29F2G08AAAMicron SLC256M MT29F2G08AABMicron SLC256M MT29F2G16AAB(x16) Micron SLC256M MT29F2G08ABDMicron SLC256M MT29F2G16ABD(x16) Micron SLC256M MT29F2G08AADMicron SLC256M MT29F2G16AAD(x16) Micron SLC256M MT29F2G08ABBEA Micron SLC256M MT29F2G16ABBEA(x16) Micron SLC256M MT29F2G08ABAEA Micron SLC256M MT29F2G16ABAEA(x16) Micron SLC256M MT29F2G16AAA(x16) Micron SLC512M MT29F4G08BBCMicron SLC512M MT29F4G16BBC(x16) Micron SLC512M MT29F4G08BABMicron SLC512M MT29F4G16BAB(x16) Micron SLC512M MT29F4G08ABA/CMicron SLC512M MT29F4G16ABA/C(x16) Micron SLC512M MT29F4G08AAA/CMicron SLC512M MT29F4G08ABBDAMicron SLC512M MT29F4G16ABBDA(x16) Micron SLC512M MT29F4G08ABADAMicron SLC512M MT29F4G16ABADA(x16) Micron SLC512M MT29F4G16AAA/C(x16) Micron SLC1G MT29F8G08FABMicron SLC1G MT29F8G08DAAMicron SLC1G MT29F8G08BAAMicron SLC1G MT29F8G16BAA(x16) Micron SLC1G MT29F8G08ADBDAH4 Micron SLC1G MT29F8G16ADBDAH4(x16) Micron SLC1G MT29F8G08ADADAH4 Micron SLC1G MT29F8G16ADADAH4(x16) Micron SLC1G MT29H8G08ACAH1Micron SLC1G MT29F8G08ABABAMicron SLC1G MT29F8G08AAAMicron SLC2G MT29F16G08FAAMicron SLC2G MT29F16G16FAA(x16) Micron SLC2G MT29F16G08ABABA Micron SLC2G MT29H16G08ECAH1 Micron SLC2G MT29F16G08DAAMicron SLC4G MT29F32G08FAAMicron SLC4G MT29H32G08GCAH2 Micron SLC4G MT29F32G08AFABA Micron SLC8G MT29F64G08AJABAIntel SLC512M JS29F04G08AANB1Intel SLC1G JS29F08G08CANB1Intel SLC1G JS29F08G08BANB1Intel SLC1G JS29F08G08AANC1Intel SLC1G JS29F08G08AAND1/2Intel SLC2G JS29F16G08FANB1Intel SLC2G JS29F16G08AAND1/2Intel SLC2G JS29F16G08CANC1Intel SLC4G JS29F32G08FANC1Intel SLC4G JS29F32G08CAND1/2Intel SLC8G JS29F64G08JAND1/2 Spectek SLC128M FxxMx9xxxK3WGSpectek SLC512M FxxM40AxxK3xGSpectek SLC512M FxxMx9xxxK3W2Spectek SLC1G FxxM40AxxK3x2Spectek SLC1G FxxMx9xxxK3W4Spectek SLC1G FxxM51AxxK3xGSpectek SLC1G FxxM61AxxK3xGSpectek SLC2G FxxM40AxxK3x4Spectek SLC2G FxxM51AxxK3x2Spectek SLC2G FxxM62BxxK3xGSpectek SLC4G FxxM51AxxK3x4Spectek SLC4G FxxM62BxxK3x2Spectek SLC8G FxxM62BxxK3x4 PowerFlash SLC64M PF79AL1208 PowerFlash SLC64M PF79BL1208 PowerFlash SLC256M ASU2GA30GT PowerFlash SLC512M ASU4GA30GT Hynix SLC16M HY27US08281AHynix SLC16M HY27US16281A(x16)Hynix SLC32M HY27US08561M/AHynix SLC32M HY27US16562M/A(x16) Hynix SLC32M HY27SS08561M/AHynix SLC32M HY27SS16561M/A(x16) Hynix SLC64M HY27US08121M/AHynix SLC64M HY27US16121M/A(x16) Hynix SLC64M HY27SS08121M/AHynix SLC64M HY27SS16121M/A(x16) Hynix SLC128M H27U1G8F2BHynix SLC128M HY27UA081G4MHynix SLC128M HY27(U/S)A081G1M Hynix SLC128M HY27(U/S)A161G1M(x16) Hynix SLC128M HY27SS081G1XHynix SLC128M HY27UF081G2MHynix SLC128M HY27UF081G2AHynix SLC128M HY27SF081G2M(x16) Hynix SLC256M HY27(U/S)B082G4M Hynix SLC256M HY27(U/S)B162G4M(x16) Hynix SLC256M HY27UF082G2MHynix SLC256M HY27SF082G2MHynix SLC256M HY27UF162G2M(x16) Hynix SLC256M HY27SF162G2M(x16) Hynix SLC256M HY27UF082G2AHynix SLC256M HY27UF162G2A(x16) Hynix SLC256M HY27SF162G2A(x16) Hynix SLC256M HY27UF082G2BHynix SLC256M HY27SF082G2B(x16) Hynix SLC512M HY27UG084G2MHynix SLC512M HY27SG084G2MHynix SLC512M HY27UG164G2M(x16) Hynix SLC512M HY27SG164G2M(x16) Hynix SLC512M HY27UF084G2MHynix SLC512M HY27UF084G2BHynix SLC512M HY27UF164G2B(x16) Hynix SLC512M HY27SF084G2BHynix SLC512M HY27SF164G2B(x16) Hynix SLC1G HY27UH088G2MHynix SLC1G HY27UG088G5MHynix SLC1G HY27UG088G5BHynix SLC1G HY27UG088G2MHynix SLC1G H27U8G8F2MHynix SLC2G HY27UH08AG5MHynix SLC2G HY27UH08AG5BHynix SLC2G H27UAG8G5MHynix SLC4G HY27UK08BGFMHynix SLC4G HY27UK08BGFBHynix SLC4GB H27UBG8H5MHynix SLC8GB H27UCG8KFMST SLC16M NAND128R3AST SLC16M NAND128W3AST SLC16M NAND128R4A(x16)ST SLC16M NAND128W4A(x16) ST SLC32M NAND256R3AST SLC32M NAND256W3AST SLC32M NAND256R4A(x16)ST SLC32M NAND256W4A(x16) ST SLC64M NAND512R3AST SLC64M NAND512W3AST SLC64M NAND512R4A(x16)ST SLC64M NAND512W4A(x16) ST SLC64M NAND512W3BST SLC128M NAND01GR3AST SLC128M NAND01GW3AST SLC128M NAND01GR4A(x16) ST SLC128M NAND01GW4A(x16) ST SLC128M NAND01GW3B2AST SLC128M NAND01GR3B2BST SLC128M NAND01GW3B2BST SLC128M NAND01GR4B2B(x16) ST SLC128M NAND01GW4B2B(x16) ST SLC128M NAND01GR3B2CST SLC128M NAND01GW3B2CST SLC128M NAND01GR4B2C(x16) ST SLC128M NAND01GW4B2C(x16) ST SLC256M NAND02GR3B2CST SLC256M NAND02GW3B2CST SLC256M NAND02GR4B2C(x16)ST SLC256M NAND02GW4B2C(x16)ST SLC256M NAND02GR3B2DST SLC256M NAND02GW3B2DST SLC256M NAND02GR4B2D(x16)ST SLC256M NAND02GW3B2AST SLC256M NAND02GW4B2D(x16)ST SLC512M NAND04GW3B2BST SLC512M NAND04GR3B2DST SLC512M NAND04GW3B2DST SLC512M NAND04GR4B2D(x16)ST SLC512M NAND04GW4B2D(x16)ST SLC1G NAND08GW3B2AST SLC1G NAND08GR3B4CST SLC1G NAND08GW3B4CST SLC1G NAND08GR3B2CST SLC1G NAND08GW3B2CST SLC1G NAND08GR4B2C(x16)ST SLC1G NAND08GW4B2C(x16)ST SLC1G NAND08GW3F2AST SLC2G NAND16GW3B4DST SLC2G NAND16GW3F4AST SLC2G NAND16GW3F2AST SLC4G NAND32GW3F4A Toshiba SLC16M TC58DVM72A1FT00 Toshiba SLC32M TC58DVM82A1FT00 Toshiba SLC64M TC58NVM9S3BTG00 Toshiba SLC64M TC58NVM9S8CTA00(x16) Toshiba SLC64M TC58DVM92A1FT00 Toshiba SLC128M TC58DVG02A1FT00 Toshiba SLC128M TC58NVG0S3ETA00 Toshiba SLC128M TC58NVG0S3AFT05 Toshiba SLC128M TC58NVG0S3BTGI0 Toshiba SLC128M TC58NVG0S3BTG00 Toshiba SLC256M TC58DVG12A1FT00Toshiba SLC256M TH58NVG1S3AFT05 Toshiba SLC256M TC58NVG1S3BFT00 Toshiba SLC256M TC58NVG1S3BFT00 Toshiba SLC256M TC58NVG1S8BFT00(x16) Toshiba SLC256M TC58NVG1S8BFT00(x16) Toshiba SLC256M TC58NVG1S3ETA00 Toshiba SLC512M TH58NVG2S3BFT00 Toshiba SLC1G TC58NVG3S0DTG00 Toshiba SLC2G TH58NVG4S0DTG20 Toshiba SLC4G TC58NVG5S0DTG20 SanDisk SLC64M SDTNFCH-512SanDisk SLC128M SDTNKGHSM-1024 SanDisk SLC256M SDTNGBHE0-2048 SanDisk SLC256M SDTNGFHE0-2048 SanDisk SLC512M SDTNIHHSM-4096 SanDisk SLC512M SDTNIHHSM-4096(x16) SanDisk SLC512M SDTNKEHSM-4096 SanDisk SLC512M SDTNKEHSM-4096(x16) SanDisk SLC1G SDTNKFHSM-8192 SanDisk SLC1G SDTNLJAHSM-1024 SanDisk SLC1G SDTNKFHSM-8192(x16) SanDisk SLC2G SDTNKGHSM-16384 SanDisk SLC2G SDTNKGHSM-16384(x16) SanDisk SLC2G SDTNLJBHSM-2048 SanDisk SLC4G SDTNLJCHSM-4096 Infineon SLC64M HYF33DS512800ATC Infineon SLC64M HYF33DS512800BTC Infineon SLC64M HYF33DS512804(5)BTC/I Infineon SLC128M HYF33DS1G800CTI Spansion SLC64M S30MS512RSpansion SLC64M S39MS512RSpansion SLC128M S30MS01GRSpansion SLC128M S39MS01GRSpansion SLC256M S39MS02GRSpansion SLC256M S30MS02GR Spansion SLC512M S30MS04GR表制程CE Pin1111111111111111111112211111111211221 50nm12 50nm14 50nm2 50nm411111111111111 M69A1 M69A1 M69A1 M69A11111111 M60A1 M60A1 M60A1 M60A112211 M60A1 M60A1 M60A1 M60A1 50nm1 34nm1 50nm122 34nm1 50nm2 50nm2 50nm2 50nm2 34nm2 34nm2112 50nm1 34nm134nm1 50nm2 50nm2 34nm2 34nm411122 50nm1 34nm12 50nm2 34nm1 50nm2 34nm2 34nm211111111111111 41nm1111111221111111111111111111221 48nm12248nm244 48nm2 48nm4111111111111111111111111111111111111111122111112212111111 43nm111111111 43nm11 56nm1 56nm2 56nm21111111111111111111 65nm1 65nm1 65nm1 65nm1 65nm165nm1 65nm1。

Document Title256M x 8 Bit / 128M x 16 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.10.20.30.40.50.60.70.8RemarkAdvanceHistory1. Initial issue1. I OL (R/B) of 1.8V device is changed.-min. Value: 7mA -->3mA -typ. Value: 8mA -->4mA1. 5th cycle of ID is changed : 40h --> 44h1. Add WSOP Package Dimensions.1. Add two-K9K2GXXU0M-YCB0/YIB0 Stacked Package 1. Min valid block of K9W4GXXU1M-YCB0/YIB0 is changed .- min. 4016 --> 40361. Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 30invalid blocks.2. K9W4GXXU1M’s ID is changed (Before)(After)1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)2. Add the data protection Vcc guidence for 1.8V device - below about 1.1V. (Page 37)The min. Vcc value 1.8V devices is changed.K9K2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95VDevice 2nd Cycle 3rd cycle 4th Cycle 5th Cycle K9W4G08U1M DCh C315h 4Ch K9W4G16U1M CChC355h4ChDevice 2nd Cycle 3rd cycle 4th Cycle 5th Cycle K9W4G08U1M DAh C115h 44h K9W4G16U1MCAhC155h44hDraft DateAug. 30.2001Nov. 5.2001Jan. 23. 2002May.29.2002Aug.13.2002Aug. 22.2002Nov. 07.2002Nov. 22.2002Mar. 6.2003Document Title256M x 8 Bit / 128M x 16 Bit NAND Flash MemoryRevision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.91.01.11.21.31.4RemarkHistoryPb-free Package is added.K9K2G08U0M-FCB0,FIB0K9K2G08Q0M-PCB0,PIB0K9K2G08U0M-PCB0,PIB0K9K2G16U0M-PCB0,PIB0K9K2G16Q0M-PCB0,PIB0K9W4G08U1M-PCB0,PIB0,ECB0,EIB0K9W4G16U1M-PCB0,PIB0,ECB0,EIB0Errata is added.(Front Page)-K9K2GXXQ0MtWC tWP tWH tRC tREH tRP tREA tCEA Specification 45 25 15 50 15 25 30 45Relaxed value 80 60 20 80 20 60 60 751. The 3rd Byte ID after 90h ID read command is don’t cared. The 5th Byte ID after 90h ID read command is deleted.New package dimension is added.(K9W4GXXU1M-KXB0/EXB0)1. Min valid block of K9W4GXXU1M-YCB0/YIB0 is changed .- min. 4036 --> 40162. Note is added.(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.)AC parameters are changed-K9K2GXXQ0MtWC tWP tWH tRC tREH tRP tREA tCEA Before 45 25 15 50 15 25 30 45After 80 60 20 80 20 60 60 75Draft DateMar. 13.2003Mar. 17.2003Apr. 9. 2003Apr. 15. 2003Apr. 18. 2003Aug. 5. 2003GENERAL DESCRIPTIONFEATURES• Voltage Supply-1.8V device(K9K2GXXQ0M): 1.7V~1.95V -3.3V device(K9XXGXXUXM): 2.7 V ~3.6 V • Organization- Memory Cell Array-X8 device(K9K2G08X0M) : (256M + 8,192K)bit x 8bit -X16 device(K9K2G16X0M) : (128M + 4,096K)bit x 16bit - Data Register-X8 device(K9K2G08X0M): (2K + 64)bit x8bit -X16 device(K9K2G16X0M): (1K + 32)bit x16bit - Cache Register-X8 device(K9K2G08X0M): (2K + 64)bit x8bit -X16 device(K9K2G16X0M): (1K + 32)bit x16bit • Automatic Program and Erase - Page Program-X8 device(K9K2G08X0M): (2K + 64)Byte -X16 device(K9K2G16X0M): (1K + 32)Word - Block Erase-X8 device(K9K2G08X0M): (128K + 4K)Byte -X16 device(K9K2G16X0M): (64K + 2K)Word • Page Read Operation - Page Size- X8 device(K9K2G08X0M): 2K-Byte - X16 device(K9K2G16X0M) : 1K-Word - Random Read : 25µs(Max.) - Serial Access1.8V device(K9K2GXXQ0M): 80ns(Min.) 3.3V device(K9XXGXXUXM): 50ns(Min.)256M x 8 Bit / 128M x 16 Bit NAND Flash Memory• Fast Write Cycle Time- Program time : 300µs(Typ.) - Block Erase Time : 2ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years • Command Register Operation• Cache Program Operation for High Performance Program • Power-On Auto-Read Operation • Intelligent Copy-Back Operation • Unique ID for Copyright Protection • Package :- K9K2GXXX0M-YCB0/YIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9K2G08U0M-VCB0/VIB048 - Pin WSOP I (12X17X0.7mm) - K9K2GXXX0M-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package - K9K2G08U0M-FCB0/FIB048 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9K2G08U0M-V,F(WSOPI ) is the same device as K9K2G08U0M-Y ,P(TSOP1) except package type.- K9W4GXXU1M-YCB0,PCB0/YIB0,PIB0 : Two K9K2G08U0M stacked.48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- K9W4GXXU1M-KCB0,ECB0/KIB0,EIB0 : Two K9K2G08U0M stacked.48 - Pin TSOP I (12 x 17 / 0.5 mm pitch)Offered in 256Mx8bit or 128Mx16bit, the K9K2GXXX0M is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112-byte(X8device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) or 64K-word(X16 device) block. Data in the data page can be read out at 80ns(1.8V device) or 50ns(3.3V device) cycle time per byte(X8device) or word(X16 device). The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K2GXXX0M ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2GXXX0M is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.An ultra high density solution having two 2Gb stacked with two chip selects is also available in standard TSOPI package.PRODUCT LISTPart Number Vcc Range OrganizationPKG TypeK9K2G08Q0M-Y ,P 1.7 ~ 1.95VX8TSOP1K9K2G16Q0M-Y ,P X16K9XXG08UXM-Y ,P ,K,E 2.7 ~ 3.6V X8K9XXG16UXM-Y ,P ,K,E X16K9K2G08U0M-V,FX8WSOP1PIN CONFIGURATION (TSOP1)K9K2GXXX0M-YCB0,PCB0/YIB0,PIB0X8X16X16X8PACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220FUnit :mm/Inch0.787±0.00820.00±0.20#1#240.20+0.07-0.030.008+0.003-0.0010.500.0197#48#250.48812.40M A X12.000.4720.10 0.004M A X 0.250.010()0.039±0.0021.00±0.050.0020.05MIN0.0471.20MAX0.45~0.750.018~0.0300.724±0.00418.40±0.100~8°0.0100.25T Y P0.125+0.0750.0350.005+0.003-0.0010.500.020()48-pin TSOP1Standard Type 12mm x 20mm123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CN.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C PRE Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.CN.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CVss I/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.C PRE Vcc N.C N.C N.C I/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0VssPIN CONFIGURATION (WSOP1)K9K2G08U0M-VCB0,FCB0/VIB0,FIB0PACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)48 - WSOP1 - 1217FUnit :mm15.40±0.10#1#240.20+0.07-0.030.16+0.07-0.030.50T Y P (0.50±0.06)#48#2512.00±0.100.10+0.075-0.0350.58±0.040.70 MAX(0.1Min)17.00±0.200°~8°0.45~0.75123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C DNU N.C N.C N.C R/B RE CE DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.CN.C N.C DNU N.C I/O7I/O6I/O5I/O4N.C DNU N.C Vcc Vss N.C DNU N.C I/O3I/O2I/O1I/O0N.C DNU N.C N.CPIN CONFIGURATION (TSOP1)K9W4G08U1M-YCB0,PCB0/YIB0,PIB0PACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220FUnit :mm/Inch0.787±0.00820.00±0.20#1#240.16+0.07-0.030.008+0.003-0.0010.500.0197#48#250.48812.40M A X12.000.4720.10 0.004M A X 0.250.010()0.039±0.0021.05±0.030.0020.02MIN0.0471.20MAX0.45~0.750.018~0.0300.724±0.00418.40±0.100~8°0.0100.25T Y P0.125+0.0750.0350.005+0.003-0.0010.500.020()48-pin TSOP1Standard Type 12mm x 20mm123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C N.C N.C N.C R/B2R/B1 RE CE1CE2N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CN.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C PRE Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.CX16N.C N.C N.C N.C N.C R/B2R/B1 RE CE1CE2N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CX16Vss I/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.C PRE Vcc N.C N.C N.C I/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0VssX8X8PIN CONFIGURATION (TSOP1)PACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE (I)48 - TSOP1 - 1217FUnit :mm15.40±0.10#1#240.20+0.07-0.030.16+0.07-0.030.50T Y P (0.50±0.06)#48#2512.00±0.100.15+0.075-0.0351.00±0.031.15 MAX(0.02Min)17.00±0.200°~8°0.45~0.75123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C N.C N.C N.C R/B2R/B1 RE CE1CE2N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CN.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C PRE Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.CX16N.C N.C N.C N.C N.C R/B2R/B1 RE CE1CE2N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CX16Vss I/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.C PRE Vcc N.C N.C N.C I/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0VssX8X8K9W4G08U1M-KCB0,ECB0/KIB0,EIB048-pin TSOP112mm x 17mmPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7(K9K2G08X0M)I/O 0 ~ I/O 15(K9K2G16X0M)DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and output.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE / CE1 control during read operation, refer to ’Page read’ section of Device operation .CE2CHIP ENABLEThe CE2 input enables the second K9K2GXXU0MREREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.R/B2READY/BUSY OUTPUTThe R/B2 output indicates the status of the second K9K2GXXU0MPREPOWER-ON READ ENABLEThe PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when PRE pin is tied to Vcc.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K2GXXX0M is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8(X8 device) or 1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or 1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056-word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program opera-tions. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2GXXX0M.The K9K2GXXX0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some com-mands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execu-tion. The 256M byte(X8 device) or 128M word(X16 device) physical space requires 29(X8) or 28(X16) addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K2GXXX0M.The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed.The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address input after power-on.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.Table 1. Command SetsFunction1st. Cycle2nd. Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hCache Program80h15hCopy-Back Program85h10hBlock Erase60h D0hRandom Data Input*85h-Random Data Output*05h E0hRead Status70h ONOTE : 1. Random Data Input/Output can be executed in a page.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less.ParameterSymbol Test Conditions K9K2GXXQ0M(1.8V)K9XXGXXUXM(3.3V)UnitMin Typ Max Min Typ Max Operat-ingCurrent Page Read withSerial AccessI CC 1tRC=50ns, CE=V IL I OUT =0mA-1020-1530mA ProgramI CC 2--1020-1530EraseI CC 3--1020-1530Stand-by Current(TTL)I SB 1CE=V IH , WP=PRE=0V/V CC--1--1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=PRE=0V/V CC -20100-20100µA Input Leakage Current I LI V IN =0 to Vcc(max)--±20--±20Output Leakage Current I LO V OUT =0 to Vcc(max)--±20--±20Input High VoltageV IH*-V CC -0.4-V CC +0.3 2.0-V CC +0.3V Input Low Voltage, All inputs V IL*--0.3-0.4-0.3-0.8Output High Voltage Level V OH K9K2GXXQ0M:I OH =-100µA K9XXGXXUXM:I OH =-400µA Vcc-0.1-- 2.4--Output Low Voltage LevelV OL K9K2GXXQ0M :I OL =100uA K9XXGXXUXM :I OL =2.1mA --0.1--0.4Output Low Current(R/B)I OL (R/B)K9K2GXXQ0M :V OL =0.1V K9XXGXXUXM :V OL =0.4V34-810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXGXXXXM-XCB0 :T A =0 to 70°C, K9XXGXXXXM-XIB0:T A =-40 to 85°C)Parameter Symbol K9K2GXXQ0M(1.8V)K9XXGXXUXM(3.3V)Unit Min Typ.Max Min Typ.Max Supply Voltage V CC 1.7 1.8 1.95 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC,+0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol RatingUnit K9K2GXXQ0M(1.8V) K9XXGXXUXM(3.3V)Voltage on any pin relative to V SS V IN/OUT -0.6 to + 2.45-0.6 to + 4.6V V CC -0.2 to + 2.45-0.6 to + 4.6Temperature Under Bias K9XXGXXXXM-XCB0T BIAS -10 to +125°C K9XXGXXXXM-XIB0-40 to +125Storage Temperature K9XXGXXXXM-XCB0T STG -65 to +150°C K9XXGXXXXM-XIB0Short Circuit CurrentIos5mACAPACITANCE (T A =25°C, V CC =1.8V/3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.ItemSymbol Test ConditionMaxUnit K9K2GXXX0MK9W4GXXU1MInput/Output Capacitance C I/O V IL =0V 2040pF Input CapacitanceC INV IN =0V2040pFVALID BLOCKNOTE :1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits . Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.* : Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 40 invalid blocks.ParameterSymbol Min Max Unit K9K2GXXX0M Valid Block Number N VB 20082048Blocks K9W4GXXU1MValid Block NumberN VB4016*4096*BlocksAC TEST CONDITION(K9XXGXXXXM-XCB0 :TA=0 to 70°C, K9XXGXXXXM-XIB0:TA=-40 to 85°CK9K2GXXQ0M : Vcc=1.70V~1.95V , K9XXGXXUXM : Vcc=2.7V~3.6V unless otherwise noted)ParameterK9K2GXXQ0M K9XXGXXUXM Input Pulse Levels 0V to Vcc 0.4V to 2.4VInput Rise and Fall Times 5ns 5ns Input and Output Timing LevelsVcc/21.5VK9K2GXXQ0M:Output Load (Vcc:1.8V +/-10%)K9XXGXXUXM:Output Load (Vcc:3.0V +/-10%) 1 TTL GATE and CL=30pF1 TTL GATE and CL=50pF K9XXGXXUXM:Output Load (Vcc:3.3V +/-10%)- 1 TTL GATE and CL=100pFMODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP and PRE should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP PRE Mode H L L H X X Read Mode Command Input L H L H X X Address Input(5clock)H L L H H X Write ModeCommand Input L H L H H X Address Input(5clock)L L L HH X Data Input L L L H X X Data Output X X X X H X X During Read(Busy)X X X X X H X During Program(Busy)X X X X X H X During Erase(Busy)X X (1)X X X L XWrite Protect XXHXX0V/V CC (2)0V/V CC (2) Stand-byAC Characteristics for OperationNOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.ParameterSymbol Min Min Max Max Unit K9K2GXXQ0MK9K2GXXU0MK9K2GXXQ0MK9K2GXXU0MData Transfer from Cell to Register t R --2525µs ALE to RE Delay t AR 1010--ns CLE to RE Delay t CLR 1010--ns Ready to RE Low t RR 2020--ns RE Pulse Width t RP 6025--ns WE High to Busy t WB --100100ns Read Cycle Time t RC 8050--ns RE Access Time t REA --6030ns CE Access Time t CEA --7545ns RE High to Output Hi-Z t RHZ --3030ns CE High to Output Hi-Z t CHZ --2020ns RE or CE High to Output hold t OH 1515--ns RE High Hold Time t REH 2015--ns Output Hi-Z to RE Low t IR 00--ns WE High to RE Low t WHR 6060--ns Device Resetting Time (Read/Program/Erase)t RST--5/10/500(1)5/10/500(1)µsAC Timing Characteristics for Command / Address / Data InputNOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.Parameter Symbol MinMaxUnit K9K2GXXQ0MK9K2GXXU0MK9K2GXXQ0MK9K2GXXU0MCLE setup Time t CLS 00--ns CLE Hold Time t CLH 1010--ns CE setup Time t CS 00--ns CE Hold Time t CH 1010--ns WE Pulse Width t WP 6025(1)--ns ALE setup Time t ALS 00--ns ALE Hold Time t ALH 1010--ns Data setup Time t DS 2020--ns Data Hold Time t DH 1010--ns Write Cycle Time t WC 8045--ns WE High Hold Timet WH2015--nsProgram / Erase CharacteristicsNOTE : 1. Max. time of t CBSY depends on timing between internal program completion and data inParameterSym-Min Typ Max Unit Program Time t PROG -300700µs Dummy Busy Time for Cache Program t CBSY3700µs Number of Partial Program Cycles in the Same Page Main Array Nop --4cycles Spare Array--4cycles Block Erase Timet BERS-23msNAND Flash Technical NotesIdentifying Invalid Block(s)Invalid Block(s)Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-mation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the perfor-mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaran-teed to be a valid block, does not require Error Correction up to 1K program/erase cycles.All device locations are erased(FFh for X8, FFFFh for X16) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 1st byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh(X8) or non-FFFFh(X16) data at the column address of 2048(X8 device) or 1024(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block information is prohibited.*Check "FFh( or FFFFh)" at the column address Figure 3. Flow chart to create invalid block table.StartSet Block Address = 0Check "FFh Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInvalid Block(s) Tableof the 1st and 2nd page in the block2048(X8 device) or 1024(X16 device)or FFFFh" ?NAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?Write 00hI/O 0 = 0 ?No*If ECC is used, this verification Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterWrite AddressWait for tR TimeVerify DataFailProgram Completedor R/B = 1 ?Program ErrorYesNo Yes*Program ErrorPass: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.* operation is not needed.Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block.To improve the efficiency of mem-ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure Mode Detection and Countermeasure sequenceWriteErase FailureStatus Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block ReplacementRead back ( Verify after Program) --> Block Replacementor ECC Correction ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionWrite 30hRead ID OperationCECLEWEALERE90hRead ID CommandMaker Code Device Code00h EChDevice t REAAddress. 1cycleXXh4th cyc.*ID Defintition Table90 ID : Access command = 90HDescription1st Byte 2nd Byte 3rd Byte 4th ByteMaker Code Device Code Don’t carePage Size, Block Size, Spare Size, OrganizationI/Oxt ARCode*Device Device Code*(2nd Cycle)4th Cycle*K9K2G08Q0M AAh 15h K9K2G08U0M DAh 15h K9K2G16Q0M BAh 55h K9K2G16U0M CAh55hK9W4G08U1M Same as each K9K2G08U0M in it K9W4G16U1MSame as each K9K2G16U0M in it。

NAND的几个参数，指标缩写：SLC: Single-Level CellMLC: Multi-Level CellSB: Small Block=(512+16)Bytes/pageLB: Large Block=(2048+64)Bytes/pageDDP: Double Die PackageQDP: Quadruple Die PackageDSP: Double Stack Package1P,2P,4P: Plane 与CE无关举例SAMSUNG MLC---K9G4G08U0M为普通MLC,K9L8G08U0M(DDP)为双片K9G4G08U0M组成K9G4G08U0M为DDP,有4个Plane,1个CE,1个R/B,每个Plane由1024个Block和(2048+64)Byte page registers组成,一个Block有128个Page,每个Page有(2048+64)Byte,所以总容量为4*[1024*128*(2048+64)Byte+(2048+64)Byte]=8Gbit+256Mbit,MLC按page读，写（编程），按block删。

内部Page寄存器大小与每个page的大小相同，以便于同步写.K9L8G08U0M虽然由2个K9G4G08U0M die封装而成,但仅有一个CE和一个R/B,其控制芯片#1 #2读写是由内部的R/B(#1),R/B(#2)信号来实现,Interleaving(交叉存取)过程中,Host通过发送F1h来询问芯片#1的状态,发送F2h来询问chip #2的状态.K9L8G08U0M(DDP) 由2个K9G4G08U0M芯片封装而成K9HAG08U1M(QDP) 由2个K9L8G08U0M芯片封装而成，CE1和CE2分离,R/B1和R/B2分离。

K9MBG08U5M (DSP) 由4个K9L8G08U0M芯片封装（2片堆叠），CE1/CE2/CE3/CE4 ,R/B1 R/B2 R/B3 R/B4都是分离的。

2009-12-04 20:02:47| 分类：共同分享（穹内同|字号订阅/blog/usbking/article/b0-i5849820.html从SUMSUNG闪存芯片编号识容量三星的闪存芯片均以K9打头，与容量相关的字段是从第4位到第7位。

第4～5位表示闪存密度，12代表512M、16代表16M、28代表128M、32代表32M、40代表4M、56代表256M、64代表64M、80代表8M、1G代表1G 、2G代表2G、4G代表4G、8G 代表8G、00代表没有。

第6～7位表示闪存结构，00代表没有、08代表×8. 16代表×16. 32代表×32。

闪存芯片的容量=闪存密度×闪存结构÷8通过上述公式就可以计算出闪存芯片的真实容量了编号为K9K1G08U0M-YC80的SUMSUNG闪存芯片。

这块闪存芯片的规格为：128M×8bit、50ns速度，单颗容量128MB。

工作电压2.4～2.9V。

芯片编号K9F5608U0A，32M×8bit规格50ns速度，单颗容量32MB。

工作电压2.7～3.6V，内部分成块写区域大小（16K＋512）。

三星型号详解K9×××××：Nand FlashK8×××××：Nor FlashK7×××××：Sync SRAM(同步SRAM，带clock，速度快，网络产品，6个晶体管)K6×××××：Aync SRAM(异步SRAM，不带clock，速度快，手机产品，6个晶体管)K5×××××：MCP（相当于K1+K8+K9）K4×××××：DRAMK3×××××：Mask RomK2×××××：FRAMK1×××××：utRAM(使用SRAM技术，但只有2个晶体管跟1个电容，所以比SRAM功耗大，但成本低)samsung 编号：K9LAG08U0M，容量为2G，以K9L为开头的三星闪存一般都为MLC闪存，使用MLC闪存是大势所趋* K9K8G(1GB)、K9W8G(1GB)、K9WAG(2GB)* K9x1Gxxxxx = 1Gb (GigaBit) = 128MB (MegaByte)* K9x2Gxxxxx = 2Gb (GigaBit) = 256MB (MegaByte)* K9x4Gxxxxx = 4Gb (GigaBit) = 512MB (MegaByte)* K9x8Gxxxxx = 8Gb (GigaBit) = 1024MB (MegaByte)* (1 Byte = 8 bits)SAMSUNG K9F2808U0B-YCB0 32MBK9F2808U0C-VCB0 32MBK9F5608U0B-YCB0 16MBK9F5608U0C-YCB0 16MBK9F1208U0M-YCB0 64MBK9F1208U0A-YCB0 64MBK9F1208U0A-YIB0 64MBK9F1208U0A-VCB0 64MBK9K1G08U0A-YCB0 128MBK9K1G08U0M-YCB0 128MBK9K1G08U0M-VIB0 128MBK9F1G08U0M-YCB0 128MBK9F1G08U0A-YCB0 128MBK9F1G08U0M-VCB0 128MBK9F1G08U0M-VIB0 128MBK9F1G08U0M-FIB0 128MBK9K2G08U0M-YCB0 256MBK9K2G08U0A-FIB0 (90nm) 256MBK9K2G08U0M-VCB0 256MBK9K2G08U0M-VIB0 256MBK9K2G08U0A-VIB0 (90nm) 256MBK9F2G08U0M-YCB0 (90nm) 256MBK9K4G08U0M-YCB0 (90nm) 512MBK9K4G08U0M-YCBO(90nm) 512MBK9K4G08U0M-PIB0(90nm) 512MBK9W8G08U1M-YCB0(90nm) 1GBK9W8G08U1M-YIB0(90nm) 1GBK9WAG08U1M 2GMNAND闪存芯片, 一般都是Samsung 或Hynix 芯片. SAMSUNG闪存的型号及对应容量:K9x1Gxxxxx = 1Gb (GigaBit) = 128MB (MegaByte)K9x2Gxxxxx = 2Gb (GigaBit) = 256MB (MegaByte)K9x4Gxxxxx = 4Gb (GigaBit) = 512MB (MegaByte)K9x8Gxxxxx = 8Gb (GigaBit) = 1024MB (MegaByte)(1 Byte = 8 bits)Hynix闪存的型号及对应容量:HY27UH081G2M = 1Gb (GigaBit) = 128MB (MegaByte) HY27UH082G2M = 2Gb (GigaBit) = 256MB (MegaByte) HY27UH084G2M = 4Gb (GigaBit) = 512MB (MegaByte) HY27UH088G2M = 8Gb (GigaBit) = 1024MB (MegaByte)(1 Byte = 8 bits)Part No Description MfgNANDFLASHHY27US08281A-T(P)CB 16Mx8 HYNIXHY27US08561A-T(P)CB 32Mx8 HYNIXHY27US08121A-T(P)CB 64Mx8 HYNIXHY27UF081G2M-T(P)CB 128Mx8 HYNIXHY27UF082G2M-T(P)CB 256Mx8 HYNIXHY27UF082G2A-TPCB 256Mx8 HYNIXHY27UG084G2M-TPCB 512Mx8 HYNIXHY27UF084G2M-TPCB 512Mx8 HYNIXHY27UT084G2M-TPCB 512Mx8 HYNIXHY27UH088G2M-TPCB 1Gx8 HYNIXHY27UU085G2M-TPCB 1Gx8 HYNIXHynix闪存的型号及对应容量:HY27UH081G2M = 1Gb (GigaBit) = 128MB (MegaByte); HY27UH082G2M = 2Gb (GigaBit) = 256MB (MegaByte); HY27UH084G2M = 4Gb (GigaBit) = 512MB (MegaByte); HY27UH088G2M = 8Gb (GigaBit) = 1024MB (MegaByte)ATJ2051/ATJ2085主控支持的闪存FLASH型号列表品牌型号内存ATJ2085(2051) samsung K9K4G08U0M512M ysamsung K9W4G08U1M 512M ysamsung K9W8G08U1M 1GB ysamsung K9F4G08U0M 512M ysamsung K9F4G08U0A 512M ysamsung K9K8G08U0M1G ysamsung K9K8G08U0A 1G nsamsung K9WAG08U1M2G ysamsung K9G4G08U0M 512M nsamsung K9L8G08U0M 1G nsamsung K9HAG08U1M 2G nHynix HY27UG084G1M512M yHynix HY27UG084G2M512M yHynix HY27UH084G1M512M nHynix HY27UH084G2M512M y Hynix HY27UG088G2M1G y Hynix HY27UG088G5M1G n Hynix HY27UG088GDM1G n Hynix HY27UH088G2M 1G y Hynix HY27UH088GDM 1G n Hynix HY27UH08AG5M 2G n Hynix HY27UH08AGDM 2G n Hynix HY27UF084G2M 512M y Hynix HY27UG088G5M 1GB n Hynix HY27UU088G5M 1G n Hynix HY27UV08AG5M 2G n Hynix HY27UT084G2A, 512M n Hynix HY27UT084G2M 512M n Hynix HY27UU088G 1GB nHynix HY27UU8G5M(MLC)1GB n Hynix HY27UT4G2M(MLC) 512M n Hynix HY27UVAG5M(MLC) 2GB nHynix HY27US08561M VPCB 428A 32MB HY27US08561M TPIB 427A 32MBHY27US08121M TCB 64MBHY27US08121M TPIB 407T 64MBHY27US08121M TCB 416A 64MBHY27US08121M TCB 422A 64MBHY27US08121M TCB 426A 64MBHY27US08121M TPCB 427B 64MBHY27US08121M VPCB 429A 64MBHY27UA081G1M TCB 128MBHY27UA081G1M TPCB 128MBHY27UA081G1M TCB 423A 128MBHY27UG082G2M 256MBHY27UH084G2M 512MBHY27UG088G5M 1GBHY27UH088G2M 1GBHY27UH08AG5M 2GBTOSHIBA TC58128AFT 16MBTC58128AFTI 16MBTC58DVM72A1FT00/05 16MBTC58256AFT 32MBTC58NVM8S0AFTI0 32MBTC58DVM82A1FT00/05 32MBTC58DVM82A1FTI0 32MBTC58512FT 64MBTC58DVM92A1FT00/05 64MBTH58100FT 128MBTC58DVG02A1FT00/05 128MBTC58NVG0S3AFT00/05 128MBTC58NVG0S3AFTI5 128MBTH58NVG1S3AFT00/05 256MBTH58NVG1S3AFTI0 256MBTC58NVG1S3BFT00 256MBTC58005FT 64MBTC58DVM94B1FT00/05 64MBTC58010FT 128MBTC58DVG04B1FT00/05 128MBTC58DVG14B1FT00/05 256MBTC58DVG14B1FTI0 256MBTH58DVG24B1FT00/05 512MBTC58NVG1D4BFT00 256MBTC58NVG1D4BFT00 256MBTC58NVG2D4BFT00 512MBTH58NVG3D4BFT00 1GBTH58NVG3D4BFTI0 1GBTC58NVG3D4CTG10 1GBTH58NVG4D4BTG20 2GBSANDISK SDTNFAH-128, SDTNGAHE0-128 16M SDTNFAH-256, SDTNGAHE0-256 32M SDTNFAH-512, SDTNGAHE0-512 64M SDTNFCH-512, SDTNGCHE0-512 64M SDTNFBH-1024, SDTNGBHE0-1024 128M SDTNFCH-1024, SDTNGCHE0-1024 128MSDTNFDH-2048, SDTNGDHE0-2048 256MMicron MT29F2G08A 256MBMT29F4G08B 256MBMT29F4G08BAB 51 从SUMSUNG闪存芯片编号识容量从SUMSUNG闪存芯片编号识容量三星的闪存芯片均以K9打头，与容量相关的字段是从第4位到第7位。

K9XXG08UXAINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.11.01.1RemarkAdvance PreliminaryFinal History1. Initial issue1. Leaded part is eliminated2. tRHW is definedment of "Addressing for program operation" is added (p.17)1. 4GB DSP is addedDraft DateNov. 09. 2005Jan. 10. 2006Mar. 7. 2006July 18th 2006GENERAL DESCRIPTIONFEATURES• Voltage Supply - 2.70V ~ 3.60V • Organization- Memory Cell Array : (1G + 32M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.) * K9NBG08U5A : 50ns(Min.)1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9K8G08U0A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-ICB0/IIB052 - Pin TLGA (12 x 17 / 1.0 mm pitch) - K9NBG08U5A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)Offered in 1G x 8bit, the K9K8G08U0A is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns(K9NBG08U5A : 50ns) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as com-mand input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0A ′s extended reli-ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. TheK9K8G08U0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.An ultra high density solution having two 8Gb stacked with two chip selects is also available in standard TSOPI package and another ultra high density solution having two 16Gb TSOPI package stacked with four chip selects is also available in TSOPI-DSP .PRODUCT LISTPart Number Vcc RangeOrganizationPKG Type K9K8G08U0A-Y 2.70 ~ 3.60VX8TSOP1K9WA G08U1A-Y K9WA G08U1A-I 52TLGA K9NBG08U5A-PTSOP1-DSP1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View1.0(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321K9WAG08U1A - ICB0 / IIB052-TLGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NCNCNCNCNCNC NCVccVcc VssVssVss /RE1/RE2/CE1/CE2CLE1CLE2ALE1ALE2/WE1/WE2/WP1/WP2R/B1R/B2VssIO0-1IO0-2IO1-1IO1-2IO2-1IO3-1IO2-2IO3-2IO4-1IO4-2IO5-1IO5-2IO6-1IO6-2IO7-1IO7-2∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.There are two CE pins (CE 1 & CE 2) in the K9WAG08U1A and four CE pins (CE 1 & CE 2 & CE 3 & CE 4) in the K9NBG08U5A.There are two R/B pins (R/B1 & R/B2) in the K9WAG08U1A and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the K9NBG08U5A.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation.Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation. CE2CHIP ENABLEThe CE2 input enables the second K9K8G08U0AREREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K8G08U0A is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0A. The K9K8G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0A.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.The K9WAG08U1A is composed of two K9K8G08U0A chips which are selected separately by each CE1 and CE2 and the K9NBG08U5A is composed of four K9K8G08U0A chips which are selected seperately by each CE1, CE2, CE3 and CE4. Therefore, in terms of each CE, the basic operations of K9WAG08U0A and K9NBG08U5A are same with K9K8G08U0A except some AC/DC charateristics.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hTwo-Plane Page Program(4)80h---11h81h---10hCopy-Back Program85h10hTwo-Plane Copy-Back Program(4)85h---11h81h---10hBlock Erase60h D0hTwo-Plane Block Erase60h---60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh OChip1 Status(3)F1h OChip2 Status(3)F2h ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.3. Interleave-operation between two chips is allowed.It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.4.Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.3. The typical value of the K9WAG08U1A’s I SB 2 is 40µA and the maximum value is 200µA.4. The typical value of the K9NBG08U5A’s I SB 2 is 80µA and the maximum value is 400µA.5. The maximum value of K9WAG08U1A-P’s I LI and I LO is ±40µA , the maximum value of K9WAG08U1A-I’s I LI and I LO is ±20µA .6. The maximum value of K9NBG08U5A’s I LI and I LO is ±80µA.ParameterSymbol Test ConditionsMinTypMaxUnitOperating CurrentPage Read withSerial Access I CC 1tRC=25ns(K9NBG08U5A: 50ns)CE=V IL, I OUT =0mA-2535mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -20100µAInput Leakage Current I LI V IN =0 to Vcc(max)--±20Output Leakage Current I LO V OUT =0 to Vcc(max)--±20Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH I OH =-400µA 2.4--Output Low Voltage Level V OL I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXG08UXA-XCB0 :T A =0 to 70°C, K9XXG08UXA-XIB0:T A =-40 to 85°C)ParameterSymbol Min Typ.Max Unit Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc+0.3 (<4.6V)Temperature Under Bias K9XXG08UXA-XCB0T BIAS -10 to +125°C K9XXG08UXA-XIB0-40 to +125Storage Temperature K9XXG08UXA-XCB0T STG-65 to +150°CK9XXG08UXA-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1A-IXB0’s capacitance(I/O, Input) is 20pF.ItemSymbol Test Condition Min MaxUnit K9K8G08U0AK9WAG08U1A*K9NBG08U5AInput/Output Capaci-C I/O V IL =0V -204080pF Input CapacitanceC INV IN =0V-204080pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.* : Each K9K8G08U0A chip in the K9WAG08U1A and K9NBG08U5A has Maximun 160 invalid blocks.Parameter Symbol Min Typ.Max Unit K9K8G08U0A N VB 8,032-8,192Blocks K9WAG08U1A N VB 16,064*-16,384*Blocks K9NBG08U5AN VB32,128*32,768*BlocksAC TEST CONDITION(K9XXG08UXA-XCB0: T A =0 to 70°C, K9XXG08UXA-XIB0:T A =-40 to 85°C ,K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9XXG08UXA Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF (K9K8G08U0A-P/K9WAG08U1A-I) 1 TTL GATE and CL=30pF (K9WAG08U1A-P) 1 TTL GATE and CL=30pF (K9NBG08U5A-P)MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byProgram / Erase CharacteristicsNOTE : 1. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C tempera-ture .ParameterSymbol Min Typ Max Unit Program Time t PROG -200700µs Dummy Busy Time for Two-Plane Page Program t DBSY -0.51µs Number of Partial Program Cycles Nop --4cycles Block Erase Timet BERS- 1.52msAC Timing Characteristics for Command / Address / Data InputNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleParameterSymbol MinMaxUnitK9NBG08U5AK9K8G08U0A K9NBG08U5AK9K8G08U0A K9WAG08U1AK9WAG08U1ACLE Setup Time t CLS (1)2512--ns CLE Hold Time t CLH 105--ns CE Setup Time t CS (1)3520--ns CE Hold Time t CH 105--ns WE Pulse Width t WP 2512--ns ALE Setup Time t ALS (1)2512--ns ALE Hold Time t ALH 105--ns Data Setup Time t DS (1)2012--ns Data Hold Time t DH 105--ns Write Cycle Time t WC 4525--ns WE High Hold Timet WH 1510--ns Address to Data Loading Timet ADL (2)7070--nsAC Characteristics for OperationNOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.ParameterSymbol MinMaxUnitK9NBG08U5AK9K8G08U0A K9NBG08U5AK9K8G08U0A K9WAG08U1AK9WAG08U1AData Transfer from Cell to Register t R -2020µs ALE to RE Delay t AR 1010-ns CLE to RE Delay t CLR 1010-ns Ready to RE Low t RR 2020-ns RE Pulse Width t RP 2512-ns WE High to Busy t WB --100100ns Read Cycle Time t RC 5025--ns RE Access Time t REA --3020ns CE Access Time t CEA --4525ns RE High to Output Hi-Z t RHZ --100100ns CE High to Output Hi-Z t CHZ --3030ns RE High to Output hold t RHOH 1515--ns RE Low to Output hold t RLOH -5--ns CE High to Output hold t COH 1515--ns RE High Hold Time t REH 1510--ns Output Hi-Z to RE Low t IR 00--ns RE High to WE Low t RHW 100100--ns WE High to RE Lowt WHR 6060--ns Device Resetting Time(Read/Program/Erase)t RST--5/10/500(1)5/10/500(1)µsNAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block table.StartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9K8G08U0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn’t need to be page 0.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Interleave Page ProgramK9K8G08U0A is composed of two K9F4G08U0As. K9K8G08U0A provides interleaving operation between two K9F4G08U0As.This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.At first, the host issues page program command to one of the K9F4G08U0A chips, say K9F4G08U0A(chip #1). Due to this K9K8G08U0A goes into busy state. During this time, K9F4G08U0A(chip #2) is in ready state. So it can execute the page program command issued by the host.After the execution of page program by K9F4G08U0A(chip #1), it can execute another page program regardless of the K9F4G08U0A(chip #2). Before that the host needs to check the status of K9F4G08U0A(chip #1) by issuing F1h command. Only when the status of K9F4G08U0A(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0A(chip #1) is in busy state, the host has to wait for the K9F4G08U0A(chip #1) to get into ready state.Similarly, K9F4G08U0A chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0A(chip #2) by issuing F2h command. When the K9F4G08U0A(chip #2) shows ready state, host can issue another page program command to K9F4G08U0A(chip #2).This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation.NOTES : During interleave operations, 70h command is prohibited.R / B (#1)b u s y o f C h i p #1I /O X80h10h C o m m a n d A 30 : L o w A d d & D a t a80h 10h A 30 : H i g h A d d & D a t ab u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e P a g e P r o g r a m≈≈≈F 1h o r F 2h A B CDa n o t h e r p a g e p r o g r a m o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a p a g e p r o g r a m o p e r a t i o n a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a p a g e p r o g r a m c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g p a g e p r o g r a m o p e r a t i o n .S t a t e C : P a g e p r o g r a m o n c h i p #1 i s t e r m i n a t e d , b u t p a g e p r o g r a m o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r p a g e p r o g r a m c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e p a g e p r o g r a m o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x h。