信息科学与工程学院EDA课程设计报告VGA接口显示器显示汉字设计组员姓名：班级：指导老师：时间：目录摘要 (3)一、设计任务： (3)二、VGA显示原理： (3)VGA的颜色编码： (5)三、设计方案： (5)四、调试过程： (6)五、VGA显示功能图： (6)1顶层模块： (8)2分频模块： (8)3点阵模块： (9)4时序控制模块： (13)八、改进方向： (16)总结 (17)参考文献 (17)摘要由于FPGA芯片具有可靠性高、编程灵活、体积小等优点，采用其控制VGA 接口进行汉字显示，有效地解决了通用处理器控制VGA接口显示汉字的缺点。
关键词：显示绘图陈列;现场可编程门陈列;VGA汉字显示一、设计任务：使用VGA接口显示器显示汉字，此次演示显示“中国”两个字。
二、VGA显示原理：VGA的汉字显示是利用VGA显示的原理，使用正确的时序信号对VGA接口相应的管脚进行控制输出RGB颜色信息来显示相应的字符信息其中VGA显示原理及时序信号的控制必须遵循VGA的工业标准。
显示处理前端中的SRAM 中存储的每一位数据对应相应LCD显示屏上一个像素点的亮和灭，“1”表示亮，“0”表示灭。
在显示设备上显示汉字也就是按照汉字的点阵图向显示器上输出1或0的高低电平，从而在显示器上显示出具体的汉字。
常见的彩色显示器，一般由CRT（阴极射线管）构成，彩色是由G、R、B （绿：Green，红：Red，蓝：Blue）三基色组成。
显示是用逐行扫描的方式解决，阴极射线枪发出电子束打在涂有荧光粉的荧光屏上，产生GRB三基色，合成一个彩色像素。
扫描从屏幕的左边下一行的起始位置，在这期间，CRT对电子束进行消隐，每行结束时，用行同步信号进行行同步；扫描完所有行，用场同步信号进行场同步，并使扫描回到屏幕的左上方，同时进行行场消隐，预备下一场的扫描。
对于普通的VGA显示器，其引出线共含5个信号：G、R、B：三基色信号：HS：行同步信号；VS：场同步信号。
对于5个信号的时序驱动，对于VGA显示器要严格遵循“VGA工业标准”，即640X480X60HZ模式。
通常我们用显示器都满足工业标准，因此我们设计VGA控制时要参考显示器的技术规则。
上述描述了行场扫描的时序要求：扫描的时候从屏幕的左上方开始，从左到右，从上到下进行扫描，每次扫完一行时候，电子束回到屏幕左边开始进行下一行的扫描，在这个期间中，CRT会对电子束进行行消隐，从行同步头开始扫描，每行结束后，用行同步信号进行行同步；扫描完所有行，用场同步信号进行场同步，并使扫描回到屏幕的左上方，同时行场消隐，预备下一场的扫描。
所以时钟的频率为行场周期乘上频率525*800*60Hz约25MHz,行频为525*60=31.5KHz,其中60Hz表示场频率。
VGA工业标准所要求频率：时钟频率（Clock frequency）:25.175MHz(像素输出频率)；行频（Line frequency ）:31469Hz;场频（Field）:59.94Hz(每秒图像刷新频率)；VGA的颜色编码：三、设计方案：FPGA芯片作为中央控制器控制整个系统的处理，根据自顶向下的设计流程，按照层次化、结构化的设计方法可以将FPGA系统划分为以下几个模块：顶层模块、分频模块、点阵模块、时序控制模块。
系统工作原理：FPGA芯片读人配置信息，配置完成后，FPGA进人工作状态，将要显示的汉字的字模信息初始化到单口RAM 中，由系统时钟产生时序，程序根据时序信息控制VGA接口输出行、场同步及颜色信息到显示器上。
注意问题：一个时序驱动，时序偏差可能导致不正常的显示，另一个VGA 信号电平驱动；上图描述VGA基本显示本次我们的也是在这上面进行改进，我们将50MHz 的频率进行二分频，作为时钟频率输入然后进入显示控制处理电路把RGB三基色以及进行的行场同步信号处理经过控制后送入显示设备。
框架图：四、调试过程：本次调试过程中,程序出现了一些小小问题，虽然后面能够显示汉字，但修改了下程序颜色并不能很好的控制，进行了多次的程序改进以及进行调试认为设置的屏幕大小让汉字的颜色变化不是很明显，也有可能是下载程序时没有很好的下载，用的还是以前下载的程序导致颜色并没有改变，我们还是有所不足，需要更多的实践经验。
五、VGA显示功能图：引脚图：仿真图：导出电路图:六、使用说明：1.打开QuartusⅡ新建工程，新建VHDL语言等一系列基本步骤。
2.输入下列程序，编译，仿真，锁定引脚后在编译下载。
锁定引脚要注意几个输入引脚与几个输出引脚，要根据你所拥有的芯片及其原理图的引脚进行锁定，否则会出现问题，上述引脚图可以进行参考。
3.下载完成后如果在笔记本上显示结果还需要显示器的数据连接线且还要装驱动程序,个人建议还是在台式电脑上进行实验结果操作，把实验板通电后接上与电脑显示器的连接线按下你锁定的CLK50_in键后结果就能显示“中国”。
七、程序设计模块：根据自顶向下设计方法层，首先定义顶功能块。
顶层模块处于重要的位置，定义好顶层模块功能后，才能进而分析哪些是构成顶层模块必要的子模块，然后进一步对各个子模块进行分解，直到达到无法进一步分解的底层功能块。
顶层模块主要负责规定各个模块之间的数据信号和控制信号的连接关系，也就是实例化各子模块，并且接收RAM读取控制模块传来的汉字字模信息数据流，根据数据流信息中比特位为1的位赋予红色，为0的位赋予蓝色，即用红色表示汉字“中国”，用蓝色来表示点阵点背景。
1顶层模块：定义顶层功能块，连接各模块数据信号和控制信号。
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity VGA_Module isPort ( clk50_in : in std_logic; --时钟频率50MHZRed_out : out std_logic; --定义红色输出信号Green_out : out std_logic; --定义绿色输出信号Blue_out : out std_logic; --定义蓝色输出信号hs_out : out std_logic; --水平同步时序输出vs_out : out std_logic); --垂直同步时序输出end VGA_Module;2分频模块：时序的驱动是设计VGA显示的控制需要注意的一个重要问题，这也是实验是否成功的关键设计。
时序不正确，必定不能正常显示，有时甚至会损坏显示设备。
因此，对于时序的设计我们必须遵循VGA的工业标准，在设计中使用的分辨率为640×480，实验采用的实验板提供的时钟频率为50 MHz，因此必须将系统进行分频设计，即进行二分频的设计。
50 MHz的时钟频率经过分频后得到实验所需的25MHz频率，此频率将为顶层控制模块提供VGA控制模块和RA M读取控制模块的系统时钟。
architectureBehavioral of VGA_Module issignal Clk25: std_logic;--时钟分频为25 MHzsignal Horizontal_Counter: std_logic_vector (9 downto 0); --结构体水平信号定义signal Vertical_Counter: std_logic_vector (9 downto 0); ---结构体垂直信号定义begin--Generate 25Mhz Clock --形成所需的25MHz频率process (clk50_in) --进程时钟频率为50 MHz语句执行beginif clk50_in'event and clk50_in='1' thenif (Clk25 = '0')thenClk25 <= '1' after 2 ns;elseClk25 <= '0' after 2 ns;end if;end if;end process;process (Clk25)TYPE Screen_Line1 is ARRAY(0 to 15, 0 to 99) OF std_logic;CONSTANT char_L1 : Screen_Line1 :=(3点阵模块：640X480X60HZ模式产生显示范围，控制点阵行（100个点）X列（16个点）的显示和消隐。
点阵点区汉字显示位置指定的行用高电平1表示，未显示位置用低电平0表示，从而在显示器上显示出具体的汉字。
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