AD8353-EVAL中文资料

REV.0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© 2002 Analog Devices, Inc. All rights reserved.EVAL-AD8183EB/EVAL-AD8185EBAD8183/AD8185 Evaluation BoardsORDERING GUIDEModelPackage DescriptionAD8183-EVAL Evaluation Board AD8185-EVALEvaluation BoardCAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the EVAL-AD8183EB/EVAL-AD8185EB features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, properESD precautions are recommended to avoid performance degradation or loss of functionality.BOARD DESCRIPTIONPower and GroundThere are three power supply pins on the board. V CC is +5V analog, V EE is –5 V analog, and DVCC is +5 V digital. These three power supply pins should be connected to good quality,low noise supplies. If the same ±5 V power supply is used for both analog and digital, separate cables should be run from the power supply to the evaluation board’s analog and digital power supply pins.Three 10 m F tantalum capacitors (C1–C3) are located under the power connector to decouple the power supplies as they first enter the board. As the three supplies get close to the part, they are again decoupled with 0.1 m F ceramic capacitors (C4–C6).Finally, each power pin of the device is locally decoupled with a 0.01 m F ceramic capacitor (C7–C15).The board has a separate analog and digital ground plane. With the jumper at W5 installed, these two ground planes are tied together on the board. Generally, this jumper should remain installed.Inputs and OutputsThe evaluation board has been carefully laid out to demonstrate the high speed performance of the device. Optimized for video applications, all signal inputs are terminated with 75 W resistors to ground (R1–R6). The three outputs are back-terminated with 75 W series resistors (R12–R14). Stripline techniques are used to achieve a 75 W characteristic impedance on the input and output lines. See Figure 1 for the arrangement of the PCB layers.TOP LAYER75⍀SIGNAL LAYER POWER LAYER50⍀SIGNAL LAYERFigure 1.PCB DimensionsIn addition, 75 W BNC connectors are used on the six inputs (J1–J6) and three outputs (J7–J9). The connectors are arranged in a crescent around the device. This results in all the input and output signal traces having the same length. Unused regions of the multilayer board are filled up with ground planes. As a result, the input and output traces, in addition to having a con-trolled impedance, are well shielded.SEL A /B and OESEL A /B (Pin 22 of the device) allows the A or B inputs to be selected.When SEL A /B is at logic low, (equal to or less than 0.8 V),inputs 0A, 1A, and 2A are directed to OUTPUTs 0, 1, and 2,respectively. When SEL A /B is at logic high, (equal to or greater than 2.0 V), inputs 0B, 1B, and 2B are directed to OUTPUTs 0, 1, and 2, respectively.There are two ways to provide SEL A /B to the device: using a jumper or a BNC connection. With the jumper in the W4 posi-tion, SEL A /B is tied to ground. This selects the A inputs.With the jumper in the W3 position, SEL A /B is tied to 5 V through pull-up resistor R15. This selects the B inputs.If faster use of SEL A /B is desired, the 50 W BNC connector at J10 can be used. If J10 is used, there must NOT be a jumper on W3 and W4. Microstrip line techniques provide a 50 W charac-teristic impedance from J10 to the device. Please refer to Figure 1for the arrangement of the PCB layers. If J10 is used, the user may wish to install a 50 W termination resistor at R10.OE (Pin 23) allows the three outputs to be enabled or disabled.When OE is at logic low, (equal to or less than 0.8 V), OUTPUTs 0, 1, and 2 are enabled. When OE is at logic high, (equal to or greater than 2.0 V), OUTPUTs 0, 1, and 2 are disabled (placed into a high impedance state).REV. 0–2–EVAL-AD8183EB/EVAL-AD8185EBOnce again, there are two different ways to provide OE to the device: using a jumper or a BNC connection. With the jumper in the W2 position, OE is tied to ground. This enables the outputs.With the jumper in the W1 position, OE is tied to 5 V through pull-up resistor R16. This selects “Hi Z,” or high impedance,and the outputs are disabled.A /BFigure 2.Evaluation Board SchematicIf faster use of OE is desired, the 50 W BNC connector at J11can be used. If J11 is used, there must NOT be a jumper on W1and W2. Microstrip line techniques provide a 50 W characteris-tic impedance from J11 to the device. Please refer to Figure 1for the arrangement of the PCB layers. If J11 is used, the user may wish to install a 50 W termination resistor at R11.REV. 0EVAL-AD8183EB/EVAL-AD8185EB–3–Figure 3.Component Side SilkscreenFigure 4.Board Layout (Component Side)EVAL-AD8183EB/EVAL-AD8185EBFigure 5.Board Layout (75 WSignal Layer)–4–REV. 0REV. 0EVAL-AD8183EB/EVAL-AD8185EB–5–Figure 7.Board Layout (Circuit Side;) 50 WSignal LayerFigure 8.Circuit Side Silkscreen–6––7–)(2/21––5823C.A.S.UNIDETNIRP –8–。

AD8331 Evaluation BoardAD8331-EVAL Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.GENERAL DESCRIPTIONThe AD8331 evaluation board is a platform for testing and evaluating the AD8331 variable gain amplifier (VGA). The board is provided completely assembled and tested; therefore, the user only needs to connect an input signal, V GAIN sources, and a single 5 V power supply.USER SUPPLIED OPTIONAL COMPONENTSAs shown in the schematic in Figure 2 (fixed), the board has provisions for optional components. The basic components are shown in black, and the optional components, which can be installed at the user’s discretion, are shown in grey.The input impedance of the LNA is configured for 50 Ω to accommodate most signal generators and network analyzers. Input impedances up to 6 kΩ can be realized by changing the values of RFB and CSH. Consult the AD8331 data sheet for details on this circuit feature. See Table 1 for typical values of input impedance and corresponding components.Table 1. LNA External Component Values for Common Source ImpedancesR IN (Ω) RFB (Ω, Nearest 1% Value) CSH (pF)50 274 22 75 412 12 100 562 8 200 1.13k1.2 500 3.01k None 6 k ∞ NoneThe board is designed for 0805 size surface-mount components. Space is provided for various popular configurations of overload diodes at locations D1, D2, or D3.The LNA can be evaluated on its own. If so used alone, it mustbe ac-coupled with capacitors at its differential output. Typical values are 0.1 μF, and they are installed at Position C1 and Position C2.Resistors of 0 Ω are installed at R4 and R8, unless capacitive loads larger than 10 pF are connected to the SMA connectors, LON, and LOP (such as coaxial cables.) In that event, small value resistors (68 Ω to 100 Ω) must be installed at R4 and R8.A resistor can be inserted at RCLMP if output clamping is desired. Consult the AD8331 data sheet for appropriate values.4589-1Figure 1. AD8331-EVAL Top ViewThe preferred signal detection method is a differential probe connected to VO, as shown in Figure 3. Single-ended loads can be connected using the board edge SMA connector, VOH. Be sure to take into account the 25.8 dB attenuation incurred when using the board in this manner.MEASUREMENT SETUPThe basic board connection for measuring bandwidth is shown in Figure 3. A 5 V, 100 mA minimum power supply, and a low noise, voltage reference supply for GAIN is required. Table 2 lists jumpers, and Figure 3 shows their function and positions. Table 2. Jumper FunctionsNo. FunctionENBL Enables the LNA when inserted in the top position ENBV Enables the VGA when inserted in the top positionW5, W6 Connects the AD8331’s outputs to the SMA connectors Mode Bottom, gain increases with V GAIN; Top, gain decreases with V GAINHI_LO Top, HI gain; bottom, LO gain (shown in Hi gain position) BOARD LAYOUT AND PARTS LISTThe evaluation board circuitry uses four conductor layers. The two inner layers are grounded, and all interconnecting circuitry is located on the outer layers. Figure 5 to Figure 8 illustrate the copper patterns. Table 3 is a part’s list.AD8331-EVALRev. A | Page 2 of 404589-002NOTES1. COMPONENTS IN GREY ARE OPTIONAL AND USER SUPPLIED.VOHFigure 2. Schematic of Evaluation Board04589-0031103 TEKPROBE POWER SUPPLYDP8200 PRECISION VOLTAGE REFERENCE (FOR VGAIN)4395A ANALYZERGNDFigure 3. Typical Board Test ConnectionsAD8331-EVALRev. A | Page 3 of 404589-004Figure 4. Top Silkscreen04589-005Figure 5. Primary Side Copper04589-006Figure 6. Secondary Side Copper04589-007Figure 7. Internal Layer GroundFigure 8. Power PlaneAD8331-EVALRev. A | Page 4 of 4Table 3. Parts ListQty Name DescriptionReference Designation Mfg. Mfg. Part Number 5 Inductors Ferrite Bead, 120 nH, 0603 L1, L2, L3, L4, L5 Murata BLM18BA750SN1D 1 Resistor SM, 274 Ω, 1%, 1/10 W, 0603 RFB Panasonic ERJ-3EKF2740V 2 Resistors SM, 237 Ω, 1%, 1/10 W, 0603 R16, R20 Panasonic ERJ-3EKF2370V 2 Resistors SM, 100 Ω, 1%, 1/10 W, 0603 R43, R44 Panasonic ERJ-3EKF1 1 Capacitor 0.018 μF, 10%, X7R, 0603 CFBPanasonicECJ-1VB1E183K10Capacitor0.1 μF, 50 V, 0603 C6, C14, C16, C18, C24, C26, C32, C35, C INH , CLMD Kemet C0603C104K4RAC 1 Capacitor 1000 pF, 50 V, 0603 C34 Panasonic ECJ-1VB2A102K 1 Capacitor 10 μF, 10V Tantalum C3Nichicon F931A106MAA 6 Shunt ShuntHI_LO (HI), MODE (UP),ENBL (EN), ENBV (EN), W5, W6 W. M. Berg65474-0011 Capacitor 22 pF, 50 V, 0603CSH Panasonic ECJ-1VC1H220J 1 Transformer RF, 0.015 MHz to 300 MHz T1Mini-Circuit #T1-6T KK814 Bumper FootUsed as feet. Mount to wiring side of board at 4 corners 3M S J -67A11 1 Integrated Circuit Variable Gain Amplifier DUTAnalog Devices, Inc. AD8331ARQ 3 Connector 2-Pin Header VO, W5, W6W. M. Berg 69157-102 4 Connector 3-Pin HeaderENBL, ENBV, HI_LO, MODE Fixed Molex 22-11-2032 2 Connectors SMA, Right Angle PC Mount INH, VOH Amphenol 901-143-6RFX 1 Test Point Red Loop +5VBisco TP-104-01-02 5 Test Points Black Loop GND, GND 1, GND 2, GND 3, GND 4 Bisco TP-104-01-001Test PointsPurple LoopVCM FixedBisco TP-104-01-07ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.ORDERING GUIDEModel Description AD8331-EVAL Evaluation Board with AD8331ARQ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04589-0-4/06(A)。

引言当今现场总线技术的发展日新月异，应用领域也日趋广泛，从家庭、能源、楼宇，到工业现场。

为了适应市场的需要，国内外各大公司纷纷推出新一代的、各具特色的智能化流量仪表，其中结合现场总线技术的智能电磁流量计的开发尤为引人注目。

Profibus作为目前主流总线之一，包括三种类型：DP、PA和FMS。

这三种类型均使用统一的总线访问协议，其中P R 0 F I B U S-DP(decentralized pe riphery)采用经过优化的高速、廉价通信连接，专为自动控制系统和设备级的分散I／O之间通信设计，能满足分布式控制系统的实时性、稳定性和可靠性要求。

随着PROFIBUS-DP系统应用领域的日益扩大，用户及研究部门都有自主研发或特殊调试的需求，下面将介绍结合智能化技术与现场总线技术，开发带PROFIBUS-DP接口的智能电磁流量计。

1 系统总体设计常用现场仪表系统的处理任务简单，往往使用一个CPU加一系列外围辅助电路就能达到相应的目标功能。

采用双CPU可以根据系统的总体功能要求进行合理的分工，各自完成不同的控制和处理功能，可以适当地简化硬件电路和软件资源的分配，设计相对独立，程序的修改和移植也变得容易。

此系统采用了双CPU设计，如图1所示。

16位单片机MSP430F149是电磁流量计的核心部件，实现信号的采集处理、LCD显示、存储及与8位单片机PIC18F4520进行数据交换。

PIC18F4520和PROFIBUS现场总线专用协议芯片SPC3是PR OFIBUS-DP接口部分的核心部件。

PIC18F4520负责与MSP430F149交换数据及与SPC3通信等功能的实现，SPC3负责把主站送来的数据拆包，送往PIC18F4520，同时把PIC18F4520 送来的数据打包，上传给主站。

2 系统硬件设计如图1所示，电磁流量计的硬件部分主要由传感器、电源系统、信号处理电路、励磁电路、单片机系统和总线接口电路组成。

ad835乘法器电路AD835概述AD835是一款完整的四象限电压输出模拟乘法器，采用先进的介质隔离互补双极性工艺制造。

它产生X和Y电压输入的线性乘积，3dB 输出带宽为250 MHz（小信号上升时间为1 ns）。

满量程（1V至+1V 上升至下降时间为2.5ns（采用150 Ω的标准RL），同样条件下的0.1%建立时间典型值为20 ns。

AD835不仅具有出众的速度性能，而且易于使用，功能丰富。

例如，除允许在输出端添加信号之外，Z输入端还能使AD835的工作电压放大最高约10倍。

因此，该放大器的乘积噪声非常低（50 nV/Hz），远胜于早期产品。

AD835采用8引脚PDIP封装（N）和8引脚SOIC封装（R），额定温度范围为40℃至+85℃工业温度范围。

AD835产品特点和性能优势简单：基本函数为W=XY+Z完整：只需极少的外部元件直流耦合电压输出简化应用高速：满量程的0.1%建立时间仅20ns高差分输入阻抗X、Y和Z输入低乘法器噪声50nV/vHzAD835性能参数与特点AD835是AnalogDevices公司生产的电压输出四象限乘法器电路，能够完成W=XY+Z功能，X和Y输入信号范围为-1～+1V，带宽为250MHz，在20ns内可稳定到满刻度的=±．1％，乘法器噪声为50nV／，差分乘法器输入X和Y、求和输入Z具有高的输入阻抗，输出引脚端W具有低、的输出阻抗，输出电压范围为-2．5～+2．5V，可驱动负载电阻为25Ω。

其电源电压为±5V，电流消耗为25mA；工作温度范围为-40～+85℃。

AD835的引脚功能与封装形式AD835采用PDIP一8或者SOIC一8封装。

引脚端X1和X2、Y1和Y2为差分放大器的正、负输入端，Z为求和输入端，W为乘法器输出端，VP和VN为电源电压正端和负端。

ad835乘法器电路由AD835构成的乘法器电路如图4．1．1所示。

比例系数U可以利用在引脚端W和Z之间的电阻分压器进行调节。

ad835乘法器电路
AD835是一款高速乘法器电路，由Analog Devices公司生产。

它被设计用于高速信号处理应用，如电信、雷达和图像处理等领域。

AD835采用了一个双极性延迟差分放大器作为主要的乘法功
能单元。

该放大器采用了高度优化的架构，以实现极低的失配和高的线性度。

AD835的输入和输出电平可以接受0.8V至3.8V的范围，其带宽为600MHz。

它具有低的功耗特性，只需25mA的工作电流。

AD835乘法器电路的输入端包括一个正输入端IN+和一个负
输入端IN-，输出端为OUT。

它可以实现精确的乘法运算，将输入信号与一个增益系数相乘，并输出结果。

AD835的主要特点包括：
1. 高速性能：具有600MHz的带宽，适用于高速信号处理。

2. 低功耗：工作电流只需25mA。

3. 高线性度：采用了高度优化的差分放大器架构，实现高线性度和低失配。

4. 宽电压范围：输入和输出电平可以接受0.8V至3.8V的范围。

5. 高精度：能够实现精确的乘法运算。

6. 双极性输出：输出信号可以具有正负两种极性。

AD835乘法器电路可以用于各种应用，如频率合成器、滤波
器、功率测量等。

它能够快速准确地进行乘法运算，提高信号处理的速度和精度。

华中科技大学信号与控制综合实验报告专业：电气工程及其自动化班级：电气0612班日期：2008/10/7实验组别：第一组第一次实验指导老师：
学生姓名：王璠学号： 012006019801 分数：
图1.正弦波幅度调制与解调
图35的基本连接
为信号输入端，为信号输出端，W 和Z 之间的电阻网络起微调电2.AD8W
图4.低通滤波器的频率响应
四、实验步骤及波形记录
调节函数信号发生器，输出频率为500Hz，幅值为1V的正弦波，作为调制信号，接至实验电路的调制信号输入端；运行AD9851驱动程序，使之输出频率为的正弦波，作为载波信号，
接至实验电路的载波信号输入端（两路）
3.电路后级输出有比较大的直流分量。

最初确定的实验方案中，信号输入部分和各级之调节反馈电阻或输出端串电阻等方式使电路达到最佳性能。

AD835内部的基本电路单元也datasheet 中没有给出其带容性负载定合适电容值的方法，在两级AD835之间尝试了104，334，106，2200u 等电容值，发现第直接耦合方式，导致后级有较大的直流分量输出。

此问题有待进一步研究。

间均有设计有隔直电容。

但实际调试时发现高速运放带容性负载时性能比较特殊，需要通过是高速运放，但的特性，由于经验不足，找不到一个确二级AD835的输入端均被拉低，随容值的增大，被拉低的电平有减小趋势。

最终电路采用
附录
附图1.调制与解调电路原理图
附图2.AD9851原理图
附图3.调制与解调电路
附图4.AD9851号产生电路
信。

ad835乘法器乘法公式AD835乘法器乘法公式1. 什么是AD835乘法器AD835是一款高性能低失真的模拟乘法器芯片，由安捷伦科技公司研发生产。

它通过使用模拟法实现了精确的信号乘法运算，广泛应用于各种电子设备和仪器中。

2. AD835乘法器乘法公式AD835乘法器的乘法运算公式可以表示为：Vout = Vin1 * Vin2其中，Vout表示输出电压，Vin1和Vin2分别表示输入电压。

3. 公式说明和举例解释•输入电压Vin1和Vin2可以是直流电压或交流电压，其幅值范围取决于AD835乘法器的工作电压和规格。

•输出电压Vout是输入电压的乘积，即乘法器对输入信号进行数学乘法运算后得到的结果。

•举例说明：假设Vin1 = 2V，Vin2 = 3V，根据AD835乘法器的乘法公式，可以计算得到输出电压Vout = 2V *3V = 6V。

•AD835乘法器的优点是具有高精度、低失真和宽工作电压范围等特点，可用于模拟信号处理、功率放大器校正、电路调节等应用场景。

•需要注意的是，AD835乘法器的输入电压限制和输出电流限制等参数需要根据具体的应用需求进行选择和设置，以确保乘法器的正常工作和性能表现。

4. 总结AD835乘法器是一款高性能的模拟乘法器芯片，具有广泛的应用场景。

通过乘法器的乘法公式，可以实现输入电压的精确乘法运算，得到相应的输出电压。

该乘法器在模拟信号处理、功率放大器校正等领域具有重要作用，并且具备高精度、低失真等优点。

在应用过程中，需要根据具体需求设置乘法器的输入电压范围和输出电流限制等参数，以确保其良好的工作和性能表现。

5. 其他相关公式除了AD835乘法器的乘法运算公式外，还存在其他与乘法运算相关的公式，例如：乘法的交换律乘法运算具有交换律，即数值相乘的顺序可以改变，得到的结果是相同的。

例如，对于任意实数a和b，有：a *b = b * a举例说明：假设a=2，b=3，则有2 * 3 = 3 * 2 = 6。

ZC829, ZDC833, ZMV829, ZMDC830, ZV831 Series Device DescriptionA range of silicon varactor diodes for use in frequency control and filtering.Featuring closely controlled CV characteristics and high Q.Low reverse current ensures very low phase noise performance.Available in single or dual common cathode format in a wide rage of miniature surface mount packages.Features·Close tolerance C-V characteristics ·High tuning ratio ·Low I R (typically 200pA)·Excellent phase noise performance ·High Q·Range of miniature surface mount packagesApplications·VCXO and TCXO·Wireless communications ·Pagers ·Mobile radio*Where steeper CV slopes are required there is the 12V hyperabrupt range.ZC930, ZMV930, ZV930, ZV931 Series 830 seriesISSUE 6 - JANUARY 20021SILICON 28V HYPERABRUPT VARACTOR DIODES830 seriesISSUE 6 - JANUARY 20022PARTCapacitance (pF)V R =2V,f=1MHzMin Q V R =3V f=50MHzCapacitance RatioC 2/C 20at f=1MHzMIN.NOM.MAX.MIN.MAX.829A 7.388.29.02250 4.3 5.8829B 7.798.28.61250 4.3 5.8830A 9.010.011.0300 4.5 6.0830B 9.510.010.5300 4.5 6.0831A 13.515.016.5300 4.5 6.0831B 14.2515.015.75300 4.5 6.0832A 19.822.024.2200 5.0 6.5832B 20.922.023.1200 5.0 6.5833A 29.733.036.3200 5.0 6.5833B 31.3533.034.65200 5.0 6.5834A 42.347.051.7200 5.0 6.5834B 44.6547.049.35200 5.0 6.5835A 61.268.074.8100 5.0 6.5835B 64.668.071.4100 5.0 6.5836A 90.0100.0110.0100 5.0 6.5836B95.0100.0105.0100 5.06.5TUNING CHARACTERISTICS at Tamb = 25°CPARAMETER SYMBOLMAX UNIT Forward currentI F 200mA Power dissipation at T amb =25ЊC SOT23P tot 330mW Power dissipation at T amb =25ЊC SOD323P tot 330mW Power dissipation at T amb =25ЊC SOD523P tot250mW Operating and storage temperature range-55to +150ЊCABSOLUTE MAXIMUM RATINGSPARAMETERCONDITIONS MIN.TYP.MAX.UNIT Reverse breakdown voltage I R =10uA 25V Reverse voltage leakageV R =20V 0.220nA Temperature coefficient of capacitanceV R =3V,f =1MHz300400ppCm/ЊCELECTRICAL CHARACTERISTICS at Tamb = 25°C830 seriesTYPICAL CHARACTERISTICSISSUE 6 - JANUARY 20023830 seriesISSUE 6 - JANUARY 20024O R D E R C O D E S A N D P A R T M A R K I N GR E E L C O D ER E E L S I Z ET A P E W I D T HQ U A N T I T Y P E R R E E LT A7i n c h (180m m )8m m3000T C13i n c h (330m m )8m m 10000T A P E A N D R E E L I N F O R M A T I O NT h e o r d e r c o d e s a r e s h o w n a s T A w h i c h i s f o r 7i n c h r e e l s .F o r 13i n c h r e e l s s u b s t i t u t e T C i n p l a c e o f T A i n t h e o r d e r c o d e .ISSUE 6 - JANUARY 20025830 seriesSOT23 PACKAGE DIMENSIONSSOD323 PACKAGE DIMENSIONSZetex plcFields New Road ChaddertonOldham, OL9 8NP United KingdomTelephone (44) 161 622 4422Fax: (44) 161 622 4420Zetex GmbHStreitfeldstraße 19D-81673 München GermanyTelefon: (49) 89 45 49 49 0Fax: (49) 89 45 49 49 49Zetex Inc700 Veterans Memorial Hwy Hauppauge, NY11788USATelephone: (631) 360 2222Fax: (631) 360 8222Zetex (Asia) Ltd3701-04Metroplaza, Tower 1Hing Fong Road Kwai Fong Hong KongTelephone: (852) 26100 611Fax: (852) 24250 494These offices are supported by agents and distributors in major countries world-wide.This publication is issued to provide outline information only which (unless agreed by the Company in writing)may not be used,applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned.The Company reserves the right to alter without notice the specification,design,price or conditions of supply of any product or service.For the latest product information,log on to©Zetex plc 2001830 series6ISSUE 6 - JANUARY 2002DIM MILLIMETRES MIN.MAX A ᎏ0.800A10.0000.100A20.6000.800b10.1600.300c 0.0800.220D 0.7000.900E 1.500 1.700E1 1.100 1.300L 0.2000.400L10.1700.230⍜1Њ4Њ10ЊSOD523 PACKAGE DIMENSIONSSOD323 PACKAGE DIMENSIONS。

REV.0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise unde r any pate nt or pate nt rights of Analog De vice s. Trade marks and re giste re d trade marks are the prope rty of the ir re spe ctive companie s.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© 2002 Analog Devices, Inc. All rights reserved.EVAL-AD8304EBAD8304 Evaluation BoardBOARD DESCRIPTIONThe AD8304 evaluation board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. The schematic for the AD8304 evaluation board is shown in Figure 1, and the two board sides are shown in Figures 2 and 3.It can be configured for a wide variety of experiments. The board is factory set for Photoconductive Mode with a buffer gain of unity, providing a slope of 10mV/dB and an intercept of 100 pA.By substituting resistor and capacitor values, all of the application circuits presented in this data sheet can be evaluated. Table I describes the various configuration options.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the EVAL-AD8304EB features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.ORDERING GUIDEModelPackage DescriptionAD8304-EVALEvaluation BoardOPENFigure 1.Evaluation Board SchematicREV.0C 03288–0–11/02(0)P R I N T E D I N U .S .A .–2–EVAL-AD8304EBTable I.Evaluation Board Configuration OptionsComponent FunctionDefault Condition V P , V N , AGND Positive and Negative Supply and Ground PinsNot ApplicableSW1, R10Device Enable. When SW1 is in the “0” position, the PWDN pin is SW1 = Installedconnected to ground and the AD8304 is in its normal operating mode.R10 = 10 k W (Size 0603)R1, R2Buffer Amplifier Gain/Slope Adjustment. The logarithmic slopeR1 = Open (Size 0603)of the AD8304 can be altered using the buffer’s gain-setting resistors,R2 = 0 W (Size 0603)R1 and R2.R3, R4Intercept Adjustment. A dc offset can be applied to the input term-R3 = Open (Size 0603)inals of the buffer amplifier to adjust the effective logarithmic intercept.R4 = Open (Size 0603)R5, R6, R7, R8, R9Bias Adjustment. The voltage on the VSUM and INPT pins can beR5 = R6 = Open (Size 0603)altered using appropriate resistor values. R9 is populated with a decoup-R7 = R8 = Open (Size 0603)ling capacitor to reduce noise pickup. The decoupling capacitor can be R9 = 0.1 m F (Size 0603)removed when a fixed bias is applied to VSUM.C1, C2, C3, C4, C9Supply Decoupling CapacitorsC1 = C4 = 0.1 m F (Size 0603)C2 = C3 = 1 nF (Size 0603)C9 = 10 nF (Size 0603)C10Photodiode Biaser Decoupling. Provides high frequency decoupling C10 = 0.1 m F (Size 0603)of the adaptive bias output at Pin VPDB.C5, C6, C7, C8, R11,Output Filtering. Allows implementation of a variety of filter config-R11 = R13 = 0 W (Size 0603)R12, R13, R14urations, from simple RC low-pass filters to three-pole Sallen and Key.R12 = Open (Size 0603)C7 = C8 = Open (Size 0603)R15, C11Input Filtering. Provides essential HF compensation at the inputR15 = 750 W (Size 0603)Pin INPT.C11 = 1 nF (Size 0603)LK1, LK2Guard/Shield Options. The shells of the SMA connectors usedLK1 = Installed for the input and the photodiode bias can be set to the voltage on the LK2 = OpenVSUM pin or connected to ground.Figure 2.Component Side Layout Figure ponent Side SilkscreenR14 = 0 W (Size 0603)C5 = C6 = Open (Size 0603)。

本店出售250M AD835乘法器模块，该板子布局布线紧凑有效，板子采用磁珠，陶瓷电容进行电源管脚去耦。

出色地抑制了电源的高频噪声，提高了芯片的PSRR。

并此类
板非常适合电子设计竞赛以及一些高速信号调理项目使用，能有效加速用户开发进程，性价比非常高。

AD835模块特点和参数
1、工作频率250M@-3dB
2、低噪声，出色的幅度和相位精度
3、公式W=XY+Z
4、工作电压典型+-5V，
5、接口介绍：
J1: Z端OFFESET调整电压输入,
默认接地。

J2:Y 端CARRIER IN 载波输入
J4:X 端MOD IN 调制信号输入
J3:W端OUTPUT 信号输出
6、2个输入端口留有相应的分压电阻，可实现交流耦合，分压等模式，扩展默
认输入+-1V最大输入限制。

输出端口也同样可配置成分压，交流耦合等模式。

7、提供模块PDF原理图
8、所有模块都严格测试后发货
9、静电袋包装后发货
10、提供售后技术支持。

0.1 GHz to 2.5 GHz 70 dB Logarithmic Detector/ControllerAD8313Rev. DInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESWide bandwidth: 0.1 GHz to 2.5 GHz min High dynamic range: 70 dB to ±3.0 dBHigh accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz) Fast response: 40 ns full-scale typical Controller mode with error outputScaling stable over supply and temperature Wide supply range: 2.7 V to 5.5 V Low power: 40 mW at 3 VPower-down feature: 60 mW at 3 V Complete and easy to useAPPLICATIONSRF transmitter power amplifier setpoint control and level monitoringLogarithmic amplifier for RSSI measurement cellular base stations, radio link, radarFUNCTIONAL BLOCK DIAGRAM01085-C -001Figure 1.GENERAL DESCRIPTIONThe AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its differ-ential input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz and is useful over the range of 10 MHz to 3.5 GHz. The nominal input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be increased by 6 dB or more with a narrow-band input impedance matching network or a balun. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 Vsupply, its 13.7 mA consumption (for T A = 25°C) is only 41 mW . A power-down feature is provided; the input is taken high to initiate a low current (20 µA) sleep mode, with a threshold at half the supply voltage.The AD8313 uses a cascade of eight amplifier/limiter cells, each having a nominal gain of 8 dB and a −3 dB bandwidth of3.5 GHz. This produces a total midband gain of 64 dB. At each amplifier output, a detector (rectifier) cell is used to convert the RF signal to baseband form; a ninth detector cell is placed directly at the input of the AD8313. The current-mode outputs of these cells are summed to generate a piecewise linear approxi-mation to the logarithmic function. They are converted to a low impedance voltage-mode output by a transresistance stage, which also acts as a low-pass filter.When used as a log amplifier, scaling is determined by a separate feedback interface (a transconductance stage) that sets the slope to approximately 18 mV/dB; used as a controller, this stageaccepts the setpoint input. The logarithmic intercept is positioned to nearly −100 dBm, and the output runs from about 0.45 V dc at −73 dBm input to 1.75 V dc at 0 dBm input. The scale and intercept are supply- and temperature-stable.The AD8313 is fabricated on Analog Devices’ advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is −40°C to +85°C. An evaluation board is available.INPUT AMPLITUDE (dBm)2.0–80O U T P U T V O L T A G E (V D C )1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–104O U T P U T E R R O R (d B )01085-C -002Figure 2. Typical Logarithmic Response and Error vs. Input AmplitudeAD8313Rev. D | Page 2 of 24TABLE OF CONTENTSSpecifications.....................................................................................3 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configurations and Function Description.............................7 Typical Performance Characteristics.............................................8 Circuit Description.........................................................................11 Interfaces..........................................................................................13 Power-Down Interface, PWDN................................................13 Signal Inputs, INHI, INLO........................................................13 Logarithmic/Error Output, VOUT..........................................13 Setpoint Interface, VSET............................................................14 Applications.....................................................................................15 Basic Connections for Log (RSSI) Mode.................................15 Operating in Controller Mode.................................................15 Input Coupling...........................................................................16 Narrow-Band LC Matching Example at 100 MHz................16 Adjusting the Log Slope.............................................................18 Increasing Output Current........................................................19 Effect of Waveform Type on Intercept.....................................19 Evaluation Board............................................................................20 Schematic and Layout................................................................20 General Operation.....................................................................20 Using the AD8009 Operational Amplifier..............................20 Varying the Logarithmic Slope.................................................20 Operating in Controller Mode.................................................20 RF Burst Response.....................................................................20 Outline Dimensions.......................................................................24 Ordering Guide.. (24)REVISION HISTORY6/04—Data Sheet Changed from Rev. C to Rev. DUpdated Evaluation Board Section..............................................21 2/03—Data Sheet changed from Rev. B to Rev. CTPCs and Figures Renumbered........................................Universal Edits to SPECIFICATIONS.............................................................2 Updated ESD CAUTION................................................................4 Updated OUTLINE DIMENSIONS..............................................7 8/99—Data Sheet changed from Rev. A to Rev. B 5/99—Data Sheet changed from Rev. 0 to Rev. A 8/98—Revision 0: Initial VersionAD8313Rev. D | Page 3 of 24SPECIFICATIONST A = 25°C, V S = 5 V 1, R L 10 kΩ, unless otherwise noted.Table 1.Parameter Conditions M in 2Typ M ax 2Unit SIGNAL INPUT INTERFACE Specified Frequency Range 0.1 2.5 GHz DC Common-Mode Voltage V POS – 0.75 V Input Bias Currents 10 µAInput Impedance f RF < 100 MHz 3900||1.1 Ω||pF 4LOG (RSSI) MODE Sinusoidal, input termination configurationshown in Figure 29100 MHz 5Nominal conditions ±3 dB Dynamic Range 6 53.5 65 dB Range Center −31.5 dBm ±1 dB Dynamic Range 56 dB Slope 17 19 21 mV/dB Intercept −96 −88 −80 dBm 2.7 V ≤ V S ≤ 5.5 V, −40°C ≤ T ≤ +85°C±3 dB Dynamic Range 51 64 dB Range Center −31 dBm ±1 dB Dynamic Range 55 dB Slope 16 19 22 mV/dB Intercept −99 −89 −75 dBm Temperature Sensitivity P IN = −10 dBm −0.022 dB/°C 900 MHz 5 Nominal conditions ±3 dB Dynamic Range 60 69 dB Range Center −32.5 dBm ±1 dB Dynamic Range 62 dB Slope 15.5 18 20.5 mV/dB Intercept −105 −93 −81 dBm 2.7 V ≤ V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C±3 dB Dynamic Range 55.5 68.5 dB Range Center –32.75 dBm ±1 dB Dynamic Range 61 dB Slope 15 18 21 mV/dB Intercept –110 –95 –80 dBm Temperature Sensitivity P IN = –10 dBm –0.019 dB/°C1.9 GHz 7Nominal conditions ±3 dB Dynamic Range 52 73 dB Range Center –36.5 dBm ±1 dB Dynamic Range 62 dB Slope 15 17.5 20.5 mV/dB Intercept –115 –100 –85 dBm 2.7 V ≤ V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C±3 dB Dynamic Range 50 73 dB Range Center –36.5 dBm ±1 dB Dynamic Range 60 dB Slope 14 17.5 21.5 mV/dB Intercept –125 –101 –78 dBm Temperature Sensitivity P IN = –10 dBm –0.019 dB/°CAD8313Rev. D | Page 4 of 24Parameter Conditions M in 2Typ M ax 2Unit2.5 GHz 7Nominal conditions ±3 dB Dynamic Range 48 66 dB Range Center –34 dBm ±1 dB Dynamic Range 46 dB Slope 16 20 25 mV/dB Intercept –111 –92 –72 dBm 2.7 V ≤ V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C±3 dB Dynamic Range 47 68 dB Range Center –34.5 dBm ±1 dB Dynamic Range 46 dB Slope 14.5 20 25 mV/dB Intercept –128 –92 –56 dBm Temperature Sensitivity P IN =–10 dBm –0.040 dB/°C 3.5 GHz 5Nominal conditions ±3 dB Dynamic Range 43 dB ±1 dB Dynamic Range 35 dBSlope 24 mV/dB Intercept –65 dBm CONTROL MODE Controller Sensitivity f = 900 MHz 23 V/dBLow Frequency Gain VSET to VOUT 884 dB Open-Loop Corner Frequency VSET to VOUT 8 700 Hz Open-Loop Slew Rate f = 900 MHz 2.5 V/µs VSET Delay Time 150 ns VOUT INTERFACE Current Drive Capability Source Current 400 µA Sink Current 10 mA Minimum Output Voltage Open-loop 50 mV Maximum Output Voltage Open-loop V POS – 0.1 V Output Noise Spectral Density P IN = –60 dBm, f SPOT = 100 Hz 2.0 µV/√Hz P IN = –60 dBm, f SPOT = 10 MHz 1.3 µV/√Hz Small Signal Response Time P IN = –60 dBm to –57 dBm, 10% to 90% 40 60 ns Large Signal Response Time P IN = No signal to 0 dBm; settled to 0.5 dB 110 160 ns VSET INTERFACE Input Voltage Range 0 V POS V Input Impedance 18||1 kΩ||pF POWER-DOWN INTERFACE PWDN Threshold V POS /2 V Power-Up Response Time Time delay following high to low transitionuntil device meets full specifications.1.8 µs PWDN Input Bias Current PWDN = 0 V 5 µA PWDN = V S <1 µA POWER SUPPLY Operating Range2.7 5.5 V Powered-Up Current 13.7 15.5 mA4.5 V ≤V S ≤5.5 V, –40°C ≤ T ≤ +85°C 18.5 mA 2.7 V ≤V S ≤ 3.3 V, –40°C ≤ T ≤ +85°C 18.5 mA Powered-Down Current 4.5 V ≤V S ≤ 5.5 V, –40°C ≤ T ≤ +85°C 50 150 µA 2.7 V ≤V S ≤ 3.3 V, –40°C ≤ T ≤ +85°C 20 50 µAAD83131 Except where otherwise noted; performance at V S = 3 V is equivalent to 5 V operation.2 Minimum and maximum specified limits on parameters that are guaranteed but not tested are 6 sigma values.3 Input impedance shown over frequency range in Figure 26.4 Double vertical bars (||) denote “in parallel with.”5 Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.6 Dynamic range refers to range over which the linearity error remains within the stated bound.7 Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.8 AC response shown in Figure 12.Rev. D | Page 5 of 24AD8313Rev. D | Page 6 of 24ABSOLUTE MAXIMUM RATINGSTable 2.Supply Voltage V S 5.5 V VOUT, VSET, PWDN0 V, VPOS Input Power Differential (re: 50 Ω, 5.5 V) 25 dBm Input Power Single-Ended (re: 50 Ω, 5.5 V) 19 dBm Internal Power Dissipation 200 mW θJA200°C/W Maximum Junction Temperature 125°COperating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.AD8313Rev. D | Page 7 of 24PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONVPOSINHI INLO VPOS 01085-C -003Figure 3. Pin ConfigurationTable 3. Pin Function DescriptionsPin No. Mnemonic Description1, 4 VPOS Positive Supply Voltage (VPOS), 2.7 V to 5.5 V.2 INHI Noninverting Input. This input should be ac-coupled.3 INLO Inverting Input. This input should be ac-coupled.5 PWDN Connect Pin to Ground for Normal Operating Mode. Connect this pin to the supply for power-down mode.6 COMM Device Common.7 VSET Setpoint Input for Operation in Controller Mode. To operate in RSSI mode, short VSET and VOUT. 8VOUTLogarithmic/Error Output.AD8313Rev. D | Page 8 of 24TYPICAL PERFORMANCE CHARACTERISTICST A = 25°C, V S = 5 V , R L input match shown in Figure 29, unless otherwise noted.INPUT AMPLITUDE (dBm)2.0V O U T (V )1.81.61.41.21.00.80.60.40.2001085-C -004Figure 4. V OUT vs. Input AmplitudeINPUT AMPLITUDE (dBm)6–6–7010–60E R R O R (d B )–50–40–30–20–1042–2–401085-C -005Figure 5. Log Conformance vs. Input AmplitudeINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–1010543210–1–2–3–4–5E R R O R (d B )01085-C -006Figure 6. V OUT and Log Conformance vs. Input Amplitude at 100 MHz forMultiple TemperaturesINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5E R R O R (d B )01-85-C -007Figure 7. V OUT and Log Conformance vs. Input Amplitude at 900 MHz forMultiple TemperaturesINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010E R R O R (d B )01085-C -008Figure 8. V OUT and Log Conformance vs. Input Amplitude at 1.9 GHz forMultiple TemperaturesINPUT AMPLITUDE (dBm)2.0–70V O U T (V )1.81.61.41.21.00.80.60.40.20–60–50–40–30–20–10010543210–1–2–3–4–5E R R O R (d B )01085-C -009Figure 9. V OUT and Log Conformance vs. Input Amplitude at 2.5 GHz forMultiple TemperaturesAD8313Rev. D | Page 9 of 24FREQUENCY (MHz)22211602500500S L O P E (m V /d B )1000150020002019181701085-C -010Figure 10. V OUT Slope vs. Frequency for Multiple TemperaturesSUPPLY VOLTAGE (V)242.5S L O P E (m V /d B )23222120191817161514 3.03.54.0 4.55.0 5.56.001085-C -011Figure 11. V OUT Slope vs. Supply VoltageFREQUENCY (Hz)01085-C -012Figure 12. AC Response from V SET to V OUT FREQUENCY (MHz)–110I N T E R C E P T (d B m )–70–80–90–10001085-C -013Figure 13. V OUT Intercept vs. Frequency for Multiple TemperaturesSUPPLY VOLTAGE (V)I N T E R C E P T (d B m )01085-C -014Figure 14. V OUT Intercept vs. Supply VoltageFREQUENCY (Hz)1000.1µV / H z11k10k 100k 1M 10M01085-C -015Figure 15. V OUT Noise Spectral DensityAD8313Rev. D | Page 10 of 24PWDN VOLTAGE (V)100.00S U P P L Y C U R R E N T (m A )10.001.000.100.0101085-C -016Figure 16. Typical Supply Current vs. PWDN VoltageCH. 1 GNDCH. 2 GNDCH. 3 GND01085-C -017Figure 17. PWDN Response Time 01085-C -019Figure 18. Response Time, No Signal to –45 dBmCH. 2 GND01085-C -020Figure 19. Response Time, No Signal to 0 dBm________________________________________________________________________________________________________________________________01085-C -018Figure 20. Test Setup for PWDN Response Time01085-C -021Figure 21. Test Setup for RSSI Mode Pulse ResponseCIRCUIT DESCRIPTIONThe AD8313 is an 8-stage logarithmic amplifier, specifically designed for use in RF measurement and power amplifier control applications at frequencies up to 2.5 GHz. A block diagram is shown in Figure 22. For a detailed description of log amp theory and design principles, refer to the AD8307 data sheet.VOUTVSETCOMMPWDN01085-C -001Figure 22. Block DiagramA fully differential design is used. Inputs INHI and INLO (Pins 2 and 3) are internally biased to approximately 0.75 V below the supply voltage, and present a low frequency impedance of nominally 900 Ω in parallel with 1.1 pF. The noise spectral density referred to the input is 0.6 nV/√Hz, equivalent to avoltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of −76 dBm re: 50 Ω. This sets the lower limit to the dynamic range; the Applications section shows how to increase the sensitivity by using a matching network or input transformer. However, the low end accuracy of the AD8313 is enhanced by specially shaping the demodulation transfer characteristic to partially compensate for errors due to internal noise.Each of the eight cascaded stages has a nominal voltage gain of 8 dB and a bandwidth of 3.5 GHz. Each stage is supported by precision biasing cells that determine this gain and stabilize it against supply and temperature variations. Since these stages are direct-coupled and the dc gain is high, an offset compensation loop is included. The first four stages and the biasing system are powered from Pin 4, while the later stages and the output inter-faces are powered from Pin 1. The biasing is controlled by a logic interface PWDN (Pin 5); this is grounded for normal operation, but may be taken high (to V S ) to disable the chip. The threshold is at V POS /2 and the biasing functions are enabled and disabled within 1.8 µs.Each amplifier stage has a detector cell associated with its output. These nonlinear cells perform an absolute value (full-wave rectification) function on the differential voltages along this backbone in a transconductance fashion; their outputs are in current-mode form and are thus easily summed. A ninth detector cell is added at the input of the AD8313. Since the midrange response of each of these nine detector stages isseparated by 8 dB, the overall dynamic range is about 72 dB (Figure 23). The upper end of this range is determined by the capacity of the first detector cell, and occurs at approximately 0 dBm. The practical dynamic range is over 70 dB to the ±3 dB error points. However, some erosion of this range can occur at temperature and frequency extremes. Useful operation to over 3 GHz is possible, and the AD8313 remains serviceable at 10 MHz, needing only a small amount of additional ripple filtering.INPUT AMPLITUDE (dBm)2.0–80V O U T (V )1.81.61.41.21.00.80.60.40.20–70–60–50–40–30–20–10543210–1–2–3–4–5E R R O R (d B )–9001085-c -023Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHzThe fluctuating current output generated by the detector cells, with a fundamental component at twice the signal frequency, is filtered first by a low-pass section inside each cell, and then by the output stage. The output stage converts these currents to a voltage, V OUT , at VOUT (Pin 8), which can swing rail-to-rail. The filter exhibits a 2-pole response with a corner at approximately 12 MHz and full-scale rise time (10% to 90%) of 40 ns. The residual output ripple at an input frequency of 100 MHz has an amplitude of under 1 mV . The output can drive a small resistive load; it can source currents of up to 400 µA, and sink up to 10 mA. The output is stable with any capacitive load, though settling time could be impaired. The low frequency incremental output impedance is approximately 0.2 Ω.In addition to its use as an RF power measurement device (that is, as a logarithmic amplifier), the AD8313 may also be used in controller applications by breaking the feedback path from VOUT to VSET (Pin 7), which determines the slope of the output (nominally 18 mV/dB). This pin becomes the setpoint input in controller modes. In this mode, the voltage V OUT remains close to ground (typically under 50 mV) until the decibel equivalent of the voltage V SET is reached at the input, when V OUT makes a rapid transition to a voltage close to V POS (see the Operating in Controller Mode section). The logarithmic intercept is nominally positioned at −100 dBm (re: 50 Ω); this is effective in both the log amp mode and the controller mode.With Pins 7 and 8 connected (log amp mode), the output can be stated as)dBm 100(+=IN SLOPE OUT P V Vwhere P IN is the input power stated in dBm when the source is directly terminated in 50 Ω. However, the input impedance of the AD8313 is much higher than 50 Ω, and the sensitivity of this device may be increased by about 12 dB by using some type of matching network (see below), which adds a voltage gain and lowers the intercept by the same amount. Dependence on the ref-erence impedance can be avoided by restating the expression as)V 2.2/(log 20µ×××=IN SLOPE OUT V V Vwhere V IN is the rms value of a sinusoidal input appearing across Pins 2 and 3; here, 2.2 µV corresponds to the intercept, expressed in voltage terms. For detailed information on the effect of signal waveform and metrics on the intercept positioning for a log amp, refer to the AD8307 data sheet. With Pins 7 and 8 disconnected (controller mode), the output can be stated asSET IN SLOPE S OUT V P V V V >→)100/(log when SET IN SLOPE OUT V P V V <→)100/(log when 0when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 Ω. The transition zone between high and low states is very narrow since the output stage behaves essentially as a fast integrator. The above equations can be restated asSET IN SLOPE S OUT V V V V V >µ→)V 2.2/(log when SET IN SLOPE OUT V V V V <µ→)V 2.2/(log when 0Another use of the separate VOUT and VSET pins is in raising the load-driving current capability by including an external NPN emitter follower. More complete information about usage in these modes is provided in the Applications section.INTERFACESThis section describes the signal and control interfaces and their behavior. On-chip resistances and capacitances exhibit variations of up to ±20%. These resistances are sometimes temperature-dependent, and the capacitances may be voltage-dependent.POWER-DOWN INTERFACE, PWDNThe power-down threshold is accurately centered at the midpoint of the supply as shown in Figure 24. If Pin 5 is left unconnected or tied to the supply voltage (recommended), the bias enable current is shut off, and the current drawn from the supply is predominately through a nominal 300 kΩ chain (20 µA at 3 V). When grounded, the bias system is turned on. The threshold level is accurately at V POS /2. When operating in the device ON state, the input bias current at the PWDN pin is approximately 5 µA for V POS = 3 V .PWDN VPOS COMM 01085-C -024Figure 24. Power-Down Threshold CircuitrySIGNAL INPUTS, INHI, INLOThe simplest low frequency ac model for this interface consists of just a 900 Ω resistance, R IN , in shunt with a 1.1 pF input cap-acitance, C IN , connected across INHI and INLO. Figure 25 shows these distributed in the context of a more complete schematic. The input bias voltage shown is for the enabled chip; when disabled, it rises by a few hundred millivolts. If the input is coupled via capacitors, this change may cause a low level signal transient to be introduced, having a time constant formed by these capacitors and R IN . For this reason, large coupling capacitors should be well matched. This is not necessary when using the small capacitors found in many impedance transforming networks used at high frequencies.COMMVPOS INHI INLO VPOS01085-C -025Figure 25. Input Interface Simplified SchematicFor high frequency use, Figure 26 shows the input impedance plotted on a Smith chart. This measured result of a typical device includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground from the INLO pin.1.1pF01085-C -026Figure 26. Typical Input ImpedanceLOGARITHMIC/ERROR OUTPUT, VOUTThe rail-to-rail output interface is shown in Figure 27. V OUT can run from within about 50 mV of ground, to within about 100 mV of the supply voltage, and is short-circuit safe to either supply. However, the sourcing load current, I SOURCE , is limited to that which is provided by the PNP transistor, typically 400 µA.Larger load currents can be provided by adding an external NPN transistor (see the Applications section). The dc open-loop gain of this amplifier is high, and it may be regarded as an integrator having a capacitance of 2 pF (C INT ) driven by the current-mode signal generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 µA/dB.LFROM SETPOINT SUMMED DETECTOR OUTPUTS01085-C -027Figure 27. Output Interface CircuitryThus, for midscale RF input of about 3 mV , which is some 40 dB above the minimum detector output, this current is 160 µA, and the output changes by 8 V/µs. When VOUT is connected to VSET, the rise and fall times are approximately 40 ns (for R L ≥ 10 kΩ ). The nominal slew rate is 2.5 V/µs. The HF compensation tech-nique results in stable operation with a large capacitive load, C L , though the positive-going slew rate is then limited by I SOURCE /C L to 1 V/µs for C L = 400 pF.SETPOINT INTERFACE, VSETThe setpoint interface is shown in Figure 28. The voltage, V SET, is divided by a factor of 3 in a resistive attenuator of 18 kΩ total resistance. The signal is converted to a current by the action of the op amp and the resistor R3 (1.5 kΩ), which balances the current generated by the summed output of the nine detector cells at the input to the previous cell. The logarithmic slope is nominally 3 µs × 4.0 µA/dB × 1.5 kΩ = 18 mV/dB.VSETVPOSCOMM185-C-28 Figure 28. Setpoint Interface CircuitryAPPLICATIONSBASIC CONNECTIONS FOR LOG (RSSI) MODE Figure 29 shows the AD8313 connected in its basic measurement mode. A power supply between 2.7 V and 5.5 V is required. The power supply to each of the VPOS pins should be decoupled with a 0.1 µF surface-mount ceramic capacitor and a 10 Ω series resistor.The PWDN pin is shown as grounded. The AD8313 may be disabled by a logic high at this pin. When disabled, the chip current is reduced to about 20 µA from its normal value of 13.7 mA. The logic threshold is at V POS/2, and the enable function occurs in about 1.8 µs. However, that additional settling time is generally needed at low input levels. While the input in this case is terminated with a simple 50 Ω broadband resistive match, there are many ways in which the input termi-nation can be accomplished. These are discussed in the Input Coupling section.VSET is connected to VOUT to establish a feedback path that controls the overall scaling of the logarithmic amplifier. The load resistance, R L, should not be lower than 5 kΩ so that the full-scale output of 1.75 V can be generated with the limited available current of 400 µA max.As stated in the Absolute Maximum Ratings table, an externally applied overvoltage on the VOUT pin, which is outside the range 0 V to V POS, is sufficient to cause permanent damage to the device. If overvoltages are expected on the VOUT pin, a series resistor, R PROT, should be included as shown. A 500 Ω resistor is sufficient to protect against overvoltage up to ±5 V; 1000 Ω should be used if an overvoltage of up to ±15 V is expected. Since the output stage is meant to drive loads of no more than 400 μA, this resistor does not impact device perform-ance for higher impedance drive applications (higher output current applications are discussed in the Increasing Output Current section).Figure 29. Basic Connections for Log (RSSI) Mode OPERATING IN CONTROLLER MODEFigure 30 shows the basic connections for operation in controller mode. The link between VOUT and VSET is broken and a set-point is applied to VSET. Any difference between V SET and the equivalent input power to the AD8313 drives V OUT either to the supply rail or close to ground. If V SET is greater than the equivalent input power, V OUT is driven toward ground, and vice versa.Figure 30. Basic Connections for Operation in the Controller Mode This mode of operation is useful in applications where the output power of an RF power amplifier (PA) is to be controlled by an analog AGC loop (Figure 31). In this mode, a setpoint voltage, proportional in dB to the desired output power, is applied to the VSET pin. A sample of the output power from the PA, via a directional coupler or other means, is fed to the input of the AD8313.185-C-31Figure 31. Setpoint Controller OperationV OUT is applied to the gain control terminal of the power amplifier. The gain control transfer function of the power amplifier should be an inverse relationship, that is, increasing voltage decreases gain.A positive input step on V SET (indicating a demand for increased power from the PA) drives V OUT toward ground. This should be arranged to increase the gain of the PA. The loop settles when V OUT settles to a voltage that sets the input power to the AD8313 to the dB equivalent of V SET.。

1 MHz to 2.7 GHzRF Gain BlockAD8353 Rev. CInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © 2002–2009 Analog Devices, Inc. All rights reserved.FEATURESFixed gain of 20 dBOperational frequency of 1 MHz to 2.7 GHz Linear output power up to 9 dBmInput/output internally matched to 50 Ω Temperature and power supply stable Noise figure: 5.3 dBPower supply: 3 V or 5 VAPPLICATIONSVCO buffersGeneral Tx/Rx amplificationPower amplifier predriversLow power antenna drivers FUNCTIONAL BLOCK DIAGRAMRFINVPOSRFOUTCOM2 COM12721-1Figure 1.GENERAL DESCRIPTIONThe AD8353 is a broadband, fixed-gain, linear amplifier that operates at frequencies from 1 MHz up to 2.7 GHz. It is intended for use in a wide variety of wireless devices, including cellular, broadband, CATV, and LMDS/MMDS applications. By taking advantage of ADI’s high performance, complementary Si bipolar process, these gain blocks provide excellent stability over process, temperature, and power supply. This amplifier is single-ended and internally matched to 50 Ω with a return loss of greater than 10 dB over the full operating frequency range. The AD8353 provides linear output power of 9 dBm with 20 dB of gain at 900 MHz when biased at 3 V and an external RF choke is connected between the power supply and the output pin. The dc supply current is 42 mA. At 900 MHz, the output third-order intercept (OIP3) is greater than 23 dBm and is19 dBm at 2.7 GHz. The noise figure is 5.3 dB at 900 MHz. The reverse isolation (S12) is −36 dB at 900 MHz and −30 dB at 2.7 GHz.The AD8353 can also operate with a 5 V power supply; in which case, no external inductor is required. Under these conditions, the AD8353 delivers 8 dBm with 20 dB of gain at 900 MHz. The dc supply current is 42 mA. At 900 MHz, the OIP3 is greater than 22 dBm and is 19 dBm at 2.7 GHz. The noise figure is 5.6 dB at 900 MHz. The reverse isolation (S12) is −35 dB. The AD8353 is fabricated on ADI’s proprietary, high performance, 25 GHz, Si complementary, bipolar IC process. The AD8353 is available in a chip scale package that uses an exposed paddle for excellent thermal impedance and low impedance electrical connection to ground. It operates over a −40°C to +85°C temperature range, and an evaluation board is also available.AD8353Rev. C | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 13 Basic Connections ...................................................................... 13 Applications Information .............................................................. 14 Low Frequency Applications Below 100 MHz ........................... 14 Evaluation Board ............................................................................ 15 Outline Dimensions ....................................................................... 16 Ordering Guide .. (16)REVISION HISTORY3/09—Rev. B to Rev. CChanges to Lead Temperature (Soldering, 60 sec) Parameter, Table 3 ................................................................................................ 5 Changes to Ordering Guide . (16)12/05—Rev. A to Rev. BChanges to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Figure 16 ........................................................................ 9 Changes to Figure 32 ...................................................................... 11 Moved Figure 39 to Page 15; Renumbered Sequentially ........... 15 Changes to Ordering Guide . (16)8/05—Rev. 0 to Rev. AUpdated Format .................................................................. U niversal Changes to Product Title .................................................................. 1 Changes to Features, Figure 1, and General Description ............. 1 Changes to Table 1 ............................................................................. 3 Changes to Table 2 ............................................................................. 4 Changes to Figure 2 and Table 4 ...................................................... 6 Changes to Figure 3 caption and Figure 6 caption........................ 7 Changes to Figure 17 caption and Figure 20 caption ................... 9 Changes to Basic Connections Section ....................................... 13 Added Low Frequency Applications Below 100 MHz Section 14 Changes to Table 5 .......................................................................... 15 Changes to Ordering Guide .......................................................... 16 Updated Outline Dimensions ....................................................... 16 2/02—Revision 0: Initial VersionAD8353SPECIFICATIONSV S = 3 V, T A = 25°C, 100 nH external inductor between RFOUT and VPOS, Z O = 50 Ω, unless otherwise noted.Table 1.Parameter Conditions Min Typ Max Unit OVERALL FUNCTIONFrequency Range 1 2700 MHz Gain f = 900 MHz 19.8 dBf = 1.9 GHz 17.7 dBf = 2.7 GHz 15.6 dB Delta Gain f = 900 MHz, −40°C ≤ T A ≤ +85°C −0.97 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.15 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1.34 dB Gain Supply Sensitivity VPOS ± 10%, f = 900 MHz 0.04 dB/Vf = 1.9 GHz −0.004 dB/Vf = 2.7 GHz −0.04 dB/V Reverse Isolation (S12) f = 900 MHz −35.6 dBf = 1.9 GHz −34.9 dBf = 2.7 GHz −30.3 dBRF INPUT INTERFACE Pin RFINInput Return Loss f = 900 MHz 22.3 dBf = 1.9 GHz 20.9 dBf = 2.7 GHz 11.2 dBRF OUTPUT INTERFACE Pin RFOUTOutput Compression Point f = 900 MHz, 1 dB compression 9.1 dBmf = 1.9 GHz 8.4 dBmf = 2.7 GHz 7.6 dBm Delta Compression Point f = 900 MHz, −40°C ≤ T A ≤ +85°C −1.46 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.17 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1 dB Output Return Loss f = 900 MHz 26.3 dBf = 1.9 GHz 16.9 dBf = 2.7 GHz 13.3 dB DISTORTION/NOISEOutput Third-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 23.6 dBmf = 1.9 GHz, ∆f = 1 MHz, P IN = −28 dBm 20.8 dBmf = 2.7 GHz, ∆f = 1 MHz, P IN = −28 dBm 19.5 dBm Output Second-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 31.6 dBm Noise Figure f = 900 MHz 5.3 dBf = 1.9 GHz 6 dBf = 2.7 GHz 6.8 dB POWER INTERFACE Pin VPOSSupply Voltage 2.7 3 3.3 V Total Supply Current 35 41 48 mA Supply Voltage Sensitivity 15.3 mA/V Temperature Sensitivity −40°C ≤ T A ≤ +85°C 60 μA/°CRev. C | Page 3 of 16AD8353V S = 5 V, T A = 25°C, no external inductor between RFOUT and VPOS, Z O = 50 Ω, unless otherwise noted.Table 2.Parameter Conditions Min Typ Max Unit OVERALL FUNCTIONFrequency Range 1 2700 MHz Gain f = 900 MHz 19.5 dBf = 1.9 GHz 17.6 dBf = 2.7 GHz 15.7 dB Delta Gain f = 900 MHz, −40°C ≤ T A ≤ +85°C −0.96 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.18 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1.38 dB Gain Supply Sensitivity VPOS ± 10%, f = 900 MHz 0.09 dB/Vf = 1.9 GHz −0.01 dB/Vf = 2.7 GHz −0.09 dB/V Reverse Isolation (S12) f = 900 MHz −35.4 dBf = 1.9 GHz −34.6 dBf = 2.7 GHz −30.2 dB RF INPUT INTERFACE Pin RFINInput Return Loss f = 900 MHz 22.9 dBf = 1.9 GHz 21.7 dBf = 2.7 GHz 11.5 dB RF OUTPUT INTERFACE Pin RFOUTOutput Compression Point f = 900 MHz 8.3 dBmf = 1.9 GHz 8.1 dBmf = 2.7 GHz 7.5 dBm Delta Compression Point f = 900 MHz, −40°C ≤ T A ≤ +85°C −1.05 dBf = 1.9 GHz, −40°C ≤ T A ≤ +85°C −1.49 dBf = 2.7 GHz, −40°C ≤ T A ≤ +85°C −1.33 dB Output Return Loss f = 900 MHz 27 dBf = 1.9 GHz 22 dBf = 2.7 GHz 14.3 dB DISTORTION/NOISEOutput Third-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 22.8 dBmf = 1.9 GHz, ∆f = 1 MHz, P IN = −28 dBm 20.6 dBmf = 2.7 GHz, ∆f = 1 MHz, P IN = −28 dBm 19.5 dBm Output Second-Order Intercept f = 900 MHz, ∆f = 1 MHz, P IN = −28 dBm 30.3 dBm Noise Figure f = 900 MHz 5.6 dBf = 1.9 GHz 6.3 dBf = 2.7 GHz 7.1 dB POWER INTERFACE Pin VPOSSupply Voltage 4.5 5 5.5 V Total Supply Current 35 42 52 mA Supply Voltage Sensitivity 4.3 mA/V Temperature Sensitivity −40°C ≤ T A ≤ +85°C 45.7 μA/°CRev. C | Page 4 of 16AD8353Rev. C | Page 5 of 16ABSOLUTE MAXIMUM RATINGSTable 3.Parameter Rating Supply Voltage, VPOS 5.5 V Input Power (re: 50 Ω) 10 dBm Equivalent Voltage 700 mV rms Internal Power Dissipation Paddle Not Soldered 325 mW Paddle Soldered 812 mWθJA (Paddle Soldered) 80°C/WθJA (Paddle Not Soldered) 200°C/WMaximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) AD8353ACP (Non-RoHS Compliant) 240°C AD8353ACPZ (RoHS Compliant) 260°CStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTIONAD8353Rev. C | Page 6 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONSCOM1NC RFIN COM2COM1RFOUTVPOSCOM204862-002NC = NO CONNECTFigure 2. Pin ConfigurationTable 4. Pin Function DescriptionsPin No.Mnemonic Description1, 8 COM1 Device Common. Connect to low impedance ground. 2 NC No Connection.3 RFIN RF Input Connection. Must be ac-coupled.4, 5 COM2 Device Common. Connect to low impedance ground. 6 VPOS Positive Supply Voltage.7RFOUTRF Output Connection. Must be ac-coupled.AD8353Rev. C | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICS18015012090603033030027024021002721-003Figure 3. S 11 vs. Frequency, V S = 3 V, T A = 25°C, dc ≤ f ≤ 3 GHz02721-004G A I N (d B )FREQUENCY (MHz)Figure 4. Gain vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-005R E V E R S E I S O L A T I O N (d B )FREQUENCY (MHz)0–20–30–10–15–25–5–35–40Figure 5. Reverse Isolation vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C18015012090603033030027024021002721-006Figure 6. S 22 vs. Frequency, VS = 3 V, T A = 25°C, dc ≤ f ≤ 3 GHz02721-007G A I N (d B )FREQUENCY (MHz)151052025Figure 7. Gain vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°C02721-0085001000150020003000R E V E R S E I S O L A T I O N (d B )2500FREQUENCY (MHz)0–20–30–10–15–25–5–35–40Figure 8. Reverse Isolation vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°CAD8353Rev. C | Page 8 of 1602721-009500100015002000300025000FREQUENCY (MHz)P 1d B (d B m )Figure 9. P 1dB vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-010351045250402015305OUTPUT 1dB COMPRESSION POINT (dBm)P E R C E N T A G E (%)Figure 10. Distribution of P 1dB , V S = 3 V, T A = 25°C, f = 2.2 GHz02721-011O I P 3(d B m )FREQUENCY (MHz)26161412282010221824Figure 11. OIP3 vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-012500100015002000300025000FREQUENCY (MHz)P 1d B (d B m )Figure 12. P 1dB vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°C02721-013OIP3 (dBm)P E R C E N T A G E (%)19.119.519.920.320.721.121.521.9Figure 13. Distribution of OIP3, V S = 3 V, T A = 25°C, f = 2.2 GHz02721-014O I P 3 (d Bm )FREQUENCY (MHz)26161412282010221824Figure 14. OIP3 vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°CAD8353Rev. C | Page 9 of 1602721-015N O I S E F I G U R E (d B m )FREQUENCY (MHz)5.55.04.54.08.06.57.06.07.5Figure 15. Noise Figure vs. Frequency, V S = 2.7 V, 3 V, and 3.3 V, T A = 25°C02721-016P E R C E N T A G E (%)NOISE FIGURE (dB)103525302015Figure 16. Distribution of Noise Figure, V S = 3 V, T A = 25°C, f = 2.2 GHz02721-0171801501209060300330300270240210Figure 17. S 11 vs. Frequency, V S = 5 V, T A = 25°C, dc ≤ f ≤ 3 GHz 02721-018N O I S E F I G U R E (d B )FREQUENCY (MHz)5.55.04.54.08.08.56.57.06.07.5Figure 18. Noise Figure vs. Frequency, V S = 3 V, T A = −40°C, +25°C, and +85°C02721-019S U P P L Y C U R RE N T (m A )TEMPERATURE (°C)–6010504004530155040352520–40206080–20100Figure 19. Supply Current vs. Temperature, V S = 2.7 V, 3 V, and 3.3 V02721-020180150120906030330300270240210Figure 20. S 22 vs. Frequency, V S = 5 V, T A = 25°C, dc ≤ f ≤ 3 GHzAD8353Rev. C | Page 10 of 1602721-021G A I N (d B )FREQUENCY (MHz)Figure 21. Gain vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 25°C02721-022R E V E R S E I S O L A T I O N (d B )FREQUENCY (MHz)5001000150020002500–20–30–3530000–10–40–15–25–50 Figure 22. Reverse Isolation vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 25°C02721-023P 1d B (d B m )FREQUENCY (MHz)10Figure 23. P 1dB vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, TA = 25°C 02721-024G A I N (dB )FREQUENCY (MHz)Figure 24. Gain vs. Frequency, V S = 5 V, T A = −40°C, +25°C, and +85°C02721-025R E V E R S E I S OL A T I O N (d B )FREQUENCY (MHz)–20–30–350–10–40–15–25–5Figure 25. Reverse Isolation vs. Frequency, V S = 5 V, T A = −40°C, +25°C, and +85°C02721-026500100015002000300025000FREQUENCY (MHz)P 1d B (d B m )Figure 26. P 1dB vs. Frequency, V S = 5 V, T A = –40°C, +25°C, and +85°C02721-027351045250402015305OUTPUT 1dB COMPRESSION POINT (dBm)P E R C E N T A G E (%)7.07.27.47.88.28.48.68.08.87.6Figure 27. Distribution of P 1dB , V S = 3 V, T A = 25°C, f = 2.2 GHz02721-028FREQUENCY (MHz)O I P 3 (d B m )500100015002000250020161230002624101814220Figure 28. OIP3 vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 27°C02721-029N O I S E F I G U R E (d B )FREQUENCY (MHz)50010001500200025006.55.54.530009.08.04.06.05.07.08.57.50Figure 29. Noise Figure vs. Frequency, V S = 4.5 V, 5 V, and 5.5 V, T A = 25°C 02721-030OIP3 (dBm)P E R C E N T A G E (%)Figure 30. Distribution of OIP3, V S = 5 V, T A = 25°C, f = 2.2 GHz02721-031FREQUENCY (MHz)O I P 3 (d B m )500100015002000250020161230002624101814220Figure 31. OIP3 vs. Frequency, V S = 5 V, T A = –40°C, +25°C, and +85°C02721-032FREQUENCY (MHz)N O I S E F I G U R E (d B m )75109486Figure 32. Noise Figure vs. Frequency, V S = 5 V, T A = –40°C, +25°C, and +85°C02721-033P E R C E N T A G E (%)NOISE FIGURE (dB)10302515520Figure 33. Distribution of Noise Figure, V S = 5 V, T A = 25°C, f = 2.2 GHz02721-034S U P P L Y C U R R E N T (m A )TEMPERATURE (°C)10504004530155352520Figure 34. Supply Current vs. Temperature, V S = 4.5 V, 5 V, and 5.5 V 02721-035P O U T (d B m )G A I N (d B )P IN (dBm)5015–1510–5–10Figure 35. Output Power and Gain vs. Input Power, V S = 3 V, T A = 25°C, f = 900 MHz02721-036P O U T (d B m )G A I N (d B )P IN(dBm)–305015–1510–5–10Figure 36. Output Power and Gain vs. Input Power, V S = 5 V, T A = 25°C, f = 900 MHzTHEORY OF OPERATIONThe AD8353 is a 2-stage, feedback amplifier employing both shunt-series and shunt-shunt feedback. The first stage is degenerated and resistively loaded and provides approximately 10 dB of gain. The second stage is a PNP-NPN Darlington output stage, which provides another 10 dB of gain. Series-shunt feedback from the emitter of the output transistor sets the input impedance to 50 Ω over a broad frequency range. Shunt-shunt feedback from the amplifier output to the input of the Darlington stage helps to set the output impedance to 50 Ω. The amplifier can be operated from a 3 V supply by adding a choke inductor from the amplifier output to VPOS. Without this choke inductor, operation from a 5 V supply is also possible. BASIC CONNECTIONSThe AD8353 RF gain block is a fixed gain amplifier with single-ended input and output ports whose impedances are nominally equal to 50 Ω over the frequency range 1 MHz to 2.7 GHz. Consequently, it can be directly inserted into a 50 Ω system with no impedance matching circuitry required.The input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. A complete set of scattering parameters is available at .The input pin (RFIN) is connected directly to the base of the first amplifier stage, which is internally biased to approximately 1 V; therefore, a dc blocking capacitor should be connected between the source that drives the AD8353 and the input pin, RFIN. It is critical to supply very low inductance ground connections to the ground pins (Pin 1, Pin 4, Pin 5, and Pin 8) as well as to the backside exposed paddle. This ensures stable operation. The AD8353 is designed to operate over a wide supply voltage range, from 2.7 V to 5.5 V. The output of the part, RFOUT, is taken directly from the collector of the output amplifier stage. This node is internally biased to approximately 2.2 V when the supply voltage is 5 V. Consequently, a dc blocking capacitor should be connected between the output pin, RFOUT, and the load that it drives. The value of this capacitor is not critical, but it should be 100 pF or larger.When the supply voltage is 3 V, it is recommended that an external RF choke be connected between the supply voltage and the output pin, RFOUT. This increases the dc voltage applied to the collector of the output amplifier stage, which improves performance of the AD8353 to be very similar to the performance produced when 5 V is used for the supply voltage. The inductance of the RF choke should be approximately100 nH, and care should be taken to ensure that the lowest series self-resonant frequency of this choke is well above the maximum frequency of operation for the AD8353. For lower frequency operation, use a higher value inductor.Bypass the supply voltage input, VPOS, using a large value capacitance (approximately 0.47 μF or larger) and a smaller, high frequency bypass capacitor (approximately 100 pF) physically located close to the VPOS pin.The recommended connections and components are shown in Figure 40.APPLICATIONS INFORMATIONThe AD8353 RF gain block can be used as a general-purpose, fixed gain amplifier in a wide variety of applications, such as a driver for a transmitter power amplifier (see Figure 37). Its excellent reverse isolation also makes this amplifier suitable foruse as a local oscillator buffer amplifier that would drive the local oscillator port of an upconverter or downconverter mixer (see Figure 38).AD8353HIGH POWER AMPLIFIER02721-037Figure 37. AD8353 as a Driver Amplifier04862-038Figure 38. AD8353 as a LO Driver AmplifierLOW FREQUENCY APPLICATIONS BELOW 100 MHzThe AD8353 RF gain block can be used below 100 MHz. To accomplish this, the series dc blocking capacitors, C1 and C2, need to be changed to a higher value that is appropriate for the desired frequency. C1 and C2 were changed to 0.1 μF to accomplish the sweep in Figure 39.21.020.520.019.519.018.518.017.517.016.516.0CH 1: START 300.000kHz STOP 100.000MHzFigure 39. Low Frequency Application from300 kHz to 100 MHz at 5 V VPOS, −12 dBm Input PowerEVALUATION BOARDFigure 40 shows the schematic of the AD8353 evaluation board. Note that L1 is shown as an optional component that is used to obtain maximum gain only when V P = 3 V . The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by a 0.47 μF and a 100 pF capacitor.02721-03904862-040Figure 40. Evaluation Board SchematicTable 5. Evaluation Board Configuration OptionsComponent Function Default Value C1, C2 AC coupling capacitors. 1000 pF,0603 C3 High frequency bypass capacitor. 100 pF 0603 C4 Low frequency bypass capacitor. 0.47 μF, 0603 L1Optional RF choke, used to increasecurrent through output stage when V P = 3 V. Not recommended for use when V P = 5 V.100 nH, 0603Figure 41. Silkscreen Top04862-041Figure 42. Component SideOUTLINE DIMENSIONS031207-AFigure 43. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]2 mm ×3 mm Body, Very Thin, Dual LeadCP-8-1Dimensions shown in millimetersORDERING GUIDEModel Temperature Range Package Description Package OptionBranding AD8353ACP-R2 −40°C to +85°C 8-Lead LFCSP_VDCP-8-1 JB AD8353ACP-REEL7 −40°C to +85°C 8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 JB AD8353ACPZ-REEL71 −40°C to +85°C8-Lead LFCSP_VD, 7" Tape and Reel CP-8-1 0EAD8353-EVALZ 1Evaluation Board1Z = RoHS Compliant Part.© 2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02721-0-3/09(C)。

High performance in a small packageUtilize the Agilent Technologies 83557A/83558A mm-wave source modules to obtain high power, high quality signals covering the full wave-guide bands of 50 to 75 GHz (V band) and 75 to 110 GHz (W band). These efficient frequency multipliers trans-late a 50 mW (+17 dBm) microwave signal (12.5 to 18.75 GHz) to a mm-wave signal at a very low cost com-pared to other alternatives. With their reliable, solid state design, these modules are small and lightweight and can be operated remotely from the driving source to better accomo-date your measurement setup needs. High output powerWith >+2 dBm to 75 GHz and >-1 dBm to 110 GHz, these mm-wave source modules can be used as LO’s in mixer measurements and provide additional dynamic range for insertion loss/gain measurements. The output power is leveled to provide level control and improved source match at the device under test. Additionally, the output power level can be read from the front of the source, or on the 8349B ampli-fier, depending on your configuration.Spectral purityThe 83557A/83558A source modulesoffer harmonic and sub-harmonicsuppression of <-20 dBc when usedwith low harmonic sources like the8360 series synthesized sweeper, the8673C/D synthesized signal generators,or the standard 8350B/83550A sweeposcillator. In many mm-wave measure-ments, low harmonics are importantto achieve greater measurement accu-racy and increased dynamic range.Dedicated sources simplifyconnectionsUse the 83623A synthesized sweeperor the 8350B/83550A sweep oscillatorto drive these source modules directlywithout requiring an external amplifier.With a dedicated source moduleinterface, these sources display boththe frequency and the power level atthe module’s output. Or, choose froma wide range of sources to drive thesource modules using an 8349Bmicrowave amplifier. The 8350Bsweep oscillator makes an excellent,low-cost, swept source. For increasedfrequency accuracy and stability, usethe 8360 series synthesized sweepers,the 8340/41 series synthesized sweep-ers, or the 8673 series synthesizedsignal generators.Swept V/W band network analysisWith the 8757 scalar network analyzer,or the 8510 vector network analyzer,complete V and W band measurementsystems can be configured using the8350B, 8360 series, or 8340B/8341Bmicrowave sweepers and the mm-wavesource modules. Using the 8757,simultaneous scalar reflection andtransmission measurements can bemade in waveguide. With the 8510,full S-parameter measurements canbe made using two microwave sourcesand the 83557A/83558A mm-wavemodules.Agilent 83557A/83558A50 to 75 GHz/75 to 110 GHzmm-Wave Source ModulesTypical maximum leveled output power for V and W band mm-wave source modulesSpecificationsSpecifications describe the instrument’s warranted performance over the temperature range 0°to 55°C (except where noted). Supplemental characteristics are intended to provide information useful in applying the instrument by giving typical but non-warranted performance parameters. These are denoted as “typical,” “nominal,” or “approximately.”8350B/83550A or8350B/83592C/95C8341B Opt. 00318673C/D1Agilent 83557A 50-75 GHz8349B83623A or 83624A8349B8349BLeveled Power Range(25 ±5 °C)–5 to +2 dBm–5 to +3 dBm–5 to +2 dBm–5 to +2 dBm Unleveled(Opt. 001)–5 to +4 dBm–5 to +4 dBm–5 to +4 dBm–5 to +4 dBm Power Level Accuracy(25 ±5 °C)±2.5 dB±2.0 dB±2.5 dB±2.5 dBPower Flatness(Max Leveled Power)±2.0 dB±1.5 dB±2.0 dB±2.0 dBSource Output SWRLeveled 2.0 2.0 2.0 2.0Unleveled(Typically) 3.0 3.0 3.0 3.0Spurious Signals2–20 dBc–20 dBc–20 dBc–20 dBc8350B/83550A or8350B/83592C/95C8341B Opt. 00318673C/D1Agilent 83558A 75-110 GHz8349B83623A or 83624A8349B8349BLeveled Power Range(25 ±5 °C)–5 to –1 dBm–5 to 0 dBm–5 to –1 dBm–5 to –1 dBm Unleveled(Opt. 001)–5 to +1 dBm–5 to +1 dBm–5 to +1 dBm–5 to +1 dBm Power Level Accuracy(25 ±5 °C)±2.5 dB±2.0 dB±2.5 dB±2.5 dBPower Flatness(Max Leveled Power)±2.0 dB±1.5 dB±2.0 dB±2.0 dBSource Output SWRLeveled 2.0 2.0 2.0 2.0Unleveled(Typically) 3.0 3.0 3.0 3.0Spurious Signals–20 dBc–20 dBc–20 dBc–20 dBc Common SpecificationsFrequency Accuracy, Resoluton, and Stability4(83557A) or 6 (83558A) times the frequency accuracy, resolution, and stability of the input signal.Accuracy is the same as the time base for synthesized sources.External Pulse Modulation On/Off Ratio>80 dB>80 dB>80 dB>80 dB(>60 dB for 83550A)Rise/Fall Time (Typically)10 ns50 ns50 ns40 ns(25 ns for 83550A)Min Leveled RF Pulse Width (Typically) 1 µs 1 µs 1 µs 1 µsAmplitude ModulationRate (3 dB BW) (Typically)DC – 100 kHz DC – 250 kHz DC – 100 kHz DC – 100 kHz Sensitivity (Typically) 1 dB/V(100%/V, for synthesized sources)1.Specifications apply for low harmonic sources only. The standard 8340B/8341B and the 8673B/G/H also provide the same source capabilities except the spurious output of themodules is at 0 dBc.2.Expressed in dB relative to the carrier (dBc)2General SpecificationsInput Frequencies12.5 to 18.75 GHzMinimum input power level into RF input cable+17 dBm (50 mW)Maximum input power level into RF input cable+27 dBm (0.5 W)Waveguide output connector 83557A EIA size WR-15 waveguide. Mates withJAN UG 385 flange.83558EIA size WR-10 waveguide. Mates withJAN UG387 (mod.) flange.Weight Net, 1.8 kg (4 lb.)Ordering InformationAgilent 83557A 50 to 75 GHz mm-Wave Source ModuleOption 001Deletes Leveling Coupler and DetectorOption 910Extra ManualOption W30Two Additional Years of Return-to-Agilent ServiceAgilent 83558A 75 to 110 GHz mm-Wave Source ModuleOption 001Deletes Leveling Coupler and DetectorOption 910Extra ManualOption W30Two Additional Years of Return-to-Agilent ServiceAgilent 8349B 2.0 to 20.0 GHz Microwave AmplifierOption 001Rear Panel RF Input/OutputOption 002Rear Panel RF Input and Front Panel OutputOption 910Extra ManualOption W30Two Additional Years of Return-to-Agilent ServiceFurnished with each 83557A Part numberOperating and Service Manual83557-90019Procedure and Parts for 8340 Series/83590 Series0.5 V/GHz Modification83557-90016RF Cable5061-5359Source Module Interface 5061-5391Module Base Assembly 83557-60010Furnished with each 83558A Part numberOperating and Service Manual83558-90019Procedure and Parts for 8340 Series/83590 Series0.5 V/GHz Modification83558-90016RF Cable5061-5359Source Module Interface 5061-5391Module Base Assembly 83558-600103Agilent Technologies’ Test and Measurement Support, Services, and AssistanceAgilent Technologies aims to maximize the value you receive, while minimizing your risk and problems. We strive to ensure that you get the test and measure-ment capabilities you paid for and obtain the support you need. Our extensive sup-port resources and services can help you choose the right Agilent products for your applications and apply them successfully. Every instrument and system we sell has a global warranty. Support is available for at least five years beyond the produc-tion life of the product. Two concepts underlie Agilent’s overall support policy:“Our Promise” and “Your Advantage.”Our Promise“Our Promise” means your Agilent test and measurement equipment will meet its advertised performance and functionality. When you are choosing new equipment, we will help you with product informa-tion, including realistic performance spec-ifications and practical recommendations from experienced test engineers. When you use Agilent equipment, we can verifythat it works properly, help with productoperation, and provide basic measurementassistance for the use of specified capabil-ities, at no extra cost upon request. Manyself-help tools are available.Your Advantage“Your Advantage” means that Agilentoffers a wide range of additional experttest and measurement services, which youcan purchase according to your uniquetechnical and business needs. Solve prob-lems efficiently and gain a competitive edgeby contracting with us for calibration,extra-cost upgrades, out-of-warranty repairs, andon-site education and training, as wellas design, system integration, project man-agement, and other professional services.Experienced Agilent engineers and techni-cians worldwide can help you maximizeyour productivity, optimize the return oninvestment of your Agilent instruments andsystems, and obtain dependable measure-ment accuracy for the life of those products.By internet, phone, or fax, get assistancewith all your test and measurement needs.Online Assistance/find/assistPhone or FaxUnited States:(tel)180****4844Canada:(tel)187****4414(fax) (905) 206 4120Europe:(tel) (31 20) 547 2323(fax) (31 20) 547 2390Japan:(tel) (81) 426 56 7832(fax) (81) 426 56 7840Latin America:(tel) (305) 269 7500(fax) (305) 269 7599Australia:(tel) 1 800 629 485(fax) (61 3) 9272 0749New Zealand:(tel) 0 800 738 378(fax) (64 4) 495 8950Asia Pacific:(tel) (852) 3197 7777(fax) (852) 2506 9284Product specifications and descriptions in thisdocument subject to change without notice.Copyright © 1989, 2000 Agilent TechnologiesPrinted in U.S.A. 8/005958-0398。

精心整理在DDS的基础上，完成AM、FM、ASK、FSK调制标准调幅波信号v AM(t)=V cm(1+m a cosΩt)cosωc t实现AM电路结构图（假设V cm=1）乘法器：采用模拟乘法器AD835作为信号的调制和解调单元。

AD835是一款电压输X、W=Z1决定，调节电位器可实现增益微调。

D/A的芯片转换器使输入8位D/AD/A转换器双极性输出电路D0～D7：8位数据输入线，TTL电平，有效时间应大于90ns(否则锁存器的数据会出错)；ILE：数据锁存允许控制信号输入线，高电平有效；CS：片选信号输入线（选通数据锁存器），低电平有效；WR1：数据锁存器写选通输入线，负脉冲（脉宽应大于500ns）有效。

由ILE、CS、WR1的逻辑组合产生LE1，当LE1为高电平时，数据锁存器状态随输入数据线变换，LE1的负跳变时将输入数据锁存；精心整理XFER ：数据传输控制信号输入线，低电平有效，负脉冲（脉宽应大于500ns ）有效；WR2：DAC 寄存器选通输入线，负脉冲（脉宽应大于500ns ）有效。

由WR1、XFER 的逻辑组合产生LE2，当LE2为高电平时，DAC 寄存器的输出随寄存器的输入而变化，LE2的负跳变时将数据锁存器的内容打入DAC 寄存器并开始D/A 转换。

IOUT1：电流输出端1，其值随DAC 寄存器的内容线性变化；IOUT2：电流输出端2，其值与IOUT1值之和为一常数；Rfb ：反馈信号输入线，改变Rfb 端外接电阻值可调整转换满量程精度；VCC ：电源输入端，Vcc 的范围为+5V ～+15V ；VREF AGND DGND D/A FM 1 决定，。