将8421BCD转换为余3码源代码：
Library ieee;
Use ieee.std_logic_1164.all;
Entity bcd is
Port(a:in std_logic_vector(3 downto 0);
y:out std_logic_vector(3 downto 0));
End;
Architecture rtl of bcd is
Begin
Process(a)
Begin
Case a is
When"0000"=>y<="0011";
When"0001"=>y<="0100";
When"0010"=>y<="0101";
When"0011"=>y<="0110";
When"0100"=>y<="0111";
When"0101"=>y<="1000";
When"0110"=>y<="1001";
When"0111"=>y<="1010";
When"1000"=>y<="1011";
When"1001"=>y<="1100";
When others=>y<="ZZZZ";
End case;
End process;
End;
仿真图形：
（仿真结果均有延时，大约20ns）
四输入表决器
源代码：
Library ieee;
Use ieee.std_logic_1164.all;
Entity bjq is
Port(i:in std_logic_vector(3 downto 0);
f:out std_logic);
End;
Architecture nm2 of bjq is
Begin
Process(i)
Begin
case i is
When"0000"=>f<='0';
When"0001"=>f<='0';
When"0010"=>f<='0';
When"0011"=>f<='0';
When"0100"=>f<='0';
When"0101"=>f<='0';
When"0110"=>f<='0';
When"0111"=>f<='1';
When"1000"=>f<='0';
When"1001"=>f<='0';
When"1010"=>f<='0';
When"1011"=>f<='1';
When"1100"=>f<='0';
When"1101"=>f<='1';
When"1110"=>f<='1';
When"1111"=>f<='1';
When others=>f<='Z';
End case;
End process;
End;
仿真图形：
2位二进制相乘电路源代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity multi is
port(A,B:in std_logic_vector(1 downto 0);
F:out std_logic_vector(3 downto 0));
end;
architecture bhv of multi is
begin
process(A,B)
begin
if(A="01" and B="01" )then
F<="0001";
elsif(A="01" and B="10")then
F<="0010";
elsif(A="01" and B="11")then
F<="0011";
elsif(A="10" and B="01")then
F<="0010";
elsif(A="10" and B="10")then
F<="0100";
elsif(A="10" and B="11")then
F<="0110";
elsif(A="11" and B="01")then
F<="0011";
elsif(A="11" and B="10")then
F<="0110";
elsif(A="11" and B="11")then
F<="1001";
else
F<="0000";
end if;
end process;
end;
仿真图形：
一位二进制全减器源代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity subtracter is
port(A,B,Ci:in std_logic;
F,Co:out std_logic);
end;
architecture bhv of subtracter is
begin
process(A,B,Ci)
begin
if(A='0' and B='0' and Ci='0')then
F<='0';
Co<='0';
elsif(A='0' and B='0' and Ci='1')then
F<='1';
Co<='1';
elsif(A='0' and B='1' and Ci='0')then
F<='1';
Co<='1';
elsif(A='0' and B='1' and Ci='1')then
F<='0';
Co<='1';
elsif(A='1' and B='0' and Ci='0')then
F<='1';
Co<='0';
elsif(A='1' and B='0' and Ci='1')then
F<='0';
Co<='0';
elsif(A='1' and B='1' and Ci='0')then
F<='0';
Co<='0';
else
F<='1';
Co<='1';
end if;
end process;
end;
仿真图形：
开关控制电路
