SoC设计 DFT 分析

Scan chain technique MBIST Boundary Scan
Verification vs. Test
• • • •
Verifies correctness of design. Performed by simulation, hardware emulation, or formal verification, etc. Performed once prior to manufacturing. Responsible for quality of design.
• Fault models are typically defined
on a structure basis

• Typical fault models

Different fault models for digital logic, memories and analog circuit Single stuck-at faults Transistor open/short faults Bridging faults Delay faults Memory faults Analog faults
Test Challenges
• Reduce the cost of test


• Increase the defect coverage

Reduce Reduce Reduce Reduce
the the the the
vector data size tester sequencing complexity cost of test equipment test time
Package • BGA • QFP • PGA • TAB • CSP • SIP • MCM • ...
Coverage • DC • AC • Digital • Analog • Speed • Temp • Power • ...
Qualification • Burn-in • Temp-Cycle • HVST • ESD • Latch-up • ...
Verification
• •
• •
Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.
(ATPG) • Design-for-test (DFT)

Scan
Fault Coverage
• Fault coverage

The percentage of total faults for which test patterns have been generated
Number of Detected Faults
Fault Coverage = 100 X
Total Number of Faults in the CUT
• Fault coverage is influenced by

Testability of the circuit Quality of applied patterns
Test Generation Definitions

Typically critical path
Memory Faults
Stuck-AT- 0 0
1
Stuck-AT- 1
OR Bridging Transition / 0 Reset Coupling Inversion Coupling
1 0 1 1
1
0
0 AND Bridging 1 Transition /1
Defect & Fault Modeling Definition
• Defect: Physical abnormally fabricated die • Fault: behavior difference due to a defect • Error: machine failure due to a fault
Design
Wafer Fabrication
Class Probe
Die Sort Probe
Die Assembly
Final Test
Reliability Stress
Parameter • VtP • VtN • IgS • IdS • Leff • Weff • Res • ...
Coverage • leakage • memory • Core • ...
《SoC设计方法与实现》
郭炜 郭筝 谢憬
第十章
可测试性设计
Outlines
• Overview of IC Testing • Fault Modeling • Automatic Test Pattern Generation
(ATPG) • Design-for-test (DFT) techniques
How many function test patterns can cover all the devices?
Outlines
• Overview of IC Testing • Fault Modeling • Automatic Test Pattern Generation
(ATPG) • Design-for-test (DFT) techniques
AdrE
AdrE
AdrE
AdrE
AdrE
Memory Fault – cont.
• Neighborhood pattern sensitive fault
Outlines
• Overview of IC Testing • Fault Modeling • Automatic Test Pattern Generation
Stuck-AT Faults
• What is stuck-at fault?


Applicable to any physical defect manifesting as a signal that is stuck at a fixed logic level One stuck-at fault can model more than one kind of dra material
E.g. input stuck-at „1‟, output slow-to-rise
E.g. system functional failure
• Bug – functional failure caused by design
problem
• Fault Model Derived

Why Model Faults?
• Fault model identifies target faults • Fault model makes analysis possible • Effectiveness measurable by
experiments
With the build-in DFT circuit, test vectors are generated automatically
Vector Generation Using ATPG Tool
• • •
Read in netlist with scan chain connected Read in IP and standard-cell library model Read in STIL test protocol file, generated by DFT compiler tool. (STIL - Standard Test Interface Language for Digital Test Vectord, IEEEStd. 1450.01999) Check DRC and make any necessary corrections Prepare design for ATPG, setup fault list, analyze buses for contention and set the ATPG options Generate vectors Review the test coverage and re-run ATPG if necessary Compress the vectors Convert vector to ATE vector format Save test vectors and fault list
Test
Testing Principle
• Three basic element

A known input Stimulus
A known state

A known expected response
Automatic Test Equipment (ATE)
Overview of IC Testing
0 0
1 0
1 1
Set Coupling Inversion Coupling
Passive Neighborhood Pattern Sensitive
0
1 1 1 1 1
1
0 1 0
Active Neighborhood Pattern Sensitive
Various Faults With Address Decoder

Path Delay Fault
• It models defects in circuit path • Unlike transition delay fault, path delay •
faults do not have localized fault sites. Associated with testing the AC performance of specific paths


E.g. system functional failure
Example
a b
c
• Defect: short to the grand • Fault: signal b stuck at logic 0 • Error: happens when a=1 b=1
Fault Models
Transition Delay Fault
• Model large transition delay
•
slow to rise or slow to fall transition an interconnect signal has a greater than normal propagation delay associated with it The model behaves as stuck at fault for a certain period of time
Types of Test Vector Sets
• Exhaustive

• Functional

Apply every possible input vector A long time! Test every function of the device How to guarantee the coverage? Find a test for every “modeled” fault Industry practice currently
Test vectors

• Automatic test pattern generation

An input vector for the circuit-under-test that causes the presence of a fault to be observable at a primary output