第三次HDL实验报告八位计数器、八位比较器
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Verilog HDL实验报告
Verilog 实验报告题目:八位计数器、八位比较器系部名称:通信工程
专业名称:通信工程
班级:
班内序号:
学生姓名:
时间:2010.12.2
一、八位计数器:
源代码:
module counter_8(q,clk,clr);
output [7:0] q;
input clk,clr;
reg [7:0] q;
always @(posedge clr or negedge clk) begin
if (clr)
q<=8'd0;
else
q<=q+1;
end
endmodule
测试程序:
module counter_8_test;
reg clk;
reg clr;
wire [7:0] q;
counter_8 j1(q,clk,clr);
initial
clk=1'b0;
always
#5 clk=~clk;
initial
begin
clr=1'b1;
#15 clr=1'b0;
#100 clr=1'b1;
#10 clr=1'b0;
end
initial
begin
#500 $finish;
end
initial
$monitor($time," q=%d",q);
endmodule
测试图形:
二、八位比较器:
源代码:
module compare(A,B,Fb,Fe,Fl);
input [8:0]A,B;
output Fb,Fe,Fl;
reg Fb,Fe,Fl;
initial Fb=0;
initial Fe=0;
initial Fl=0;
always @(A or B)
begin
if(A[1:0]>B[1:0])
Fb=1;
if(A[1:0]==B[1:0])
Fe=1;
if(A[1:0]
Fl=1;
else Fb=0 ;Fe=0; Fl=0;
end
endmodule
测试程序:
module compare_test;
reg [8:0]A,B;
wire Fb,Fe,Fl;
compare sti(.A(A),.B(B),.Fb(Fb),.Fe(Fe),.Fl(Fl));
initial
begin
#10 A=8'd0;B=8'd1;
#10 A=8'd2;B=8'd2;
#10 A=8'd5;B=8'd1; #10 A=8'd15;B=8'd10; #10 A=8'd10;B=8'd3; #10 A=8'd6;B=8'd6; #10 A=8'd8;B=8'd14; #10 A=8'd12;B=8'd12; # 20 $finish;
end
endmodule
测试图形: