摘 要随着电路系统数字化程度的不断提高，尤其是片上系统（SOC）的快速发展，作为连接模拟信号与数字信号的桥梁的高性能模数转换器的需求日益增强。
与其它结构相比，流水线ADC因其在高精度、高速度与低功耗之间拥有良好的折中而备受青睐。
本文采用韩国东部半导体dongbu013工艺，设计研究了一个50MSample/s的12位的流水线ADC。
在查阅大量文献的前提下，本文根据模拟IC设计流程，以高速、低压、低功耗为目标，逐步完成了各个模块电路以及整体电路的设计。
主要工作包括：（1）完成两相不交叠时钟电路的设计；自举开关电路（为消除开关电荷注入误差）设计；为保证开关电容电路的速度和精度设计了增益增强型折叠共源共栅运算放大器；动态锁存比较器电路设计。
（2）由单元电路完成各个子模块电路的设计，并对各个模块和整体系统进行详细仿真。
（3）为降低功耗采用电容和运算放大器逐级递减技术，为克服比较器失调误差设计了数字校正电路。
本设计在Cadence工作平台下，使用Spectre仿真器进行模拟验证。
模拟仿真结果表明，在+1.2V电源电压下，ADC的模拟信号输入范围为0.4V～0.8V，分辨率为12位，采样速率达50MHz，功耗约为84mW。
该流水线ADC的性能指标达到了设计要求。
关键词：流水线ADC；自举开关；开关电容电路；数字校正AbstractAs a bridge connecting the analog signal and digital signal, the demand of the high-performance analog-to-digital converter has growing rapidly with the digitalization of the circuit system, especially the rapid development of the system on chip. Compared with other structures, the pipeline ADC has a good favor because of its good compromise between the high resolution, high speed and low power consumption. In this thesis, a 50MSPS, 12bit ADC was designed in dongbu 0.13um process.Access to a large number of documents, this paper completes the design of each module circuit and the overall circuit step by step with the goal of high speed, low voltage and low power consumption, according to the Analog IC design flow. The main work of this paper is as follows. Firstly, completing the circuit design of the two-phase non-overlapping clock generator; the bootstrapped switch, which can eliminate the switch charge injection error; the gain enhanced folded cascode operational amplifier, which can ensure the speed and accuracy of the switch capacitor circuits, and the dynamic latch comparator. Secondly, completing the circuit design of each sub-module by the unit circuit, and simulating each module and the overall system in detail. Thirdly, in order to reduce the power consumption of the system, scaling down technique of the capacitor and operation amplifier was used, and a digital calibration circuit was designed to overcome the comparator offset error.This design works in the Cadence platform, the simulating tool is Cadence Spectre. The simulating results show that, with a power supply of 1.2V, the input voltage range of the ADC is between 0.4V and 0.8V, its resolution is 12 bits and sample rate is 50MHz, the power consumption is about 84mW. The parameters of this pipeline ADC meet the design requirements.Keywords： pipeline ADC, bootstrapped switch, switch capacitor circuit, digital calibration目录摘要 (I)Abstract (II)第一章绪论 (1)1.1课题研究的背景及意义 (1)1.2国内外研究现状 (1)1.3本文主要研究内容和结构安排 (4)第二章流水线ADC的基本原理 (5)2.1模数转换器的基本概念 (5)2.2模数转换器的性能参数 (5)2.3流水线ADC的结构和工作原理 (7)2.4非线性因素及其影响 (8)2.4.1热噪声 (8)2.4.2电荷注入和时钟馈通 (10)2.4.3运放有限开环增益和带宽 (12)2.5数字校正技术 (13)2.6本章小结 (15)第三章流水线ADC单元电路的分析与设计 (16)3.1MOS开关电路 (16)3.2运算放大器 (19)3.2.1增益增强原理 (19)3.2.2主运放和共模反馈电路设计 (21)3.2.3辅助运放设计 (23)3.2.4最终放大器电路验证 (25)3.3比较器 (27)3.4本章小结 (30)第四章模块和系统电路设计与仿真 (31)4.1C LOCK G ENERATOR (31)4.2采样保持电路 (33)4.3 1.5BIT/STAGE ADC (37)4.3.1Sub-ADC (37)4.3.2Sub-DAC (39)4.3.3Gain-stage (41)4.4数字校正电路 (43)4.5本章小结 (45)总结 (46)参考文献 (47)哈尔滨工业大学硕士学位论文原创性声明 (51)哈尔滨工业大学硕士学位论文使用授权书 (51)致谢 (52)第一章 绪 论1.1课题研究的背景及意义现实世界中的物理量大部分是随时间连续变化的量，即大都是模拟量，如光、电、声音、速度等[1]。
