专业英语翻译的作业

0-7803-7463-X/02/$17.00 (C) 2002 IEEE
DEVICE FABRICATION
The process flow for fabricating the Ω-FET is illustrated in Figure 2, which is similar to that reported for 35 nm gate length CMOS FinFETs [7], except for the following major differences: (1) the gate oxide thickness is decreased from 24 Å down to 17-19 Å, (2) the oxide cap on the transistor body is removed along with the undercutting of buried oxide under Si body before gate dielectric formation, and (3) different gate material and channel/source/drain doping conditions for the 1 volt version and the 0.7 volt version devices.
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Transistor Gate Length, Lg (nm)
Figure 1. Silicon body thickness (Tsb) versus transistor gate length (Lg). The solid lines for UTB-SOI or DST and double-gate FinFET are derived from [9]. The dashed line for the Ω -FET, as schematically illustrated in Figures 2 and 3, is extrapolated from this experimental work. Table I. Improvement of channel controllability by the gate using various transistor structures. Better gate control will allow the use of thicker silicon body thickness Tsb.
Very recently, the development of ultra-thin-body SOI (UTB-SOI) [2][3] or depleted-substrate transistors (DST) [4], and double-gate FinFETs [5]-[8] have attracted increasing interest for their integrated process not far from conventional planar bulk devices, and with the potential advantages of higher drive current, better short-channel-effect control, and/or less Drain Induced Barrier Lowering (DIBL). Both of these transistor structures need thin silicon body thickness (Tsb), ~ Lg/3 for UTB-SOI or DST, and ~ 2Lg/3 for FinFET, to have the aforementioned advantages. Figure 1 shows the required Tsb for the corresponding Lg. In general, increased Tsb can be realized under better gate control. In Table I, we show the improvement of the transistor gate control over the channel potential when transistor structure goes from UTB-SOI to double-gate FinFET, triple-gate MOSFET, Pi(π)-gate MOSFET [10], to the gate-all-around or surround-gate MOSFET [11][12]. The gate-all-around MOSFET offers the best gate control but suffers from process complexity and implementation difficulties. In this paper, we report a new transistor structure, called Omega (Ω) FET, which has the closest resemblance to the Gate-All-Around transistor for excellent scalability, and uses a very manufacturable process similar to that of the FinFET. The Ω-FET, schematically illustrated in Figures 2 and 3, has a top gate like the conventional UTB-SOI or DST, sidewall gates like FinFETs, and special gate extensions under the silicon body. The Ω-FET is a field effect transistor with a gate that almost wraps around the body. In fact, the longer the gate extension, the more the structure approaches the gate-all-around structure [11],[12]. The gate extension as well as the top-gate allow the use of a larger Tsb. The gate extension of Ω-FET not only plays the role of shielding electric field lines from the drain for decreasing DIBL, but also improves gate-to-channel controllability.
Silicon Body Thickness, Tsb (nm)
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UTB-SOI or DST Double-Gate FinFET Ω-FET
This work
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T FE Ω-
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e gat ble T u o D nFE Fi
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Leabharlann Baidu
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r DST SOI o UTB[2]
Device Structure UTB-SOI or DST FinFET Triple-Gate MOSFET Pi (π)-Gate MOSFET Ω-FET (This work) Gate-All-Around MOSFET 4 Number of Gates 1 2 3
INTRODUCTION
Abstract Low leakage and low active-power 25 nm gate length CMOSFETs are demonstrated for the first time with a newly proposed Omega-(Ω) shaped structure, at a conservative 1719 Å gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 µA/µm and 780 µA/µm with off state leakage currents of 8 nA/µm and 0.4 nA/µm for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 µA/µm for N-FET and 550 µA/µm for P-FET at an off current of 1 µA/µm. N-FET gate delay (CV/I) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections [1].
25 nm CMOS Omega FETs
Fu-Liang Yang, Hao-Yu Chen, Fang-Cheng Chen, Cheng-Chuan Huang, Chang-Yun Chang, Hsien-Kuang Chiu, Chi-Chuang Lee, Chi-Chun Chen, Huan-Tsung Huang, Chih-Jian Chen, Hun-Jan Tao, Yee-Chia Yeo, Mong-Song Liang, and Chenming Hu Taiwan Semiconductor Manufacturing Company, No. 6, Li-Hsin Rd. 6, Science-Based Industrial Park, Hsin-Chu, TAIWAN, ROC Phone: 886-3-6665152, Email: flyang@tsmc.com.tw
The Ω-FET, with the aid of top gate and bottom gate extension, can then accept Tsb up to ~ Lg from ~ 2Lg/3 for the FinFET. With the undercutting of the buried oxide, the Ω-FET also resembles the Pi-gate SOI MOSFET structure, which is essentially a triple-gate structure with the gate extending vertically into the buried oxide [10]. The significant body thickness increase will not only decrease body thickness sensitivity, but also reduce parasitic resistance which has been widely addressed for noticeable performance degradation [4],[6],[9],[13]. Thus, the introduction of raised source/drain technology may be postponed. Furthermore, as Tsb does not need to be smaller than Lg for the Ω-FET, there is no need to pattern features smaller than Lg.